JP4429760B2 - 多層配線基板 - Google Patents
多層配線基板 Download PDFInfo
- Publication number
- JP4429760B2 JP4429760B2 JP2004044306A JP2004044306A JP4429760B2 JP 4429760 B2 JP4429760 B2 JP 4429760B2 JP 2004044306 A JP2004044306 A JP 2004044306A JP 2004044306 A JP2004044306 A JP 2004044306A JP 4429760 B2 JP4429760 B2 JP 4429760B2
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- Prior art keywords
- wiring
- pads
- layer
- pad
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- 239000010410 layer Substances 0.000 claims description 149
- 239000000758 substrate Substances 0.000 claims description 19
- 239000011229 interlayer Substances 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 description 19
- 238000000034 method Methods 0.000 description 9
- 238000000605 extraction Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Description
11…コア基板、
12…配線層、
13…層間絶縁層、
P,P0,P1〜P4…パッド、
PR1,PR2,PR3…パッド配置領域、
TH…スルーホール、
VH…ビアホール、
WP…配線パターン。
Claims (1)
- 搭載する電子部品の電極の配置に対応させて格子状に配列された複数のパッドと、それぞれ一端が前記複数のパッドのうちいずれか1つのパッドに接続され、他端が前記パッドが配置された領域内から外側に引き出されて形成された複数の配線パターンとを有する配線層が、コア基板の両方の面側にそれぞれ層間絶縁層を介して積層された多層配線基板であって、
前記電子部品が搭載される第1層目の配線層において、前記パッドが配置された領域で最外周に配置された全てのパッドと、当該領域の隅部の近傍で対角線上に配置されたパッドと、当該領域の内側で各列上に配置されたパッドのうち隣り合う列間で斜め方向に位置する各パッドとからそれぞれ配線パターンが引き出され、
第2層目の配線層において、前記第1層目の配線層で配線パターンが引き出されていないパッドにビアホールを介して電気的に接続されたパッドのうち、当該パッドが配置された領域で最外周に配置された全てのパッドと、当該領域の内側で各列上に配置されたパッドのうち隣り合う列間で斜め方向に位置する各パッドとからそれぞれ配線パターンが引き出され、
前記コア基板を挟んで前記第1層目、第2層目の配線層と反対側の配線層において、前記第2層目の配線層で配線パターンが引き出されていないパッドにビアホール及び前記コア基板に形成されたスルーホールを介して電気的に接続されたパッドのうち、当該パッドが配置された領域で最外周に配置された全てのパッドと、当該領域の内側で各列上に配置されたパッドのうち隣り合う列間で斜め方向に位置する各パッドと、隣り合う列間で横方向に、前記スルーホールの直径以上の値に選定された距離だけ離れて位置する各パッドとからそれぞれ配線パターンが引き出されていることを特徴とする多層配線基板。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004044306A JP4429760B2 (ja) | 2004-02-20 | 2004-02-20 | 多層配線基板 |
US11/057,212 US7394026B2 (en) | 2004-02-20 | 2005-02-15 | Multilayer wiring board |
TW094104445A TWI362088B (en) | 2004-02-20 | 2005-02-16 | Multilayer wiring board |
KR1020050013004A KR101033169B1 (ko) | 2004-02-20 | 2005-02-17 | 다층 배선 기판 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004044306A JP4429760B2 (ja) | 2004-02-20 | 2004-02-20 | 多層配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005236091A JP2005236091A (ja) | 2005-09-02 |
JP4429760B2 true JP4429760B2 (ja) | 2010-03-10 |
Family
ID=34858051
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004044306A Expired - Lifetime JP4429760B2 (ja) | 2004-02-20 | 2004-02-20 | 多層配線基板 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7394026B2 (ja) |
JP (1) | JP4429760B2 (ja) |
KR (1) | KR101033169B1 (ja) |
TW (1) | TWI362088B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9468100B2 (en) | 2012-01-27 | 2016-10-11 | Murata Manufacturing Co., Ltd. | Multilayer wiring substrate |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101639618B1 (ko) * | 2009-02-03 | 2016-07-15 | 삼성전자주식회사 | 전자 소자 모듈 |
KR102449619B1 (ko) * | 2017-12-14 | 2022-09-30 | 삼성전자주식회사 | 반도체 패키지 및 이를 포함하는 반도체 모듈 |
EP3629682A1 (en) * | 2018-09-25 | 2020-04-01 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with embedded component having pads connected in different wiring layers |
CN113241336B (zh) * | 2021-04-27 | 2023-12-01 | 上海华虹宏力半导体制造有限公司 | 半导体器件结构及其形成方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3386977B2 (ja) * | 1997-06-05 | 2003-03-17 | 新光電気工業株式会社 | 多層回路基板 |
JPH11260955A (ja) | 1998-03-11 | 1999-09-24 | Shinko Electric Ind Co Ltd | 多層回路基板 |
JPH11297885A (ja) | 1998-04-14 | 1999-10-29 | Shinko Electric Ind Co Ltd | 多層回路基板 |
US7345245B2 (en) * | 2003-10-08 | 2008-03-18 | Lsi Logic Corporation | Robust high density substrate design for thermal cycling reliability |
-
2004
- 2004-02-20 JP JP2004044306A patent/JP4429760B2/ja not_active Expired - Lifetime
-
2005
- 2005-02-15 US US11/057,212 patent/US7394026B2/en active Active
- 2005-02-16 TW TW094104445A patent/TWI362088B/zh active
- 2005-02-17 KR KR1020050013004A patent/KR101033169B1/ko active IP Right Grant
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9468100B2 (en) | 2012-01-27 | 2016-10-11 | Murata Manufacturing Co., Ltd. | Multilayer wiring substrate |
Also Published As
Publication number | Publication date |
---|---|
KR20060042023A (ko) | 2006-05-12 |
KR101033169B1 (ko) | 2011-05-11 |
US20050184393A1 (en) | 2005-08-25 |
TWI362088B (en) | 2012-04-11 |
US7394026B2 (en) | 2008-07-01 |
TW200534439A (en) | 2005-10-16 |
JP2005236091A (ja) | 2005-09-02 |
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