JP2008187049A - システムインパッケージ装置 - Google Patents
システムインパッケージ装置 Download PDFInfo
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- JP2008187049A JP2008187049A JP2007020012A JP2007020012A JP2008187049A JP 2008187049 A JP2008187049 A JP 2008187049A JP 2007020012 A JP2007020012 A JP 2007020012A JP 2007020012 A JP2007020012 A JP 2007020012A JP 2008187049 A JP2008187049 A JP 2008187049A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】本発明の例に係るシステムインパッケージ装置は、パッケージ基板11と、パッケージ基板11の一面側又は他面側に配置される外部端子12と、パッケージ基板11の他面側に配置される第1チップ13と、第1チップ13上に配置される第2チップ14と、第1チップ13と第2チップ14との間に配置される複数のバンプ15とを備える。外部端子12に入力される信号は、第2チップ14を経由して第1チップ13に入力される。
【選択図】 図2
Description
本発明は、バンプを介して互いにスタックされた2つのチップ(第1及び第2チップ)を有するシステムインパッケージ装置を対象とする。このようなシステムインパッケージ装置において、パッケージの外部端子に入力される信号が上側チップ(第2チップ)を経由して下側チップ(第1チップ)に入力される構造を提案する。
次に、最良と思われるいくつかの実施の形態について説明する。
A. 構造
図1は、第1実施の形態に係るシステムインパッケージ装置を示している。図2は、図1のII−II線に沿う断面図である。
図3は、第1実施の形態の変形例に係るシステムインパッケージ装置を示している。図4は、図3のIV−IV線に沿う断面図である。
第1実施の形態によれば、下側チップは、上側チップのリードとしての導電層を有するため、システムインパッケージ装置の高性能化を図ることができる。
A. 構造
図5は、第2実施の形態に係るシステムインパッケージ装置を示している。図6は、図5のVI−VI線に沿う断面図である。
図7は、第2実施の形態の変形例に係るシステムインパッケージ装置を示している。図8は、図7のVIII−VIII線に沿う断面図である。
第2実施の形態によれば、上側チップは、そのチップを貫通するスルーホールと、そのチップの裏面に配置される導電層とを有するため、システムインパッケージ装置の高性能化を図ることができる。
A. 構造
図9は、第3実施の形態に係るシステムインパッケージ装置を示している。図10は、図9のX−X線に沿う断面図である。
図11は、第3実施の形態の第1変形例に係るシステムインパッケージ装置を示している。図12は、図11のXII−XII線に沿う断面図である。
図13は、第3実施の形態の第2変形例に係るシステムインパッケージ装置を示している。
第3実施の形態によれば、上側チップは、下側チップ上及びパッケージ基板の凸部上に跨って配置されるため、システムインパッケージ装置の高性能化を図ることができる。
本発明の例は、高速通信システムに適用できる。
本発明によれば、バンプを介して互いにスタックされた2つのチップを有するシステムインパッケージ装置の高性能化を図ることができる。
Claims (5)
- パッケージ基板と、前記パッケージ基板の一面側又は他面側に配置される外部端子と、前記パッケージ基板の他面側に配置される第1チップと、前記第1チップ上に配置される第2チップと、前記第1チップと前記第2チップとの間に配置される複数のバンプとを具備し、前記外部端子に入力される信号は、前記第2チップを経由して前記第1チップに入力されることを特徴とするシステムインパッケージ装置。
- 前記第1チップは、導電層を有し、前記信号は、前記導電層を介して前記第2チップ内のロジック回路に入力されることを特徴とする請求項1に記載のシステムインパッケージ装置。
- 前記第2チップは、スルーホールと、前記複数のバンプが配置される側とは反対側の面に配置される導電層とを有し、前記信号は、前記導電層及び前記スルーホールを介して前記第2チップ内のロジック回路に入力されることを特徴とする請求項1に記載のシステムインパッケージ装置。
- パッケージ基板と、前記パッケージ基板の一面側又は他面側に配置される外部端子と、第1チップと、前記第1チップ上及び前記パッケージ基板上に跨って配置される第2チップと、前記第1チップと前記第2チップとの間に配置される第1バンプと、前記パッケージ基板と前記第2チップとの間に配置される第2バンプとを具備し、前記外部端子に入力される信号は、前記第2チップを経由して前記第1チップに入力されることを特徴とするシステムインパッケージ装置。
- 前記第2チップのサイズは、第1チップのサイズよりも小さいことを特徴とする請求項1乃至4のいずれか1項に記載のシステムインパッケージ装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007020012A JP2008187049A (ja) | 2007-01-30 | 2007-01-30 | システムインパッケージ装置 |
US12/020,190 US8237289B2 (en) | 2007-01-30 | 2008-01-25 | System in package device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007020012A JP2008187049A (ja) | 2007-01-30 | 2007-01-30 | システムインパッケージ装置 |
Publications (1)
Publication Number | Publication Date |
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JP2008187049A true JP2008187049A (ja) | 2008-08-14 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2007020012A Pending JP2008187049A (ja) | 2007-01-30 | 2007-01-30 | システムインパッケージ装置 |
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JP (1) | JP2008187049A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010073771A (ja) * | 2008-09-17 | 2010-04-02 | Casio Computer Co Ltd | 半導体装置の実装構造 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH023354A (ja) * | 1988-06-15 | 1990-01-08 | Seiko Epson Corp | 光プリンタヘッド |
JPH06112401A (ja) * | 1992-09-25 | 1994-04-22 | Nippon Telegr & Teleph Corp <Ntt> | マルチチップ実装回路 |
JPH10200062A (ja) * | 1997-01-04 | 1998-07-31 | T I F:Kk | 半導体装置 |
JP2004207757A (ja) * | 2004-03-29 | 2004-07-22 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005268670A (ja) * | 2004-03-19 | 2005-09-29 | Nec Electronics Corp | 半導体装置 |
JP2006108150A (ja) * | 2004-09-30 | 2006-04-20 | Seiko Epson Corp | 半導体装置及び半導体装置の実装方法 |
-
2007
- 2007-01-30 JP JP2007020012A patent/JP2008187049A/ja active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH023354A (ja) * | 1988-06-15 | 1990-01-08 | Seiko Epson Corp | 光プリンタヘッド |
JPH06112401A (ja) * | 1992-09-25 | 1994-04-22 | Nippon Telegr & Teleph Corp <Ntt> | マルチチップ実装回路 |
JPH10200062A (ja) * | 1997-01-04 | 1998-07-31 | T I F:Kk | 半導体装置 |
JP2005268670A (ja) * | 2004-03-19 | 2005-09-29 | Nec Electronics Corp | 半導体装置 |
JP2004207757A (ja) * | 2004-03-29 | 2004-07-22 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2006108150A (ja) * | 2004-09-30 | 2006-04-20 | Seiko Epson Corp | 半導体装置及び半導体装置の実装方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010073771A (ja) * | 2008-09-17 | 2010-04-02 | Casio Computer Co Ltd | 半導体装置の実装構造 |
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