CN1957468A - 底部散热器 - Google Patents

底部散热器 Download PDF

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CN1957468A
CN1957468A CNA2005800167314A CN200580016731A CN1957468A CN 1957468 A CN1957468 A CN 1957468A CN A2005800167314 A CNA2005800167314 A CN A2005800167314A CN 200580016731 A CN200580016731 A CN 200580016731A CN 1957468 A CN1957468 A CN 1957468A
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chip
substrate
radiator
electrically connected
heat
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戴尔·哈科特
罗伯特·尼克森
布赖恩·塔格特
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Intel Corp
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Abstract

本发明的实施例提供一种微电子器件，该器件具有设置在芯片与衬底之间的散热器，芯片电连接到所述衬底上。对于本发明的一个实施例，散热器是热膨胀系数近似等于芯片的热膨胀系数的散热片。

Description

底部散热器
技术领域
本发明的实施例一般涉及微电子器件领域，尤其涉及用于从这种器件除去热量的方法和设备。
背景技术
引线键合的微电子器件的散热一般采用设置在硅管芯(芯片)上的散热片。图1示出根据现有技术的引线键合器件。图1所示的器件100包括利用键合引线106而引线键合到衬底110上的芯片105。芯片105可以是硅或一些其它半导体材料。在操作期间，产生热量，必须从芯片中将其除去。衬底110通常可以由陶瓷或某种类型的有机封装制成。将衬底110设置在未示出的印刷电路板(PCB)(母板)上。
通过散热片115来除去热量，该散热片通常是高导热的金属，例如铜或铝。通常，可以使散热片115成为T形以便容纳键合引线106，如图所示。或者，可以简单地按尺寸形成散热片以便仅仅覆盖芯片105的内部，由此避开键合引线106。芯片105和键合引线106则可以由施加在衬底110的表面上的封装120(通常为塑料)来保护。可以将热沉(未示出)附着到散热片上，以提高散热能力。此外或可选地，可以使风扇从上方正对着散热片。
该散热方案的缺点是，大多数的散热从芯片顶部进行。根据器件位于芯片内部的位置，芯片的顶侧可能不是最热的侧面。这意味着通过芯片的上部器件将热量吸收到散热片。
对于芯片叠置的结构来说会引起额外的麻烦。在过去几年中，人们已经对叠置芯片产生了兴趣，如果可能的话。一种这样的芯片叠置方案将许多尺寸减小的芯片叠置在一起以便有助于引线键合。图1A示出根据现有技术的芯片叠置器件。芯片叠置器件150包括多个接连变小的在顶部彼此叠置的芯片155-157，它们被引线键合到衬底160上。与图1的单个芯片方案相比，散热片165接触芯片157的面积相对较小，如图1A所示。此外，增加芯片的数量导致增加热量，必须经过更大的距离来吸收热量。即，必须通过芯片156和157将由芯片155产生的大部分热吸收到散热片165。这同样适用于采用叠置相同尺寸的芯片的方法的芯片叠置方案(例如，斜切(beveling)或中间隔离物)。
这种方案的另一个缺点是，散热片(通常为高导热金属)的热膨胀系数(CTE)与半导体芯片(例如硅)的热膨胀系数不同。这种CTE的失配会导致在正常操作中发生的预期温度变化期间使晶片弯曲。这使得有必要在散热片与芯片之间设置热界面材料(TIM)层(未示出)。包含TIM层增加了制造工艺步骤并且因为TIM层具有其特有的热阻，所以减小了器件的散热能力。
目前，一般的芯片叠置设计用于叠置存储器芯片，其瓦数相对较低。然而，随着芯片叠置器件中的芯片数量的增加，将越来越难于利用图1A所示的结构来从这种器件中除去热量。
此外，希望专门叠置功率较高的芯片(例如处理器)或与存储器芯片相结合来叠置功率较高的芯片。对于这种设计，将很可能证明当前的散热方案是不充分的。
附图简述
通过参考下面的用于阐释本发明的实施例的说明和附图，将会更好地理解本发明。在附图中：
图1示出根据现有技术的引线键合器件；
图1A示出根据现有技术的芯片叠置器件；
图2示出根据本发明的一个实施例的具有底部散热器的微电子器件；
图3示出根据本发明的一个实施例的具有底部散热器的芯片叠置微电子器件；以及
图4示出其中制造具有底部散热器的微电子器件的工艺。
详细说明
在以下说明中，阐述了许多具体的细节。然而，应该理解的是，在没有这些具体细节的情况下也可以实施本发明的实施例。在其它情况下，没有详细地示出公知的电路、结构和技术，以便不会难以理解本说明书。
关于整篇说明书的“一个实施例”或“实施例”，其意味着连同实施例所描述的具体特征、结构或特性包含在本发明的至少一个实施例中。因此，在通篇说明书中各处出现的短语“在一个实施例中”或“在实施例中”不一定都指相同的实施例。此外，可以以任何适当的方式在一个或多个实施例中结合具体的特征、结构或特性。
此外，发明方案没有展现出单个公开实施例的所有特征。因此，将详细说明书之后的权利要求书明确地并入到本详细说明书中，每一个权利要求自身表示本发明的一个单独实施例。
图2示出根据本发明的一个实施例的具有底部散热器的微电子器件。图2所示的器件200包括设置在母板220上并利用导电球221电连接到其上的衬底210。利用键合引线206将芯片205引线键合到衬底上。用作散热器的散热片270设置在芯片205与衬底210之间。散热片270允许将热量从芯片引向衬底210。根据本发明的一个实施例，散热片270由CTE与芯片205的CTE相似的材料制成。例如，散热片270可以由硅制成。对于该实施例，散热片是“虚拟的”硅片。即，散热片是其中没有实施电路的硅片。这允许散热片起到从芯片205散热的作用。对于本发明的一个实施例，由于散热片的CTE与芯片的CTE近似相同，所以在芯片与散热片之间不需要TIM层，由此消除了与该层有关的热阻。
硅具有相对较高的导热率(大约为1.48W/cmK)，尽管没有铝或铜那么高。这种高导热率允许将大量的热量从芯片引向衬底。此外，将散热片设置在芯片的底部，使得散热片与芯片的尺寸相比更大。回想到在一般的现有技术的方案中，散热片必须减小尺寸(至少在与芯片接触的点上)以便容纳键合引线。即，散热片与芯片的接触面积小于芯片的面积。根据本发明的一个实施例，设置在芯片下方的散热片与芯片相比可以相对较大。对于本发明的一个实施例，散热片大于芯片并且在芯片的整个面积上与芯片接触。该较大的散热片，与较大的接触面积相结合，允许将更多的热量从芯片的底部引向衬底。
根据本发明的一个实施例，并且如图2所示，贯穿衬底210形成许多通孔211。电镀有导电金属的通孔211可以用于衬底210与母板220之间的电连接。通孔211不仅提供电连接，而且将热量从衬底210传导到母板220。通常母板可以具有多个铜层并且因此提供良好的热沉。将尽可能多的热量从芯片传导到母板的能力大大增加了器件的散热效率。根据本发明的一个实施例，贯穿衬底形成额外的通孔211以单独用作热通孔。例如，贯穿衬底所形成的通孔多于电连接所需的通孔。这些单独用作热通孔的额外通孔增加了能够通过散热片和衬底从芯片引到母板的热量。
对于本发明的一个实施例，散热片面积的增加和热通孔的加入，允许使用穿过数量增加的衬底的热通孔。
图3示出根据本发明的一个实施例的具有底部散热器的芯片叠置微电子器件。图3所示的器件300包括衬底310、母板320、以及导电球321，如上面参考图2所述。然而，如图3所示，利用键合引线306将一组叠置的芯片305a-305c引线键合到衬底上和/或将一个芯片引线键合到另一个芯片上。在底部芯片305a与衬底310之间设置用作散热器的散热片370。散热片370允许将热量从芯片305a-305c引向衬底310。如上面参考图2所述，通孔311将热量从衬底传导到母板320。叠置的芯片305a-305c中的每一个可以是瓦数相对较低的存储器芯片。然而，根据本发明的一个实施例，叠置的芯片305a-305c中的一个或多个可以是逻辑处理器芯片。对于这种实施例，设置在芯片叠层底部上的散热片散热器效率的提高允许叠置瓦数较高的器件(例如，逻辑处理器)并将其封装在单个模中。对于本发明的一个实施例，芯片305a是逻辑处理器芯片，而芯片305b和305c是存储器芯片(例如，闪速存储器)。
图3所示的器件300还可以包括常规的附着到芯片305c顶部上的散热片(未示出)，如上面参考图1A所述。此外，所叠置的芯片数量是示例性的，根据本发明的各种可选实施例，芯片叠层可以包括或多或少的芯片。
图4示出其中制造具有底部散热器的微电子器件的工艺。图4所示的工艺400从操作405开始，其中将散热器设置在衬底上。通过常规手段将散热器附着到衬底上。对于本发明的一个实施例，选择散热器使其CTE近似等于芯片的CTE。
在操作410中，将芯片设置在散热器上。对于一个实施例，芯片由与散热器相同的材料制成并且面积基本上小于散热器。对于可选实施例，将芯片叠层设置在散热器上。对于这种实施例，最底部的芯片(与散热器接触)的CTE与散热器的CTE近似相等。
在操作415中，将芯片(芯片叠层)电连接到衬底上。例如，在一个实施例中，将芯片引线键合到衬底上，键合引线在散热器的上方延伸。
工艺400的各种操作是示例性的并且可以按照其最基本的形式进行说明，但是在不脱离本发明的基本范围下，可以向工艺400添加操作或从其中删除操作。例如，可以以常规方式将常规的散热片附着到芯片的顶侧(或最上面的芯片)，以提高对芯片或芯片叠层的散热。
虽然已经根据几个实施例来对本发明进行说明，但是本领域技术人员应该意识到，本发明不限于所述的实施例，可以在附属权利要求的精神和范围内，利用修改和变化来实施本发明。因此认为本说明书是示例性的而非限制性的。

Claims (29)

1、一种设备，包括：
衬底；
电连接到所述衬底的芯片；以及
设置在所述衬底和所述芯片之间的散热器。
2、根据权利要求1所述的设备，其中所述散热器由热膨胀系数近似等于芯片的热膨胀系数的散热片构成。
3、根据权利要求1所述的设备，还包括：
电连接到所述衬底的印刷电路板。
4、根据权利要求3所述的设备，其中，贯穿所述衬底形成一个或多个热通孔以将热量从所述衬底传导到所述印刷电路板。
5、根据权利要求4所述的设备，其中所述散热器的面积大于所述芯片。
6、根据权利要求1所述的设备，还包括：
叠置在所述芯片上并电连接到所述芯片和所述衬底中的至少一个的第二芯片。
7、根据权利要求1所述的设备，其中利用一个或多个键合引线将所述芯片电连接到所述衬底。
8、根据权利要求6所述的设备，其中所述芯片具有形成在其中的实施逻辑处理器的电子电路。
9、根据权利要求8所述的设备，还包括：
相继叠置在所述第二芯片上的一个或多个附加芯片，所述一个或多个附加芯片中的每一个电连接到另一芯片或所述衬底中的至少一个。
10、根据权利要求1所述的设备，其中所述芯片和所述散热器都基本上由硅构成。
11、一种系统，包括：
在第一芯片上实施的逻辑处理器件；
电连接到所述逻辑处理器件并将所述逻辑处理器件耦合到印刷电路板的衬底；以及
设置在所述逻辑处理器件与所述衬底之间并接触所述第一芯片底侧的散热器。
12、根据权利要求11所述的系统，还包括：
耦合到所述逻辑处理器件的存储器件，在第二芯片上实施所述存储器件，所述第二芯片叠置在所述第一芯片的顶侧上。
13、根据权利要求12所述的系统，其中所述散热器由热膨胀系数近似等于所述第一芯片的热膨胀系数的散热片构成。
14、根据权利要求13所述的系统，其中所述第一芯片基本上由硅构成并且所述散热片的热膨胀系数大约为1.48W/cmK。
15、根据权利要求12所述的系统，其中贯穿所述衬底形成一个或多个热通孔以将热量从所述衬底传导到所述印刷电路板。
16、根据权利要求15所述的系统，其中所述散热器的面积大于所述第一芯片。
17、根据权利要求12所述的系统，其中利用键合引线将所述衬底电连接到所述逻辑处理器件和所述存储器件。
18、根据权利要求11所述的系统，还包括：
相继叠置在所述第一芯片上的一个或多个附加芯片，所述一个或多个附加芯片中的每一个电连接到另一芯片或所述衬底中的至少一个。
19、根据权利要求11所述的系统，其中所述第一芯片和所述散热器都基本上由硅构成。
20、一种方法，包括：
提供具有顶表面和底表面的衬底；
将散热器附着到顶表面上；
将芯片叠置在所述散热器上；并且
将所述芯片电连接到所述衬底。
21、根据权利要求20所述的方法，其中所述散热器由热膨胀系数近似等于所述芯片的热膨胀系数的散热片构成。
22、根据权利要求20所述的方法，还包括：
电连接到所述衬底的印刷电路板。
23、根据权利要求22所述的方法，其中贯穿所述衬底形成一个或多个热通孔以将热量从所述衬底传导到所述印刷电路板。
24、根据权利要求23所述的方法，其中所述散热器的面积大于所述芯片。
25、根据权利要求20所述的方法，还包括：
将第二芯片叠置在所述芯片上；并且
将所述第二芯片电连接到所述芯片和所述衬底中的至少一个。
26、根据权利要求20所述的方法，其中利用一个或多个键合引线将所述芯片电连接到所述衬底。
27、根据权利要求25所述的方法，其中所述芯片具有形成在其中的实施逻辑处理器的电子电路。
28、根据权利要求27所述的方法，还包括：
将一个或多个附加芯片叠置在所述第二芯片上；并且
将所述一个或多个附加芯片中的每一个电连接到另一芯片或所述衬底中的至少一个。
29、根据权利要求20所述的方法，其中所述芯片和所述散热器都基本上由硅构成。
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