CN105355567A - 双面蚀刻水滴凸点式封装结构及其工艺方法 - Google Patents

双面蚀刻水滴凸点式封装结构及其工艺方法 Download PDF

Info

Publication number
CN105355567A
CN105355567A CN201510687057.8A CN201510687057A CN105355567A CN 105355567 A CN105355567 A CN 105355567A CN 201510687057 A CN201510687057 A CN 201510687057A CN 105355567 A CN105355567 A CN 105355567A
Authority
CN
China
Prior art keywords
pin
metal substrate
dao
water droplet
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201510687057.8A
Other languages
English (en)
Other versions
CN105355567B (zh
Inventor
吴奇斌
吴靖宇
耿丛正
吴莹莹
吴涛
吕磊
郭峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changjiang Electronics Technology Chuzhou Co Ltd
Original Assignee
Changjiang Electronics Technology Chuzhou Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changjiang Electronics Technology Chuzhou Co Ltd filed Critical Changjiang Electronics Technology Chuzhou Co Ltd
Priority to CN201510687057.8A priority Critical patent/CN105355567B/zh
Publication of CN105355567A publication Critical patent/CN105355567A/zh
Application granted granted Critical
Publication of CN105355567B publication Critical patent/CN105355567B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4871Bases, plates or heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/115Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)

Abstract

本发明涉及一种双面蚀刻水滴凸点式封装结构,其特征在于:它包括基岛(1)和引脚(2),所述基岛(1)正面正装或倒装有芯片(3),所述基岛(1)外围的区域、基岛(1)和引脚(2)之间的区域、基岛(1)和引脚(2)上部的区域以及芯片(3)外均包封有塑封料(5),在所述基岛(1)和引脚(2)的背面分别设置有水滴凸点式外管脚(6)。本发明先将基板双面蚀刻形成管脚形状,进行封装步骤之后,最后不需要贴膜用直接蚀刻的方法将外管脚形成一种水滴凸点式外形结构,使得和PCB板焊接的时候锡膏顺利爬到管脚侧边,加强了管脚和PCB板的结合,避免焊接不牢的问题。

Description

双面蚀刻水滴凸点式封装结构及其工艺方法
技术领域
本发明涉及一种双面蚀刻水滴凸点式封装结构及其工艺方法。属于集成电路封装领域。
背景技术
QFN(QuadFlatNo-leadPackage,四面扁平无引脚封装)是高功率密度的封装,四方扁平无引脚型态封装呈正方形或矩形,封装底部中央位置有一个或多个裸露焊盘用来导热,封装四侧配置有电极触点。
在将QFN封装装在PCB上时,是用锡膏以贴合的形式焊接在PCB上的。QFN封装的引脚区与PCB上对应位置的焊盘对应,同时PCB在与暴露焊盘对应的位置也会设置一个相应比例的散热焊盘。由于QFN封装引脚是平面的,与PCB焊接时,二者贴合很近。同时散热焊盘的尺寸相对较大,需要的锡膏和助焊剂的量也大,而助焊剂受热时会挥发产生气体;散热焊盘四周被焊脚包围,散热焊盘上的助焊剂大量的气体在面积相对较大的区域无法排出,就会在器件的散热焊盘和PCB的散热焊盘间形成气泡,阻碍焊接过程,导致接触不良。
发明内容
本发明的目的在于克服上述不足,提供一种双面蚀刻水滴凸点式封装结构及其工艺方法,该工艺方法主要是先将基板双面蚀刻形成管脚形状,进行封装步骤之后,最后不需要贴膜用直接蚀刻的方法将外管脚形成一种水滴凸点式外形结构,使得和PCB板焊接的时候锡膏顺利爬到管脚侧边,加强了管脚和PCB板的结合,避免焊接不牢的问题。
本发明的目的是这样实现的:一种双面蚀刻水滴凸点式封装结构的工艺方法,该方法主要包括以下步骤:
步骤一、取金属基板
取一片厚度合适的金属基板;
步骤二、化学蚀刻
对步骤一中的金属基板正面和背面进行化学蚀刻,化学蚀刻直至在金属基板的正面和背面形成相应的内管脚和外管脚;
步骤三、电镀金属线路层
在步骤二的金属基板正面的内管脚表面电镀一层金属线路层,形成相应的基岛和引脚;
步骤四、装片
在步骤三形成的基岛正面植入芯片;
步骤五、塑封
在步骤四中的金属基板正面采用塑封料进行塑封;
步骤六、化学蚀刻
对步骤五中的金属基板背面进行化学蚀刻,将金属基板背面蚀刻掉90%左右形成水滴凸点式外管脚;
步骤七、电镀金属层
在步骤六的金属基板背面的水滴凸点式外管脚的表面电镀金属层;
步骤八、切割成品
对步骤七的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得双面蚀刻水滴凸点式封装结构。
一种双面蚀刻水滴凸点式封装结构,它包括基岛和引脚,所述基岛正面正装或倒装有芯片,所述基岛外围的区域、基岛和引脚之间的区域、基岛和引脚上部的区域以及芯片外均包封有塑封料,在所述基岛和引脚的背面分别设置有水滴凸点式外管脚。
与现有技术相比,本发明的有益效果是:
1、外基岛和引脚呈水滴凸点式,焊盘的面积有缩小,但是凸点式的形状有利于锡膏爬到引脚侧面,焊接的时候锡膏可以通过抓住引脚两侧面和底面加强与PCB的结合,保证与PCB板焊接的牢固性和可靠度。
2、省去蚀刻步骤中需要使用的曝光显影膜,省去一部分材料成本,也减少了工艺步骤,节省制作时间。
附图说明
图1—图8为本发明一种双面蚀刻水滴凸点式封装结构的工艺方法的流程示意图。
图9为本发明一种双面蚀刻水滴凸点式封装结构的结构示意图。
其中:
基岛1、引脚2、芯片3、金属线4、塑封料5、水滴凸点式外管脚6。
具体实施方式
实施例一、芯片正装双面蚀刻水滴凸点式封装结构的工艺方法,该方法主要包括以下步骤:
步骤一、取金属基板
参见图1,取一片厚度合适的金属基板,此板材使用的目的只是为线路制作与后续封装支撑线路层结构所使用的过渡性材料,此板材的材质主要是以金属材料为主,而金属材料的材质可以是铜材﹑铁材﹑镀锌材﹑不锈钢材﹑铝材或可以达到导电功能的金属物质或非全金属物质等。
步骤二、化学蚀刻
参见图2,对步骤一中的金属基板正面和背面贴膜曝光显影进行化学蚀刻,化学蚀刻直至在金属基板的正面和背面形成相应的内管脚和外管脚,蚀刻药水可以采用氯化铜或是氯化铁。
步骤三、电镀金属线路层
参见图3,在步骤二的金属基板正面的内管脚表面电镀一层金属线路层,形成相应的基岛和引脚,且为了满足后续工艺的导电需求,部分地方设计有联筋,金属线路层材料可以是铜、铝、镍、银、金、铜银、镍金、镍钯金(通常5~20微米,可以根据不同特性变换电镀的厚度)等材料,当然其它可以导电的金属物质都可以使用,并不局限铜、铝、镍、银、金、铜银、镍金、镍钯金等金属材料,电镀方式可以是化学沉积或是电解电镀方式。
步骤四、装片打线
参见图4,在步骤三形成的基岛正面植入芯片,在基岛正面涂覆导电或是不导电的粘结物质后将芯片与基岛接合,在芯片正面与引脚正面之间进行键合金属线作业,所述金属线的材料采用金、银、铜、铝或是合金的材料,金属丝的形状可以是丝状也可以是带状。
步骤五、塑封
参见图5,在步骤四中的金属基板正面采用塑封料进行塑封,塑封方式可以采用模具灌胶方式、喷涂设备喷涂方式或是用贴膜方式。所述塑封料可以采用有填料物质或是无填料物质的环氧树脂。
步骤六、化学蚀刻
参见图6,对步骤五中的金属基板背面进行化学蚀刻,将金属基板背面蚀刻掉90%左右形成水滴凸点式外管脚,蚀刻药水可以采用氯化铜或是氯化铁。
步骤七、电镀金属层
参见图7,在步骤六的金属基板背面的水滴凸点式外管脚的表面电镀金属层,金属线路层材料可以是锡。
步骤八、切割成品
参见图8,对步骤七的半成品进行切割作业,切断联筋,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得双面蚀刻水滴凸点式封装结构,可采用常规的钻石刀片以及常规的切割设备即可。
实施例二、芯片倒装双面蚀刻水滴凸点式超薄封装结构的工艺方法,本实施例与实施例一的区别在于:
步骤四、装片
在步骤三的基岛和引脚上通过底部填充胶倒装芯片,倒装的方式可以将底部填充胶涂覆在基岛和引脚上再倒装上芯片或是将底部充胶涂覆在芯片正面后倒装于基岛和引脚正面。
同时打线过程可以省略。
参见图9,为本发明涉及的一种芯片正装双面蚀刻水滴凸点式封装结构,包括基岛1和引脚2,所述基岛1正面通过导电或不导电粘结物质设置有芯片3,所述芯片3正面与引脚2正面之间用金属线4相连接,所述基岛1外围的区域、基岛1和引脚2之间的区域、基岛1和引脚2上部的区域以及芯片3和金属线4外均包封有塑封料5,在所述基岛1和引脚2的背面分别设置有水滴凸点式外管脚6。
根据装片方式的不同,本发明还涉及一种芯片倒装双面蚀刻水滴凸点式超薄封装结构,区别在于所述芯片3通过底部填充胶倒装于基岛1和引脚2正面,同时省略金属线4。

Claims (2)

1.一种双面蚀刻水滴凸点式封装结构的工艺方法,其特征在于:该方法主要包括以下步骤:
步骤一、取金属基板
取一片厚度合适的金属基板;
步骤二、化学蚀刻
对步骤一中的金属基板正面和背面进行化学蚀刻,化学蚀刻直至在金属基板的正面和背面形成相应的内管脚和外管脚;
步骤三、电镀金属线路层
在步骤二的金属基板正面的内管脚表面电镀一层金属线路层,形成相应的基岛和引脚;
步骤四、装片
在步骤三形成的基岛正面植入芯片;
步骤五、塑封
在步骤四中的金属基板正面采用塑封料进行塑封;
步骤六、化学蚀刻
对步骤五中的金属基板背面进行化学蚀刻,将金属基板背面蚀刻掉90%左右形成水滴凸点式外管脚;
步骤七、电镀金属层
在步骤六的金属基板背面的水滴凸点式外管脚的表面电镀金属层;
步骤八、切割成品
对步骤七的半成品进行切割作业,使原本以阵列式集合体方式集成在一起并含有芯片的塑封体模块一颗颗切割独立开来,制得双面蚀刻水滴凸点式封装结构。
2.一种双面蚀刻水滴凸点式封装结构,其特征在于:它包括基岛(1)和引脚(2),所述基岛(1)正面正装或倒装有芯片(3),所述基岛(1)外围的区域、基岛(1)和引脚(2)之间的区域、基岛(1)和引脚(2)上部的区域以及芯片(3)外均包封有塑封料(5),在所述基岛(1)和引脚(2)的背面分别设置有水滴凸点式外管脚(6)。
CN201510687057.8A 2015-10-22 2015-10-22 双面蚀刻水滴凸点式封装结构及其工艺方法 Active CN105355567B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510687057.8A CN105355567B (zh) 2015-10-22 2015-10-22 双面蚀刻水滴凸点式封装结构及其工艺方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510687057.8A CN105355567B (zh) 2015-10-22 2015-10-22 双面蚀刻水滴凸点式封装结构及其工艺方法

Publications (2)

Publication Number Publication Date
CN105355567A true CN105355567A (zh) 2016-02-24
CN105355567B CN105355567B (zh) 2018-01-09

Family

ID=55331509

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510687057.8A Active CN105355567B (zh) 2015-10-22 2015-10-22 双面蚀刻水滴凸点式封装结构及其工艺方法

Country Status (1)

Country Link
CN (1) CN105355567B (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113471154A (zh) * 2021-04-02 2021-10-01 江苏尊阳电子科技有限公司 一种背面预蚀凸点式封装结构的封装工艺
CN114934272A (zh) * 2022-04-29 2022-08-23 东莞领益精密制造科技有限公司 金属条组、卷轴、卷轴屏的成型工艺及手机
CN116282841A (zh) * 2023-03-31 2023-06-23 四川虹科创新科技有限公司 玻璃窑炉清理旋转闸板积灰结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050167400A1 (en) * 2004-01-30 2005-08-04 Intersil Americas Inc. System and method for decapsulating an encapsulated object
CN1670955A (zh) * 2004-03-19 2005-09-21 恩益禧电子股份有限公司 半导体器件
US20110164642A1 (en) * 2009-12-24 2011-07-07 Sumitomo Electric Industries, Ltd. Laser diode with ridge waveguide structure and method for manufacturing the same
CN103474406A (zh) * 2013-09-27 2013-12-25 华天科技(西安)有限公司 一种aaqfn框架产品无铜扁平封装件及其制作工艺
CN104505375A (zh) * 2014-11-03 2015-04-08 南通富士通微电子股份有限公司 半导体封装结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050167400A1 (en) * 2004-01-30 2005-08-04 Intersil Americas Inc. System and method for decapsulating an encapsulated object
CN1670955A (zh) * 2004-03-19 2005-09-21 恩益禧电子股份有限公司 半导体器件
US20110164642A1 (en) * 2009-12-24 2011-07-07 Sumitomo Electric Industries, Ltd. Laser diode with ridge waveguide structure and method for manufacturing the same
CN103474406A (zh) * 2013-09-27 2013-12-25 华天科技(西安)有限公司 一种aaqfn框架产品无铜扁平封装件及其制作工艺
CN104505375A (zh) * 2014-11-03 2015-04-08 南通富士通微电子股份有限公司 半导体封装结构

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113471154A (zh) * 2021-04-02 2021-10-01 江苏尊阳电子科技有限公司 一种背面预蚀凸点式封装结构的封装工艺
CN114934272A (zh) * 2022-04-29 2022-08-23 东莞领益精密制造科技有限公司 金属条组、卷轴、卷轴屏的成型工艺及手机
CN114934272B (zh) * 2022-04-29 2023-12-08 东莞领益精密制造科技有限公司 金属条组、卷轴、卷轴屏的成型工艺及手机
CN116282841A (zh) * 2023-03-31 2023-06-23 四川虹科创新科技有限公司 玻璃窑炉清理旋转闸板积灰结构

Also Published As

Publication number Publication date
CN105355567B (zh) 2018-01-09

Similar Documents

Publication Publication Date Title
CN102456648B (zh) 封装基板的制法
CN106783792A (zh) 一种塑封体侧面引脚具有侧边爬锡性能的封装结构
CN103456645B (zh) 先蚀后封三维系统级芯片正装堆叠封装结构及工艺方法
CN203367260U (zh) 一种功率陶瓷外壳和功率芯片封装结构
TWM556934U (zh) 具有接點溝槽的預成形導線架
TW201250942A (en) Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof
CN103715165A (zh) 半导体封装件及其制法
TWM558999U (zh) 發光封裝元件
CN103887256A (zh) 一种高散热芯片嵌入式电磁屏蔽封装结构及其制作方法
CN108198790B (zh) 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
CN105355567A (zh) 双面蚀刻水滴凸点式封装结构及其工艺方法
CN102403236B (zh) 芯片外露的半导体器件及其生产方法
CN206595254U (zh) 一种塑封体侧面引脚具有侧边爬锡性能的封装结构
CN105206594B (zh) 单面蚀刻水滴凸点式封装结构及其工艺方法
CN206532771U (zh) 散热型半导体器件
CN108183091A (zh) 一种封装结构及其工艺方法
CN108364928B (zh) 一种集成电路封装结构及其加工方法
CN108198804B (zh) 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
CN105225972A (zh) 一种半导体封装结构的制作方法
CN212113712U (zh) 一种半导体封装引线框架
CN212542425U (zh) 一种半导体封装件
CN108183096A (zh) 封装结构及其制备方法
CN204361085U (zh) 金属引线框高导热倒装片封装结构
CN210925986U (zh) 一种倒装功率器件封装结构
CN203787410U (zh) 一种高散热芯片嵌入式电磁屏蔽封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant