CN108183096A - 封装结构及其制备方法 - Google Patents
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Abstract
本发明提供了一种封装结构及其制备方法,涉及半导体制造技术领域,该封装结构包括基板、导电层、芯片、导电柱和绝缘体;导电层铺设于基板上,导电柱和芯片间隔设置于导电层上,且导电柱和芯片远离基板的一侧用于设置电极焊盘;绝缘体填充于芯片与导电柱周围将导电层封闭。该封装结构完美解决垂直导电功率半导体电极在上下两面到电极焊盘在同一侧的转换;可以将封装尺寸控制在芯片尺寸的3倍以下,实际可以达到1.5倍以下,达到芯片级封装尺寸,能够适应当前电子产品的精细化发展;同时,工艺步骤少,工艺简单,适合量产,封装物料用量少,成本低。
Description
技术领域
本发明涉及半导体制造技术领域,尤其是涉及一种封装结构及其制备方法。
背景技术
SMT(Surface Mount Technology)是电子业界一门新兴的工业技术,它的兴起及迅猛发展是电子组装业的一次革命,它使电子组装变得越来越快速和简单,随之而来的是各种电子产品更新换代越来越快,集成度越来越高,价格越来越便宜。随着穿戴式电子设备的兴起,对贴片封装的缩小尺寸要求越来越高,现有贴片封装结构尺寸已经不能完全适应市场的要求,需要采用芯片级尺寸封装结构。
现有的功率半导体器件主要分为VDMOS(Vertical double-diffusion metal-oxide-semiconductor)、BJT(Bipolar Junction Transistor,双极结型晶体管)、二极管,都是垂直导电的功率半导体器件,现有功率半导体贴片封装,都是在固定框架上,通过固晶、焊线、塑封、电镀、成型五步主要工序,将功率半导体芯片封装在特定的贴片封装形式中。而垂直导电的BJT、VDMOS、二极管等功率器件,由于芯片背面需要通过大电流,更是离不开这种封装结构。
但是这种封装结构外形体积大,不适于穿戴电子设备和移动电子设备等要求小空间的电器,同时采用的物料消耗大,导致成本增加,对企业造成经济负担。
公开于该背景技术部分的信息仅仅旨在加深对本发明的总体背景技术的理解,而不应当被视为承认或以任何形式暗示该信息构成已为本领域技术人员所公知的现有技术。
发明内容
本发明的目的之一在于提供一种封装结构,以解决现有技术中存在的封装结构体积大,不适应当下电子产品的小而精的发展,且物料消耗大,成本高的技术问题。
本发明的目的之二在于提供一种封装结构的制备方法,以解决现有技术中存在的封装结构体积大,不适应当下电子产品的小而精的发展,且物料消耗大,成本高的技术问题。
第一方面,本发明提供一种封装结构,包括基板、导电层、芯片、导电柱和绝缘体;所述导电层铺设于所述基板上,所述导电柱和所述芯片间隔设置于所述导电层上,且所述导电柱和所述芯片远离所述基板的一侧用于设置电极焊盘;所述绝缘体填充于所述芯片与所述导电柱周围将所述导电层封闭。
作为一种进一步的技术方案,所述绝缘体将所述导电柱和所述芯片包裹,所述电极焊盘为块体结构且突出于所述绝缘体表面。
作为一种进一步的技术方案,所述绝缘体填充于所述芯片与所述导电柱的侧面,以使所述芯片与所述导电柱突出于所述绝缘体表面,所述电极焊盘层状覆盖于所述芯片、所述导电柱远离所述基板的一侧。
作为一种进一步的技术方案,所述电极焊盘的厚度为1-500μm。
作为一种进一步的技术方案,所述电极焊盘的材质为金属或金属合金。
作为一种进一步的技术方案,所述导电层与所述导电柱、所述导电层与所述芯片之间通过连接层连接。
作为一种进一步的技术方案,所述绝缘体的材质为环氧树脂、硅胶、陶瓷、光刻胶、聚酰亚胺中的任意一种。
作为一种进一步的技术方案,所述基板的材质为金属、硅、陶瓷、蓝宝石、玻璃中的任意一种。
第二方面,本发明提供的一种封装结构的制备方法,用于制备如上述技术方案提供的任一种所述的封装结构,包括以下步骤:
准备基板;
在所述基板上覆盖形成导电层;
通过导电连接层在所述基板上设置间隔分布的导电柱和芯片;
将绝缘体布满所述导电柱和所述芯片的侧面;
在所述芯片和所述导电柱远离所述基板的一侧设置电极焊盘。
作为一种进一步的技术方案,所述导电层通过蒸发、电镀、化学镀或热压中任一种方式形成于所述基板上。
与现有技术相比,本发明提供的封装结构及其制备方法能够达到以下有益效果:
本发明提供的封装结构,是一种新型的贴片封装结构,能够实现功率半导体芯片垂直导电的性能,封装外形尺寸只比半导体芯片略大,达到芯片级封装尺寸,能够适应当前电子产品的精细化发展;同时,制造用料少,单个封装成本低。
本发明提供的封装结构的制备方法,用于制备上述封装结构,能够取得上述封装结构的所有有益效果,且该制备方法简单易实施,具有良好的推广前景。
附图说明
为了更清楚地说明本发明具体实施方式或现有技术中的技术方案,下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施方式,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例一提供的一种封装结构的具体实施方式;
图2为本发明实施例一提供的另一种封装结构的具体实施方式。
图标:100-基板;200-导电层;300-连接层;400-导电柱;500-芯片;600-电极焊盘;700-绝缘体。
具体实施方式
下面将结合附图对本发明的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
在本发明的描述中,需要说明的是,术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。此外,术语“第一”、“第二”、“第三”仅用于描述目的,而不能理解为指示或暗示相对重要性。
在本发明的描述中,需要说明的是,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通。对于本领域的普通技术人员而言,可以具体情况理解上述术语在本发明中的具体含义。
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是,此处所描述的具体实施方式仅用于说明和解释本发明,并不用于限制本发明。
实施例一
本发明实施例提供一种封装结构,包括基板100、导电层200、芯片500、导电柱400和绝缘体700;导电层200铺设于基板100上,导电柱400和芯片500间隔设置于导电层200上,且导电柱400和芯片500远离基板100的一侧用于设置电极焊盘600;绝缘体700填充于芯片500与导电柱400周围将导电层200封闭。
目前最常用的CSP(Chip Scale Package)封装是一种最为先进的封装形式,其封装尺寸不超过裸芯片5001.2倍,体积很小。
CSP封装主要包括以下5种封装类别:1、柔性基板封装,由美国Tessera公司开发的这类CSP封装的主要由IC芯片、载带(柔性体)、粘接层、凸点(铜/镍)等构成,载带是用聚酰亚胺和铜箔组成,它的主要特点是结构简单,可靠性高,安装方便,可利用原有的TAB(TapeAutomated Bonding)设备焊接;2、刚性基板封装,由日本Toshiba公司开发的这类CSP封装,实际上就是一种陶瓷基板100薄型封装,主要由芯片、氧化铝基板、铜凸点和树脂构成,通过倒装焊、树脂填充和打印3个步骤完成,它的封装效率(芯片与基板面积之比)可达到75%,是相同尺寸的TQFP的2.5倍;3、引线框架式CSP封装,由日本Fujitsu公司开发的此类CSP封装分为Tape-LOC和MF-LOC两种形式,将芯片安装在引线框架上,引线框架作为外引脚,因此不需要制作焊料凸点,可实现芯片与外部的互连;4、圆片级CSP封装,由ChipScale公司开发的此类封装,它是在圆片前道工序完成后,直接对圆片利用半导体工艺进行后续组件封装,利用划片槽构造周边互连,再切割分离成单个器件,该封装结构主要包括两项关键技术即再分布技术和凸焊点制作技术,它有以下特点:相当于裸片大小的小型组件(在最后工序切割分片)、以圆片为单位的加工成本(圆片成本率同步成本)、加工精度高(由于圆片的平坦性、精度的稳定性);5、微小模塑型CSP,由日本三菱电机公司开发的CSP结构主要由IC芯片、模塑的树脂和凸点等构成,芯片上的焊区通过在芯片上的金属布线与凸点实现互连,整个芯片浇铸在树脂上,只留下外部触点,这种结构可实现很高的引脚数,有利于提高芯片的电学性能、减少封装尺寸、提高可靠性,完全可以满足储存器、高频器件和逻辑器件的高I/O数需求。同时由于它无引线框架和焊丝等,体积特别小,提高了封装效率。
但是,CSP封装适合于电极焊盘在同一侧的集成电路芯片,不适合于垂直导电的功率半导体芯片。
SMT发展至今,随着电子产品集成度的不断提高,标准零件逐步向微型化发展。
本发明实施例提供的封装结构是一种新型的贴片封装结构,能够实现功率半导体芯片垂直导电的性能,完美解决垂直导电功率半导体电极在上下两面到电极焊盘在同一侧的转换;可以将封装尺寸控制在芯片500尺寸的3倍以下,实际可以达到1.5倍以下,达到芯片级封装尺寸,能够适应当前电子产品的精细化发展;同时,工艺步骤少,工艺简单,适合量产,封装物料用量少,成本低。
其中,基板100上的导电层200和导电柱400将芯片500下面的一个或多个电极通过的电流导入到整个封装结构的表层,使得功率半导体封装后所有的导电的电极焊盘600在同一侧,适合贴片焊接的要求。使用导电柱400导通电流,比传统封装结构中的焊线工艺电流密度大,能够节约能耗。
需要说明的是,导电层200与导电柱400、导电层200与芯片500之间通过连接层300连接。
具体地,导电层200通过蒸发、电镀、化学镀或热压中任一种方式形成于基板100上。
上述电极焊盘600的厚度为1-500μm,根据具体的工作需求进行改变调整。此外,电极焊盘600的材质为金属或金属合金,且电极焊盘600的金属成分主要为金属锡。
绝缘体700的材质为环氧树脂、硅胶、陶瓷、光刻胶、聚酰亚胺中的任意一种,具有良好的绝缘性,能够对导电柱400和芯片500起到良好的保护效果,且实现工艺简单,用量少,成本低。
基板100的材质为金属、硅、陶瓷、蓝宝石、玻璃中的任意一种,这些材料都具有一定的硬度,能够符合贴片焊接的要求。导电柱400的材质则是金属、硅等能够导电的材料。
具体地,绝缘体700与导电柱400和芯片500之间的连接结构可以有两种实现方式:
方式一
绝缘体700将导电柱400和芯片500包裹,电极焊盘600为块体结构且突出于绝缘体700表面。
参照图1,以这种结构为基础,作为一种具体的实施例,本实施例提供的封装结构中,导电层200铺设于基板100上,且导电层200的铺设面积小于基板100的面积。在导电层200的上通过连接层300设置有导电柱400和芯片500,导电柱400和芯片500之间间隔设置。导电柱400和芯片500远离基板100的一侧设置有块体状的电极焊盘600,绝缘体700填充于导电柱400与芯片500之间以保护导电柱400和芯片500,并且绝缘体700将导电柱400、芯片500和导电层200封闭,导电柱400和芯片500上的电极焊盘600则突出于绝缘体700暴露于封装结构的表面,方便后期贴片焊接。
需要说明的是,此处,电极焊盘600的厚度较大,以使电极焊盘600不被绝缘体700遮盖,影响焊接效果。
方式二
绝缘体700填充于芯片500与导电柱400的侧面,以使芯片500与导电柱400突出于绝缘体700表面,电极焊盘600层状覆盖于芯片500、导电柱400远离基板100的一侧。
以这种结构为基础,作为一种具体的实施例,本实施例提供的封装结构中,导电层200通过铺设于基板100上,且导电层200的铺设面积小于基板100的面积。在导电层200通过连接层300设置有导电柱400和芯片500,导电柱400和芯片500之间间隔设置。导电柱400和芯片500远离基板100的一侧设置有层状的电极焊盘600,绝缘体700填充于导电柱400与芯片500之间以保护导电柱400和芯片500,并且绝缘体700将导电层200封闭,而导电柱400和芯片500以及设置于二者上的电极焊盘600突出于绝缘体700表面,方便后期贴片焊接。
需要说明的是,此处,电极焊盘600的厚度较小。
另外,导电柱400的数量可以有多个,举例说明,参照图2,其中,导电层200具有两个,每个导电层200靠近基板100边缘的一侧分别通过一个连接层300设置有一个导电柱400,而两个导电层200相互接近的一侧分别通过一个连接层300连接相同的一个芯片500。
需要说明的是,以上两种封装结构的具体实现方式只是对本发明实施例提供的封装结构的具体结构举例说明,并不用于限定本发明的保护范围。
综上,本发明提供的封装结构,是一种新型的贴片封装结构,能够实现功率半导体芯片垂直导电的性能,完美解决垂直导电功率半导体电极在上下两面到电极焊盘600在同一侧的转换;可以将封装尺寸控制在芯片500尺寸的3倍以下,实际可以达到1.5倍以下,达到芯片500级封装尺寸,能够适应当前电子产品的精细化发展;同时,工艺步骤少,工艺简单,适合量产,封装物料用量少,成本低。
实施例二
本发明实施例提供一种封装结构的制备方法,用于制备如实施例以提供的任一种封装结构,包括以下步骤:
准备基板100;
在基板100上覆盖形成导电层200;
通过连接层300在基板100上设置间隔分布的导电柱400和芯片500;
将绝缘体700布满导电柱400和芯片500的侧面;
在芯片500和导电柱400远离基板100的一侧设置电极焊盘600。
其中,导电层200通过蒸发、电镀、化学镀或热压中任一种方式形成于基板100上。
可以看出,本发明实施例提供的封装结构的制备方法,能够制备实施例一所提供的任一种封装结构,也就能取得上述封装结构的所有有益效果,且工艺步骤少,工艺简单,适合量产,具有良好的发展前景。
以上对本发明的封装结构及其制备方法进行了说明,但是,本发明不限定于上述具体的实施方式,只要不脱离权利要求的范围,可以进行各种各样的变形或变更。本发明包括在权利要求的范围内的各种变形和变更。
最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。
Claims (10)
1.一种封装结构,其特征在于,包括基板、导电层、芯片、导电柱和绝缘体;所述导电层铺设于所述基板上,所述导电柱和所述芯片间隔设置于所述导电层上,且所述导电柱和所述芯片远离所述基板的一侧用于设置电极焊盘;所述绝缘体填充于所述芯片与所述导电柱周围将所述导电层封闭。
2.根据权利要求1所述的封装结构,其特征在于,所述绝缘体将所述导电柱和所述芯片包裹,所述电极焊盘为块体结构且突出于所述绝缘体表面。
3.根据权利要求1所述的封装结构,其特征在于,所述绝缘体填充于所述芯片与所述导电柱的侧面,以使所述芯片与所述导电柱突出于所述绝缘体表面,所述电极焊盘层状覆盖于所述芯片、所述导电柱远离所述基板的一侧。
4.根据权利要求2或3所述的封装结构,其特征在于,所述电极焊盘的厚度为1-500μm。
5.根据权利要求1所述的封装结构,其特征在于,所述电极焊盘的材质为金属或金属合金。
6.根据权利要求1所述的封装结构,其特征在于,所述导电层与所述导电柱、所述导电层与所述芯片之间通过连接层连接。
7.根据权利要求1所述的封装结构,其特征在于,所述绝缘体的材质为环氧树脂、硅胶、陶瓷、光刻胶、聚酰亚胺中的任意一种。
8.根据权利要求1所述的封装结构,其特征在于,所述基板的材质为金属、硅、陶瓷、蓝宝石、玻璃中的任意一种。
9.一种封装结构的制备方法,其特征在于,用于制备如权利要求1-8中任一项所述的封装结构,包括以下步骤:
准备基板;
在所述基板上覆盖形成导电层;
通过导电连接层在所述基板上设置间隔分布的导电柱和芯片;
将绝缘体布满所述导电柱和所述芯片的侧面;
在所述芯片和所述导电柱远离所述基板的一侧设置电极焊盘。
10.根据权利要求9所述的封装结构的制备方法,其特征在于,所述导电层通过蒸发、电镀、化学镀或热压中任一种方式形成于所述基板上。
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