CN107706117A - 单步封装 - Google Patents

单步封装 Download PDF

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Publication number
CN107706117A
CN107706117A CN201710675601.6A CN201710675601A CN107706117A CN 107706117 A CN107706117 A CN 107706117A CN 201710675601 A CN201710675601 A CN 201710675601A CN 107706117 A CN107706117 A CN 107706117A
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CN
China
Prior art keywords
semiconductor
sealant
semiconductor wafer
column
semiconductor element
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Granted
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CN201710675601.6A
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English (en)
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CN107706117B (zh
Inventor
K.K.候
J.克拉克
J.麦克劳德
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Semtech Corp
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Semtech Corp
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Priority to CN202110689294.3A priority Critical patent/CN113410186A/zh
Publication of CN107706117A publication Critical patent/CN107706117A/zh
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Publication of CN107706117B publication Critical patent/CN107706117B/zh
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Abstract

本发明公开了单步封装。一种半导体装置，包括半导体晶片。在半导体晶片之上形成多个柱状凸块。在柱状凸块之上沉积焊料。当半导体晶片在载体上时，在形成柱状凸块之后，将半导体晶片单片化成多个半导体管芯。当半导体管芯保持在载体上时，在半导体管芯和柱状凸块周围沉积密封剂。密封剂覆盖在柱状凸块之间的半导体管芯的有源表面。

Description

单步封装
要求保护本国优先权
本申请要求保护2016年8月9日提交的美国临时申请号62/372,720的权益，所述申请通过引用被并入在本文中。
技术领域
本发明一般涉及半导体装置，并且更特别地涉及使用单步封装（single-shotencapsulation）来封装半导体管芯的方法和半导体装置。
背景技术
通常在现代电子产品中发现半导体装置。半导体装置在电气部件的数量和密度方面变化。分立的半导体装置一般包含一种类型的电气部件，例如发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器以及功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体装置典型地包含数百至数百万的电气部件。集成半导体装置的示例包括微控制器、微处理器、电荷耦合装置（CCD）、太阳能电池以及数字微镜装置（DMD）。
半导体装置执行各种各样的功能，诸如信号处理、高速计算、发射和接收电磁信号、控制电子装置、将日光变换成电力，以及为电视显示器创建视觉投影。在娱乐、通信、功率转换、网络、计算机以及消费产品的领域中发现半导体装置。也在军事应用、航空、汽车、工业控制器以及办公设备中发现半导体装置。
半导体制造的一个目标是产生更小的半导体装置。更小的装置以及作为结果产生的更小的最终产品典型地消耗更少的功率、能够被更高效地产生、并且具有更高的性能。更小的半导体装置和更小的最终产品在制造时消耗更少的材料，这减少环境影响。此外，更小的半导体装置具有更小的覆盖区，其对于拥挤的印刷电路板和更小的最终产品而言是期望的。更小的管芯尺寸可以通过造成具有更小的、更高密度的有源和无源部件的管芯的前端工艺中的改进来实现。后端工艺可以通过电气互连和封装（packaging）材料中的改进而造成具有更小覆盖区的半导体装置封装。
也可以通过减少制造步骤而使半导体制造更加高效。制造商寻求使用于制造半导体装置的工艺流线化（streamline），使得需要更少步骤、使用更少材料并且使用更加环境友好的材料。改进制造工艺可以改进新产品投入市场的时间以及制造的成本。
需要提供一种具有改进的成本、制造时间、环境影响以及寄生特性的半导体封装。
附图说明
图1a-1e图示在半导体晶片上形成低剖面凸块；
图2a-2c图示在钝化层开口之上的低剖面凸块；
图3图示低剖面凸块和重新分配层；
图4a-4f图示利用单步封装来封装来自晶片的半导体管芯；
图5a-5d图示利用单步封装制造的半导体封装；
图6a-6b图示利用单步封装制造的双组合（dual gang）封装；
图7a-7b图示利用单步封装制造的三组合封装；
图8a-8d图示用于利用单步封装来封装半导体管芯的第二工艺流程；
图9a-9f图示用于利用单步封装来封装半导体管芯的第三工艺流程；以及
图10a-10b图示利用半导体封装的电子装置。
具体实施方式
在参考附图的下面的描述中的一个或多个实施例中描述了本发明，在所述附图中相似的数字表示相同或相似的元件。虽然关于用于实现本发明的目的的最佳模式描述了本发明，但是本领域中的那些技术人员将领会到本描述意图覆盖替换方案、修改以及等同物如同可以被包括在本发明的如由所附权利要求以及如由下面的公开和绘图支持的权利要求的等同物所限定的精神和范围之内。
半导体装置一般使用两个复杂的制造工艺来制造：前端制造和后端制造。前端制造涉及多个管芯在半导体晶片的表面上的形成。晶片上的每个管芯包含有源和无源电气部件，其被电气连接以形成功能电气电路。有源电气部件诸如晶体管和二极管，具有控制电流的流动的能力。无源电气部件诸如电容器、电感器和电阻器创建用以执行电气电路功能所必要的在电压与电流之间的关系。
有源和无源部件通过包括掺杂、沉积、光刻、刻蚀以及平坦化的一系列工艺步骤而被形成在半导体晶片的表面之上。掺杂通过诸如离子注入或热扩散的技术将杂质引入到半导体材料中。掺杂工艺通过响应于电场或基极电流而动态地改变半导体材料电导率来修改有源装置中的半导体材料的电导率。晶体管包含不同的掺杂类型和掺杂程度的区，其如对于使晶体管能够在施加电场或基极电流时促进或限制电流的流动所必要的那样来布置。
有源和无源部件通过具有不同电气性质的材料的层形成。各层可以通过各种沉积技术来形成，所述沉积技术部分地由正被沉积的材料类型确定。例如，薄膜沉积可以包括化学气相沉积（CVD）、物理气相沉积（PVD）、电解电镀以及化学镀工艺。每个层一般被图案化以形成有源部件、无源部件或在部件之间的电气连接的部分。
后端制造指的是将完成的晶片切割或单片化成单独的半导体管芯以及封装半导体管芯以用于结构支撑、电气互连以及环境隔离。完成的封装然后被插入到电气系统中，并且该半导体装置的功能被使得可用于其他系统部件。
图1a示出半导体晶片120，其具有基底衬底材料122，诸如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅或用于结构支撑的其他体块半导体材料。多个半导体管芯或部件124被形成在晶片120上通过非有源、管芯间晶片区域或锯道126分离。锯道126提供用以将半导体晶片120单片化成单独的半导体管芯124的切割区域。在一个实施例中，半导体晶片120具有100-450毫米（mm）的宽度或直径。
图1b示出半导体晶片120的部分的横截面视图。每个半导体管芯124具有背面或非有源表面128以及有源表面130，其包含模拟或数字电路，其实施为形成在管芯之内并且根据管芯的电气设计和功能而电气互连的有源装置、无源装置、导电层以及电介质层。例如，电路可以包括一个或多个晶体管、二极管以及其他电路元件，其形成在有源表面130之内来实施模拟电路或数字电路，诸如数字信号处理器（DSP）、ASIC、MEMS、存储器或其他信号处理电路。半导体管芯124也可以包含集成无源装置（IPD）诸如电感器、电容器和电阻器，用于RF信号处理。在一个实施例中，半导体管芯124包括单个有源部件，例如二极管或功率MOSFET。
使用PVD、CVD、电解电镀、化学镀工艺或其他适合的金属沉积工艺来将导电层132形成在有源表面130之上。导电层132包括铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、银（Ag）或其他适合的导电材料的一个或多个层。导电层132作为电气连接到有源表面130上的电路的接触焊盘来操作。
在图1c中，绝缘或电介质层134形成在半导体晶片120之上。绝缘层134包含二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、焊料抗蚀剂或具有相似绝缘和支撑性质的其他材料的一个或多个层。绝缘层134的部分通过激光直接烧蚀（LDA）、刻蚀、或其他适合于暴露半导体管芯124上的导电层132的工艺来去除。
在图1d中，使用电镀工艺来从导电层132向上生长低剖面柱状凸块140。直接从管芯焊盘向上制造低剖面柱状凸块140。在一些实施例中，使用电解电镀、化学镀或其他适合的沉积工艺来从Al、Cu、Sn、Ni、Au、Ag、钛（Ti）、钨（W）、另一适合导电材料或其合金形成柱状凸块140。在其他实施例中，使用光刻掩模来形成柱状凸块140。在一个实施例中，低剖面柱状凸块140在平面视图中近似0.5 mm×0.5 mm具有近似50微米（µm）的高度。在图1e中，焊料帽142被沉积在凸块140之上。
通过在凸块140之上电镀或以其他方式沉积Ni、Au、Sn、Ag或其组合来形成焊料帽142。在一个实施例中，使用单个掩蔽层来形成柱状凸块140和焊料帽142。在一些实施例中，焊料帽142包括无铅焊料。
图2a-2c图示在聚酰亚胺（PI）钝化层中的开口之上形成低剖面凸块140。在图2a中，PI层150形成在绝缘层134之上。在其他实施例中，使用其他钝化材料。在后续制造步骤期间，PI层150保护绝缘层134。在图2b中，通过LDA或适合于暴露导电层132以用于在图2c中形成凸块140和焊料帽142的其他刻蚀工艺来穿过PI层150形成开口152。
图3图示在形成凸块140之前在半导体管芯124之上形成的重新分配层（RDL）。将绝缘或电介质层160形成在绝缘层134和导电层132之上。绝缘层160包含SiO2、Si3N4、SiON、Ta2O5、Al2O3或具有相似绝缘和结构性质的其他材料的一个或多个层。绝缘层160完全跨半导体晶片120延伸。通过LDA、刻蚀、或适合于暴露导电层132以用于后续电气互连的其他工艺来去除绝缘层160的部分。
使用PVD、CVD、电解电镀、化学镀或其他适合的金属沉积工艺来将导电层162形成在绝缘层160之上。导电层162包含Al、Cu、Sn、Ni、Au、Ag或其他适合的导电材料的一个或多个层。在一个实施例中，导电层162包括Ti/Cu、TiW/Cu或耦合剂/Cu的粘附或种子层。可选地将具有良好湿法刻蚀选择性的另一种材料诸如Ni、Au或Ag添加到种子层。通过溅射、化学镀或通过沉积层压Cu箔结合化学镀来沉积种子层。导电层162通过绝缘层160中的开口而电气连接到半导体管芯124的导电层132。导电层162被图案化成扇出或扇入配置以按期望将低剖面凸块140定位在半导体管芯124之上。在一些实施例中，在绝缘层160和导电层导电层162之上交织附加的绝缘层和导电层以实施更高级的信号路由（signal routing）。
将与绝缘层160或PI层150相似的绝缘或钝化层164形成在绝缘层160和导电层162之上。在导电层162之上的钝化层164中形成开口。如在图1d和1e中那样，使低剖面凸块140和焊料帽142穿过钝化层164中的开口形成在导电层162上。
图4a-4f图示使用单步封装工艺来封装来自图1a-1e的单独的半导体管芯124。如果期望PI层或RDL，则在图2c或图3中的半导体晶片120上执行相似的工艺。在图4a中，在半导体管芯124之间对晶片120挖沟槽。在锯道126中使用激光切割工具或锯片172穿过绝缘层134并且仅部分穿过晶片120形成沟槽170。在一个实施例中，使用深反应离子刻蚀（DRIE）形成沟槽170。在一些实施例中，将沟槽170形成至在60与200µm之间的深度，包括凸块140和焊料帽142的高度在内。
在图4b中，晶片120被翻转并且安装到基底支撑物174和背面研磨带176上，其中有源表面130和沟槽170朝向该基底支撑物定向。使用背面研磨工具180用机械研磨或刻蚀工艺来对晶片120进行背面研磨以去除基底材料122的部分并且减少半导体晶片120的厚度。用背面研磨工具180减薄半导体晶片120形成半导体晶片的新背面表面178。在图4b中示出的实施例中，沟槽170被形成为至少与对于半导体管芯124期望的最终厚度一样深。背面研磨操作通过去除锯道126中的所有剩余半导体材料来使半导体管芯124与彼此分离。
图4c-4d图示替换的实施例，其中没有完全穿过半导体管芯124的期望最终厚度形成沟槽170。背面研磨工具180去除半导体晶片120的部分，但是没有将半导体晶片充分减薄成分离的半导体管芯124。在一些实施例中，在背面研磨之后的半导体管芯124的厚度，包括凸块140-142在内，在80与220µm之间的范围内，在完成背面研磨之后有大约20µm的半导体晶片厚度保留在锯道126中。在图4d中通过使用激光切割工具或锯片182去除锯道126之内的半导体晶片120的剩余部分来使半导体管芯124单片化。在一些实施例中，在背面研磨之后使用DRIE或另一适合的刻蚀工艺来使半导体管芯124单片化。
可选地，例如通过溅射，使图4b或图4d的替换实施例中的半导体管芯124在单片化之后暴露于氧化物涂层。在图4e中，使用膏印刷、压缩模塑、转移模塑、液体密封剂模塑、真空层压、旋涂或其他适合的敷料器将密封剂或模制化合物186沉积在半导体管芯124和低剖面凸块140之上作为绝缘材料。特别地，密封剂186覆盖半导体管芯124的侧表面、有源表面130以及背面表面178。密封剂186还完全在每个凸块140周围延伸，而使焊料帽142从密封剂暴露。密封剂186可以是聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或具有适当填料的聚合物。密封剂186是不导电的且在环境上保护半导体装置免受外部要素和污染物。密封剂186还保护半导体管芯124以免由于暴露于光而引起的降级。
在一些实施例中，密封剂186的表面与焊料帽142的表面共面。在其他实施例中，焊料帽142凹进在密封剂186之内或从密封剂延伸出。半导体管芯124和密封剂186被作为板从载体174去除并且例如在炉中经受可选的模塑后固化（PMC）工艺。密封剂186维持每个半导体管芯124的相对位置，近似好像该半导体管芯保持作为半导体晶片120的部分一样。半导体管芯124通过密封剂186而不是基底材料122连接到彼此。
在PMC之后，将在密封剂186之内的半导体管芯124安装到载体190与用于单片化的热或UV释放带192上。使用锯片、激光切割工具或水切割工具194在半导体管芯之间将半导体管芯124单片化成单步封装（SSE）封装200。单片化SSE封装200被从载体190热释放或者通过UV辐照从载体190释放，并且被封装成例如带和卷以用于递送到将把该封装集成到电子装置中的消费者。在一些实施例中，SSE封装200被发送以用于测试操作。
图5a-5d从各种视角图示SSE封装200。图5a示出在图4a-4f的视图中的SSE封装200的横截面。图5b图示其中SSE封装200被相对于图5a向左或向右转动九十度的横截面视图。虽然图5a-5d中的半导体管芯124是二端子装置，例如二极管，但是在其他实施例中类似地封装具有附加端子和附加凸块140的更复杂的半导体管芯124。半导体管芯124可以是二端子装置、三端子装置例如功率MOSFET，或具有更多端子，例如具有地址和数据总线的ASIC。
图5c和5d图示SSE封装200的透视图。图5c是外部视图，而图5d将密封剂186图示为透明的以透露在密封剂之内的半导体管芯124和凸块140的结构。在图5d中的虚线是仅仅由于密封剂186是透明的而可见的线。
在不需要基底框架或基板（其保持作为最终封装的部分）的情况下形成SSE封装200，这允许减少的封装厚度。在一些实施例中，SEE封装200的厚度是近似0.150 mm或更低。SSE封装200的相对低的厚度满足愈发更小装置尤其是可穿戴和物联网（IoT）装置的制造商的需要。SSE封装200的构造，其允许消除内部基板和引线接合（wire bond），改进封装可靠性、增加产品性能并且简化组装工艺。也减少寄生电气特性，例如电阻、电感和电容。
没有内部焊料接合的SSE封装200的构造允许将无铅焊料用于焊料帽142，其相对于传统锡铅焊料在更高的温度处熔化。在其他封装类型中，内部焊料接合，例如用以使用球栅阵列或引线接合连接将半导体管芯124耦合到框架，可以在将最终封装安装到印刷电路板（PCB）或其他基板时熔化。可以在无铅焊料所需要的更高的温度处将SSE封装200安装到基板而不冒封装完整性的风险。柱状凸块140与焊料帽142可以在晶片级处形成并且不被回流，直到使用焊料帽将SSE封装200附接在消费者的PCB上。由于简化的工艺流程，SSE封装200是薄的且重量轻的，具有改进的第二级板可靠性和投入市场的时间。
图6a-6b图示形成在同一封装中包括两个半导体管芯124的双组合封装220。使用切割工具194来使半导体管芯124单片化，如在图4f中那样。然而，对于半导体管芯对中的一些的邻近半导体管芯124不被单片化。双组合封装220包括两个半导体管芯124，其可以被连接到PCB上的一对导电迹线。图7a-7b图示将半导体管芯124单片化成三个半导体管芯的组以形成三组合封装230。可以将半导体管芯124单片化成针对要在电路板上一起使用的装置的数量的任何期望的配置。
图8a-8d图示作为在图4a-4f中的流程的替换方案的单步封装工艺。在图8a中，将半导体晶片120设置成有源表面130朝向载体174定向，如在图4c中那样，但是没有先前沟槽170的形成。如果期望PI层和/或RDL层，则也可以使用来自图2c或3的半导体晶片120。在图8b中，如在图4d中那样，使用锯片或激光切割工具182将半导体管芯124单片化。在一些实施例中，使用DRIE。在图8c中，如在图4e中那样，沉积密封剂186，并且在图8d中如在图4f中那样使密封的半导体管芯124单片化成SSE封装250。SSE封装250与SSE封装200相似，但是工艺在没有沟槽170的形成的情况下进行。
图9a-9f图示用于单步封装的第三工艺流程。在图9a中，如在图8a中那样对半导体晶片120进行背面研磨。在图9b中，将半导体晶片120安装在热释放带260上，其中背面表面178朝向热释放带定向。将锯片或激光切割工具262用于使半导体管芯124穿过锯道126单片化。在单片化之后，将半导体管芯124转移安装到支撑物基底或载体264上，如在图9c中示出的那样。在安装半导体管芯124之前，将UV或热转移带266设置在载体264上。在一个实施例中，带260是热带并且带266是UV带。在图9d中，在没有释放UV带266的情况下，使用提高的温度来去除热释放带260。在另一个实施例中，带266是热释放带而带260是UV释放带。
在图9e中，如在图4e中那样，沉积密封剂186，并且在图9f中如在图4f中那样使密封的半导体管芯124单片化成SSE封装270。SSE封装270与SSE封装200相似，但是工艺如在图9a-9f中那样进行。
图10a图示被安装到PCB或其他基板360上的SSE封装之一。基板360包括形成在基板的表面之上的导电层或迹线362。按期望使导电层362图案化以实施电子装置的意图的功能。图10a示出SSE封装230作为示例，但是任何公开的SSE封装被相似地安装。将SSE封装230设置在360上，其中密封剂186接触基板。焊料帽142接触导电层362。在一些实施例中，例如由于用于附接的粘附层、在导电层362上提供的附加焊膏或装置制造的其他物流（logistical）现实，在SSE封装230与基板360之间存在偏移。使焊料帽142回流到导电层362上以将SSE封装230机械接合和电气连接到基板360。焊料142基本上包含在密封剂186的开口之内。
图10b图示安装在PCB 360上作为电子装置370的部分的SSE封装230，所述电子装置370具有连同该SSE封装一起安装在PCB的表面上的多个半导体封装。取决于应用，电子装置370可以具有一种类型的半导体封装或多种类型的半导体封装。
电子装置370可以是使用半导体封装来执行一个或多个电气功能的独立系统。替换地，电子装置370可以是更大系统的子部件。例如，电子装置370可以是平板电脑、蜂窝电话、数码相机、通信系统或其他电子装置的部分。电子装置370也可以使图形卡、网络接口卡或可以集成到计算机中的其他信号处理卡。半导体封装可以包括微处理器、存储器、ASIC、逻辑电路、模拟电路、RF电路、分立装置或其他半导体管芯或电气部件。
在图10b中，PCB 360提供一般基板用于安装在PCB上的半导体封装的结构支撑和电气互连。使用蒸发、电解电镀、化学镀、丝网印刷或其他适合的金属沉积工艺来将导电信号迹线362形成在PCB 360的表面之上或PCB 360的层之内。信号迹线362提供在半导体封装、安装部件以及其他外部系统部件中的每个之间的电气通信。按需要，迹线362还提供到半导体封装的电源和地连接。
SSE封装372是使用以上公开的单步封装工艺之一封装的ASIC。SSE封装230是三组合封装，并且与三个邻近导电迹线串联焊接。为了图示的目的，在PCB 360上示出数个类型的第一级封装，包括接合引线封装390和倒装芯片382。此外，数个类型的第二级封装，包括球栅阵列（BGA）384、凸点芯片载体（BCC）392、连接盘栅格阵列（LGA）394、多芯片模块（MCM）388、四面无引线扁平封装（QFN）396、嵌入式晶片级球栅阵列（eWLB）386、以及晶片级芯片尺寸封装（WLCSP）380被示出安装在PCB 360上。在一个实施例中，eWLB 386是扇出晶片级封装（Fo-WLP）或扇入晶片级封装（Fi-WLP）。取决于系统需要，可以将半导体封装的任何组合（用第一和第二级封装样式的任何组合配置的）以及其他电子部件连接到PCB 360。
在一些实施例中，电子装置370包括单个附接的半导体封装，而其他实施例要求多个互连封装。通过将一个或多个半导体封装组合在单个基板之上，制造商可以将预制造的部件并入到电子装置和系统中。因为半导体封装包括复杂的功能，所以可以使用较不昂贵的部件和流线化的制造工艺来制造电子装置。作为结果产生的装置较不易于故障并且制造起来较不昂贵，从而对消费者造成更低的成本。
虽然已经详细说明了本发明的一个或多个实施例，但是技术人员将领会到，在不脱离如在所附权利要求中阐述的本发明的范围的情况下，可以对那些实施例做出修改和改编。

Claims (15)

1.一种制造半导体装置的方法，包括：
提供半导体晶片；
在所述半导体晶片之上形成多个柱状凸块；
在所述柱状凸块之上沉积焊料；
在形成所述柱状凸块之后，将所述半导体晶片单片化成多个半导体管芯；以及
在所述半导体管芯和柱状凸块周围沉积密封剂。
2.权利要求1所述的方法，进一步包括：
将所述半导体晶片设置在载体上；
当所述半导体晶片在所述载体上时，将所述半导体晶片单片化；以及
当所述半导体晶片保持在所述载体上时，在将所述半导体晶片单片化之后，沉积密封剂。
3.权利要求2所述的方法，其中当沉积所述密封剂时，焊料接触所述载体。
4.权利要求1所述的方法，进一步包括：在将所述半导体晶片单片化之前，在所述半导体管芯之间形成沟槽。
5.权利要求4所述的方法，其中将所述半导体晶片单片化包括将所述半导体晶片背面研磨至所述沟槽。
6.一种制造半导体装置的方法，包括：
提供半导体晶片；
在所述半导体晶片之上形成多个柱状凸块；
在形成所述柱状凸块之后，将所述半导体晶片单片化成多个半导体管芯；以及
在所述半导体管芯周围沉积密封剂。
7.权利要求6所述的方法，进一步包括：切穿所述密封剂以分离所述半导体管芯，其中多个半导体管芯保持通过所述密封剂连接。
8.权利要求6所述的方法，进一步包括：
将所述半导体晶片设置在第一载体上；
在所述第一载体上将所述半导体晶片单片化；
将所述半导体管芯从所述第一载体转移安装到第二载体；以及
当所述半导体管芯在所述第二载体上时，在所述半导体管芯周围沉积所述密封剂。
9.权利要求6所述的方法，进一步包括：在沉积所述密封剂之前在所述柱状凸块之上沉积焊料。
10.权利要求9所述的方法，进一步包括：
将所述半导体管芯设置在基板上，其中所述密封剂接触所述基板；以及
将所述焊料回流到所述基板的导电层上。
11.一种半导体装置，包括：
半导体管芯；
在所述半导体管芯之上形成的柱状凸块；
在所述柱状凸块之上形成的焊料帽；以及
在所述半导体管芯、柱状凸块以及焊料帽之上沉积的密封剂。
12.权利要求11所述的半导体装置，其中所述密封剂的表面与所述焊料的表面共面。
13.权利要求11所述的半导体装置，进一步包括基板，所述基板包括导电迹线，其中所述密封剂接触所述基板并且所述焊料帽机械接合到所述导电迹线。
14.权利要求11所述的半导体装置，进一步包括形成在所述半导体管芯与柱状凸块之间的重新分配层。
15.权利要求11所述的半导体装置，进一步包括通过密封剂机械连接到彼此的多个半导体管芯。
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