TW201946164A - 單次式封裝 - Google Patents

單次式封裝 Download PDF

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Publication number
TW201946164A
TW201946164A TW108135700A TW108135700A TW201946164A TW 201946164 A TW201946164 A TW 201946164A TW 108135700 A TW108135700 A TW 108135700A TW 108135700 A TW108135700 A TW 108135700A TW 201946164 A TW201946164 A TW 201946164A
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TW
Taiwan
Prior art keywords
semiconductor
sealant
carrier
semiconductor die
solder
Prior art date
Application number
TW108135700A
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English (en)
Inventor
客坤 侯
喬納森 克拉克
約翰 麥克里歐
Original Assignee
美商先科公司
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Application filed by 美商先科公司 filed Critical 美商先科公司
Publication of TW201946164A publication Critical patent/TW201946164A/zh

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Abstract

一種半導體裝置係包含一半導體晶圓。複數個柱凸塊係被形成在該半導體晶圓之上。一焊料係被沉積在該些柱凸塊之上。當該半導體晶圓是在一載體上且在形成該些柱凸塊之後，該半導體晶圓係被單粒化成為複數個半導體晶粒。在該半導體晶粒仍然在該載體上時，一密封劑係被沉積在該半導體晶粒以及柱凸塊周圍。該密封劑係覆蓋該半導體晶粒的在該些柱凸塊之間的一主動表面。

Description

單次式封裝
本發明係大致有關於半導體裝置，並且更具體而言係有關於一種利用單次式封裝來封入一半導體晶粒之半導體裝置及方法。
國內優先權之主張
本申請案係主張2016年8月9日申請的美國臨時申請案號62/372,720的益處，該申請案係被納入在此作為參考。
半導體裝置係常見於現代的電子產品中。半導體裝置係在電性構件的數目及密度上變化。離散的半導體裝置一般包含一類型的電性構件，例如是發光二極體(LED)、小信號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(MOSFET)。整合的半導體裝置通常包含數百個到數百萬個電性構件。整合的半導體裝置的例子係包含微控制器、微處理器、電荷耦合裝置(CCD)、太陽能電池、以及數位微鏡裝置(DMD)。
半導體裝置係執行廣範圍的功能，例如是信號處理、高速的計算、傳送及接收電磁信號、控制電子裝置、轉換太陽光成為電力、以及產生用於電視顯示器的視覺投影。半導體裝置係見於娛樂、通訊、電力轉換、網路、電腦以及消費者產品的領域中。半導體裝置亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備中。
半導體製造的一目標是產出較小的半導體裝置。較小的裝置以及所產生的較小的終端產品通常消耗較低的功率，可以更有效率地加以生產，並且具有較高的效能。較小的半導體裝置以及較小的終端產品係在製造上消耗較少的材料，此係降低環境上的影響。此外，較小的半導體裝置係具有一較小的覆蓋區，其係擁擠的印刷電路板及較小的終端產品所期望的。較小的晶粒尺寸可藉由在產生具有較小且較高密度的主動及被動構件之晶粒的前端製程中的改良來加以達成。後端製程可以藉由在電互連及封裝材料上的改良來產生具有較小覆蓋區的半導體裝置封裝。
半導體製造亦可以藉由減少製造步驟而被做成是更有效率的。製造商係尋求精簡用於製造半導體裝置的製程，使得較少的步驟是所需的，較少的材料係被利用，並且對於環境更友善的材料係被利用。改進製程可以改善新產品上市的時間以及製造的成本。
對於提供一種具有改善的成本、製造的時間、環境的影響、以及寄生的特徵之半導體封裝係存在著需求。
本發明的一態樣是關於一種製造一半導體裝置之方法，其包括：提供一半導體晶圓；在該半導體晶圓之上形成複數個柱凸塊；在該些柱凸塊之上沉積一焊料；在形成該些柱凸塊之後，單粒化該半導體晶圓成為複數個半導體晶粒；以及在該些半導體晶粒以及柱凸塊周圍沉積一密封劑。
本發明的另一態樣是關於一種製造一半導體裝置之方法，其包括：提供一半導體晶圓；在該半導體晶圓之上形成複數個柱凸塊；在形成該些柱凸塊之後，單粒化該半導體晶圓成為複數個半導體晶粒；以及在該些半導體晶粒周圍沉積一密封劑。
本發明的另一態樣是關於一種半導體裝置，其係包括：一半導體晶粒；一柱凸塊，其係被形成在該半導體晶粒之上；一焊料蓋，其係被形成在該柱凸塊之上；以及一密封劑，其係被沉積在該半導體晶粒、柱凸塊、以及焊料蓋之上。
本發明係在以下參考該些圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號係代表相同或類似的元件。儘管本發明係以用於達成本發明之目的之最佳模式來加以描述，但熟習此項技術者將會體認到的是，該說明係欲涵蓋可內含在藉由以下的揭露內容及圖式所支持之所附的申請專利範圍及該些申請專利範圍的等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。
半導體裝置一般是利用兩個複雜的製程：前端製造及後端製造來加以製造。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。在該晶圓上的每一個晶粒係包含電連接以形成功能電路的主動及被動電性構件。例如是電晶體及二極體的主動電性構件係具有控制電流流動的能力。例如是電容器、電感器及電阻器的被動電性構件係產生執行電路功能所必要的電壓及電流之間的一種關係。
被動及主動構件係藉由一系列的製程步驟而形成在半導體晶圓的表面之上，該些製程步驟包含摻雜、沉積、微影、蝕刻及平坦化。摻雜係藉由例如是離子植入或熱擴散的技術以將雜質帶入半導體材料中。該摻雜製程係藉由響應於一電場或基極電流來動態地改變該半導體材料的導電度以修改主動元件中的半導體材料的導電度。電晶體係包含具有不同類型及程度的摻雜的區域，該些區域係以使得該電晶體在電場或基極電流的施加時提升或限制電流的流動所必要的來加以配置。
主動及被動構件係藉由具有不同電氣特性的材料層來加以形成。該些層可藉由各種沉積技術來形成，該些技術部分是由被沉積的材料類型所決定的。例如，薄膜沉積可能牽涉到化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解的電鍍以及無電的電鍍製程。每一個層一般是被圖案化，以形成主動構件、被動構件或是構件間的電連接的部分。
後端製造係指切割或單粒化完成的晶圓成為個別的半導體晶粒，並且為了結構的支撐、電互連以及環境的隔離來封裝該半導體晶粒。該完成的封裝係接著被插入一電性系統中，並且使得該半導體裝置的功能為可供其它系統構件利用的。
圖1a係展示一具有一種基底基板材料122的半導體晶圓120，例如是矽、鍺、磷化鋁、砷化鋁、砷化鎵、氮化鎵、磷化銦、碳化矽、或是其它用於結構的支撐的基體半導體材料。複數個半導體晶粒或構件124係被形成在晶圓120上，該些半導體晶粒124係藉由一非主動的晶粒間的晶圓區域或切割道126來加以分開。切割道126係提供切割區域以將半導體晶圓120單粒化成為個別的半導體晶粒124。在一實施例中，半導體晶圓120係具有一100-450毫米(mm)的寬度或直徑。
圖1b係展示半導體晶圓120的一部分的橫截面圖。每一個半導體晶粒124係具有一背表面或非主動表面128以及一包含類比或數位電路的主動表面130，該類比或數位電路係被實施為形成在該晶粒內並且根據該晶粒的電性設計及功能來電互連的主動元件、被動元件、導電層、以及介電層。例如，該電路係包含一或多個電晶體、二極體、以及其它電路元件，其係被形成在主動表面130內以實施類比電路或數位電路，其例如是數位信號處理器(DSP)、ASIC、MEMS、記憶體、或是其它的信號處理電路。半導體晶粒124亦可包含例如是電感器、電容器及電阻器之整合的被動元件(IPD)，以用於射頻(RF)信號處理。在一實施例中，半導體晶粒124係包含單一主動構件，例如是一個二極體或是一功率MOSFET。
一導電層132係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它適當的金屬沉積製程而被形成在主動表面130之上。導電層132係包含一或多層的鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、銀(Ag)、或是其它適當的導電材料。導電層132係運作為電連接至在主動表面130上的電路的接觸墊。
在圖1c中，一絕緣或介電層134係被形成在半導體晶圓120之上。絕緣層134係包含一或多層的二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、鋁氧化物(Al2O3)、阻焊劑、其它具有類似絕緣及結構的性質之材料。絕緣層134的一部分係藉由雷射直接剝蝕(LDA)、蝕刻、或是其它適當的製程來加以移除，以在半導體晶粒124上露出導電層132。
在圖1d中，低輪廓的柱凸塊140係利用一電鍍製程而從導電層132向上生長。低輪廓的柱凸塊140係直接由該些晶粒墊向上所製成的。在某些實施例中，柱凸塊140係利用電解的電鍍、無電的電鍍、或是其它適當的沉積製程，而由Al、Cu、Sn、Ni、Au、Ag、鈦(Ti)、鎢(W)、其它適當的導電材料、或是其之合金所形成的。在其它實施例中，柱凸塊140係利用一微影遮罩來加以形成。在一實施例中，低輪廓的柱凸塊140在平面圖上大約是0.5mm乘以0.5mm，其具有一約50微米(µm)的高度。一焊料蓋142係在圖1e中沉積在凸塊140之上。
焊料蓋142係藉由在凸塊140之上電鍍或是以其它方式沉積Ni、Au、Sn、Ag、或是其之組合來加以形成。在一實施例中，柱凸塊140以及焊料蓋142係利用單一遮罩層來加以形成。在某些實施例中，焊料蓋142係包含一無鉛的焊料。
圖2a-2c係描繪在一聚醯亞胺(PI)鈍化層中的開口之上形成低輪廓的凸塊140。在圖2A中，PI層150係被形成在絕緣層134之上。其它的鈍化材料係被使用在其它實施例中。PI層150係在後續的製造步驟期間保護絕緣層134。在圖2b中，開口152係藉由LDA或是其它適當的蝕刻製程穿過PI層150而被形成以露出導電層132，以用於在圖2c中的凸塊140及焊料蓋142的形成。
圖3是描繪一重新分佈層(RDL)係在凸塊140的形成之前被形成在半導體晶粒124之上。一絕緣或介電層160係被形成在絕緣層134以及導電層132之上。絕緣層160係包含一或多層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似絕緣及結構的性質之材料。絕緣層160係完全橫跨半導體晶圓120來延伸的。絕緣層160的一部分係藉由LDA、蝕刻、或是其它適當的製程而被移除以露出導電層132，以用於後續的電互連。
一導電層162係利用PVD、CVD、電解的電鍍、無電的電鍍、或是其它適當的金屬沉積製程而被形成在絕緣層160之上。導電層162係包含一或多層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的導電材料。在一實施例中，導電層162係包含一Ti/Cu、TiW/Cu、或是一偶合劑/Cu的黏著或晶種層。另一種例如是Ni、Au、或Ag的具有良好的濕式蝕刻選擇性的金屬係選配地被加到該晶種層。該晶種層係藉由濺鍍、無電的電鍍、或是藉由沉積疊層的Cu箔結合無電的電鍍來加以沉積的。導電層162係透過在絕緣層160中的開口來電連接至半導體晶粒124的導電層132。導電層162係用一種扇出或扇入的配置而被圖案化，以將低輪廓的凸塊140根據需要來設置在半導體晶粒124之上。在某些實施例中，額外的絕緣層及導電層係交錯在絕緣層160以及導電層162之上，以實施更先進的信號繞線。
一類似於絕緣層160或PI層150的絕緣或鈍化層164係被形成在絕緣層160及導電層162之上。開口係被形成在導電層162之上的鈍化層164中。如同在圖1d及1e中，低輪廓的凸塊140及焊料蓋142係透過在鈍化層164中的開口而被形成在導電層162上。
圖4a-4f係描繪利用單次式封裝製程以封裝來自圖1a-1e的個別的半導體晶粒124。若一PI層或RDL是所要的話，則一類似的製程係在圖2c或圖3中的半導體晶圓120上加以執行。在圖4a中，晶圓120係在半導體晶粒124之間形成溝槽。溝槽170係利用雷射切割工具或是鋸刀172，穿過在切割道126中的絕緣層134並且只部分地穿過晶圓120來加以形成。在一實施例中，溝槽170係利用深反應性離子蝕刻(DRIE)來加以形成。在某些實施例中，溝槽170係被形成到包含凸塊140及焊料蓋142的高度在內的一介於60到200µm之間的深度。
在圖4b中，晶圓120係在主動表面130及溝槽170被定向朝向該基底支撐件之下，被倒置並且安裝到基底支撐件174以及背面研磨帶176之上。晶圓120係在一利用背面研磨工具180的機械式研磨或蝕刻製程下被背面研磨，以移除基底材料122的一部分並且降低半導體晶圓120的厚度。利用背面研磨工具180來薄化半導體晶圓120係形成該半導體晶圓的一新的背表面178。在圖4b所示的實施例中，溝槽170係被形成至少與半導體晶粒124的一所要的最後厚度一樣深的。該背面研磨操作係藉由移除所有在切割道126中的其餘的半導體材料來將半導體晶粒124彼此分開。
圖4c-4d係描繪一替代實施例，其中溝槽170並未完全穿過半導體晶粒124的所要的最後的厚度來加以形成。背面研磨工具180係移除半導體晶圓120的一部分，但是並不充分地薄化該半導體晶圓以分開半導體晶粒124。在某些實施例中，半導體晶粒124在背面研磨之後的包含凸塊140-142的厚度是在介於80到220µm之間的範圍中，其中在背面研磨完成之後，在切割道126中剩餘的半導體晶圓厚度是在20µm左右。半導體晶粒124係在圖4d中藉由利用雷射切割工具或是鋸刀182來移除在切割道126之內的半導體晶圓120的其餘的部分而被單粒化。在某些實施例中，DRIE或是另一適當的蝕刻製程係被用來在背面研磨之後單粒化半導體晶粒124。
在圖4b或圖4d的替代實施例的任一個中的半導體晶粒124係在單粒化之後，選配地例如是藉由濺鍍而被曝露到一氧化物塗層。在圖4e中，一密封劑或是模製化合物186係利用一膏印刷、壓縮模製、轉移模製、液體密封劑模製、真空疊層、旋轉塗覆、或是其它適當的施用器，而被沉積在半導體晶粒124以及低輪廓的凸塊140之上以作為一種絕緣材料。尤其，密封劑186係覆蓋半導體晶粒124的側表面、主動表面130、以及背表面178。密封劑186亦完全地延伸在每一個凸塊140的周圍，而留下焊料蓋142從該密封劑被露出。密封劑186可以是聚合物複合材料，例如是具有填充物的環氧樹脂、具有填充物的環氧丙烯酸酯、或是具有適當的填充物的聚合物。密封劑186是非導電的，並且在環境上保護該半導體裝置免於外部的元素及污染物。密封劑186亦保護半導體晶粒124免於由於曝露於光的劣化。
在某些實施例中，密封劑186的一表面係與焊料蓋142的一表面共平面的。在其它實施例中，焊料蓋142係凹陷在密封劑186之內、或是從該密封劑延伸的。半導體晶粒124及密封劑186係從作為一面板的載體174被移除，並且使其通過一選配的後模具固化(PMC)製程，例如是在一烘箱中。密封劑186係維持每一個半導體晶粒124的相對的位置大致就像是該半導體晶粒仍然是半導體晶圓120的部分。半導體晶粒124係藉由密封劑186來連接至彼此，而不是基底材料122。
在PMC之後，在密封劑186之內的半導體晶粒124係被安裝到具有熱或UV解黏膠帶(release tape)192的載體190之上以用於單粒化。半導體晶粒124係在該些半導體晶粒之間利用鋸刀、雷射切割工具、或是水切割工具194而被單粒化成為單次式封裝(single-shot encapsulant，SSE)的封裝200。該些被單粒化的SSE封裝200係用熱、或是透過UV照射以從載體190被解黏，並且被封入例如是一捲帶以用於傳遞給將會整合該些封裝到電子裝置中的消費者。在某些實施例中，SSE封裝200係被傳送至一測試操作。
圖5a-5d係描繪來自各種視圖的一SSE封裝200。圖5a係展示在圖4a-4f的視圖中的SSE封裝200的一橫截面。圖5b係描繪一橫截面圖，其中SSE封裝200係相對於圖5a向左或是向右轉九十度。儘管在圖5a-5d中的半導體晶粒124是一種兩個端子的裝置(例如，一個二極體)，但是具有額外的端子及額外的凸塊140的更複雜的半導體晶粒124係在其它實施例中類似地加以封裝。半導體晶粒124可以是一種兩個端子的裝置、一種三個端子的裝置(例如，一功率MOSFET)、或是具有更多個端子的，例如是一具有位址及資料匯流排的ASIC。
圖5c及5d係描繪SSE封裝200的一立體圖。圖5c是一外部的視圖，而圖5d係將密封劑186描繪為透明的，以露出在該密封劑之內的半導體晶粒124及凸塊140的結構。在圖5d中的虛線是只因為密封劑186是透明的，才為可見的線。
SSE封裝200係在沒有維持作為最後的封裝的部分之一基底引線架或基板的需求下加以形成，此係容許有一降低的封裝厚度。在某些實施例中，SSE封裝200的一厚度是大約0.150mm或是更低的。SSE封裝200的相當低的厚度係符合越來越小的裝置(尤其是可穿戴式裝置以及物聯網(IoT)裝置)的製造商的需要。SSE封裝200的容許內部的基板及引線接合的消除的結構係改善封裝可靠度、增進產品效能、並且簡化該組裝過程。例如是電阻、電感及電容的寄生的電性特徵也被降低。
SSE封裝200的不具有內部的焊料接合的結構係容許無鉛的焊料的使用於焊料蓋142，其係在一相對於傳統的錫-鉛焊料的較高溫下熔化。在其它封裝類型中，內部的焊料接合(例如是利用一球柵陣列或引線接合連接來用以將半導體晶粒124耦接至一引線架)可能會在將該最後的封裝安裝至一印刷電路板(PCB)或是其它基板時熔化。SSE封裝200可以在無鉛的焊料所需的較高溫下被安裝到一基板，而不會危及封裝完整性。具有焊料蓋142的柱凸塊140可以在晶圓層級被形成，並且直到SSE封裝200係利用該些焊料蓋而被附接在消費者的PCB上才加以回焊。SSE封裝200是薄的且輕量的，其係具有一改善的第二級的板可靠度以及由於簡化的製程流程的上市時間。
圖6a-6b係描繪形成一雙群封裝220，其係包含在同一個封裝中的兩個半導體晶粒124。如同在圖4f中，切割工具194係被用來單粒化半導體晶粒124。然而，對於某些半導體晶粒對的相鄰的半導體晶粒124並未被單粒化。雙群封裝220係包含可以連接至一PCB上的一對導電線路的兩個半導體晶粒124。圖7a-7b係描繪單粒化半導體晶粒124成為三個半導體晶粒的群組，以形成三群封裝230。半導體晶粒124可以針對於將在一電路板上一起被使用的裝置數量，而被單粒化為任意所要的配置。
圖8a-8d係描繪單次式封裝製程，其係在圖4a-4f中的流程的替代方案。在圖8a中，半導體晶圓120係如同在圖4c中地以主動表面130被定向朝向載體174下來加以設置，但是並無事先形成的溝槽170。若一PI層及/或RDL層是所要的，則來自圖2c或3的半導體晶圓120亦可被使用。在圖8b中，半導體晶粒124係如同在圖4d中地利用鋸刀或是雷射切割工具182而被單粒化。在某些實施例中，DRIE係被使用。密封劑186係如同在圖4e中地在圖8c中被沉積，並且被封入的半導體晶粒124係如同在圖4f中地在圖8d中被單粒化成為SSE封裝250。SSE封裝250係類似於SSE封裝200，但是該製程係在無溝槽170的形成下進行的。
圖9a-9f係描繪一用於單次式封裝的第三製程流程。在圖9a中，半導體晶圓120係如同在圖8a中地被背面研磨。在圖9b中，半導體晶圓120係以背表面178被定向朝向該熱解黏膠帶下，被安裝在熱解黏膠帶260之上。鋸刀或是雷射切割工具262係被用來穿過切割道126以單粒化半導體晶粒124。在單粒化之後，半導體晶粒124係被轉移安裝到支撐基底或是載體264之上，即如同在圖9c中所示者。UV或熱轉移帶266係在半導體晶粒124的安裝之前被設置在載體264上。在一實施例中，帶260是一熱解黏膠帶，並且帶266是一UV帶。在圖9d中，一升高的溫度係被用來在不釋放UV帶266之下移除熱解黏膠帶260。在另一實施例中，帶266是一熱解黏膠帶，而帶260是一UV解黏膠帶。
密封劑186係如同在圖4e中地在圖9e中被沉積，並且該被封入的半導體晶粒124係如同在圖4f中地在圖9f中被單粒化成為SSE封裝270。SSE封裝270係類似於SSE封裝200，但是該製程係如同在圖9a-9f中地進行。
圖10a係描繪該些SSE封裝中之一，其係被安裝到一PCB或是其它基板360之上。基板360係包含一導電層或是線路362，其係被形成在該基板的一表面之上。導電層362係根據需要而被圖案化，以實施一電子裝置的所要的功能。圖10a係展示SSE封裝230以作為一例子，但是所揭露的SSE封裝的任一個都可以類似地被安裝。SSE封裝230係在密封劑186接觸該基板之下，被設置在基板360上。焊料蓋142係接觸導電層362。在某些實施例中例如是由於一用於附接的黏著層、被設置在導電層362上的額外的焊料膏、或是裝置製造的其它邏輯實體，一偏移係存在於SSE封裝230與基板360之間。焊料蓋142係被回焊到導電層362之上，以將SSE封裝230機械式地接合及電連接至基板360。焊料142係實質內含在密封劑186的開口之內。
圖10b係描繪SSE封裝230被安裝在PCB 360之上以作為一電子裝置370的部分，其中複數個半導體封裝係和該SSE封裝一起被安裝在該PCB的一表面之上。電子裝置370可以根據應用而具有一種類型的半導體封裝、或是多種類型的半導體封裝。
電子裝置370可以是一獨立的系統，其係利用該些半導體封裝以執行一或多個電性功能。或者是，電子裝置370可以是一較大的系統的一子構件。例如，電子裝置370可以是一平板電腦、行動電話、數位相機、通訊系統、或是其它電子裝置的部分。電子裝置370亦可以是可被插入到一電腦中的一顯示卡、網路介面卡、或是其它的信號處理卡。該些半導體封裝可包含微處理器、記憶體、ASIC、邏輯電路、類比電路、RF電路、離散的裝置、或是其它半導體晶粒或電性構件。
在圖10b中，PCB 360係提供一個一般的基板，以用於被安裝在該PCB之上的半導體封裝的結構上的支撐及電互連。導電的信號線路362係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或是其它適當的金屬沉積製程而被形成在PCB 360的一表面之上、或是在PCB 360的層之內。信號線路362係提供用於在該些半導體封裝、所安裝的構件、以及其它外部的系統構件的每一個之間的電性通訊。線路362亦視需要地提供電源及接地連接至該些半導體封裝。
SSE封裝372是一利用在以上揭露的單次式封裝製程中之一所封裝的ASIC。SSE封裝230是該三群封裝，並且與三個相鄰的導電線路串聯焊接的。為了說明之目的，數種類型的第一層級的封裝(其係包含接合導線封裝390及覆晶382)係被展示在PCB 360上。此外，數種類型的第二層級的封裝(其係包含球柵陣列(BGA)384、凸塊晶片載體(BCC)392、平台柵格陣列(LGA)394、多晶片的模組(MCM)388、四邊扁平無引腳封裝(QFN)396、內嵌的晶圓層級球柵陣列(eWLB)386、以及晶圓級晶片尺寸封裝(WLCSP)380)係被展示安裝在PCB 360之上。在一實施例中，EWLB 386是一扇出晶圓層級的封裝(Fo-WLP)或是扇入晶圓層級的封裝(Fi-WLP)。依據該些系統需求，利用第一及第二層級的封裝類型以及其它電子構件的任意組合來加以配置的半導體封裝的任意組合都可以連接至PCB 360。
在某些實施例中，電子裝置370係包含單一附接的半導體封裝，而其它實施例係需要多個互連的封裝。藉由在單一基板之上組合一或多個半導體封裝，製造商可以將預製的構件納入到電子裝置及系統內。因為該些半導體封裝係包含複雜的功能，因此電子裝置可以利用較不昂貴的構件以及一精簡化的製程來加以製造。所產生的裝置係較不可能失效而且製造起來較不昂貴，此係產生較低的成本給消費者。
儘管本發明的一或多個實施例已經詳細地加以描述，但是本領域技術人員將會體認到可以在不脫離如同在以下的申請專利範圍中所闡述的本發明的範疇下，對於那些實施例做出修改及調適。
120‧‧‧半導體晶圓
122‧‧‧基底基板材料
124‧‧‧半導體晶粒(構件)
126‧‧‧切割道
128‧‧‧非主動表面
130‧‧‧主動表面
132‧‧‧導電層
134‧‧‧絕緣(介電)層
140‧‧‧低輪廓的柱凸塊
142‧‧‧焊料蓋
150‧‧‧聚醯亞胺(PI)層
152‧‧‧開口
160‧‧‧絕緣(介電)層
162‧‧‧導電層
164‧‧‧絕緣(鈍化)層
170‧‧‧溝槽
172‧‧‧雷射切割工具(鋸刀)
174‧‧‧基底支撐件
176‧‧‧背面研磨帶
178‧‧‧背表面
180‧‧‧背面研磨工具
182‧‧‧雷射切割工具(鋸刀)
186‧‧‧密封劑(模製化合物)
190‧‧‧載體
192‧‧‧解黏膠帶
194‧‧‧鋸刀(雷射切割工具、水切割工具)
200‧‧‧單次式封裝(SSE)的封裝
220‧‧‧雙群封裝
230‧‧‧三群封裝
250‧‧‧SSE封裝
260‧‧‧熱解黏膠帶
262‧‧‧雷射切割工具(鋸刀)
264‧‧‧支撐基底(載體)
266‧‧‧UV(熱)轉移帶
270‧‧‧SSE封裝270
360‧‧‧基板
362‧‧‧導電層(線路)
370‧‧‧電子裝置
372‧‧‧SSE封裝
380‧‧‧晶圓級晶片尺寸封裝(WLCSP)
382‧‧‧覆晶
384‧‧‧球柵陣列(BGA)
386‧‧‧內嵌的晶圓層級球柵陣列(eWLB)
388‧‧‧多晶片的模組(MCM)
390‧‧‧接合導線封裝
392‧‧‧凸塊晶片載體(BCC)
394‧‧‧平台柵格陣列(LGA)
396‧‧‧四邊扁平無引腳封裝(QFN)
圖1a-1e係描繪在一半導體晶圓上形成低輪廓的凸塊；
圖2a-2c係描繪在一鈍化層開口之上的低輪廓的凸塊；
圖3是描繪一低輪廓的凸塊以及重新分佈層；
圖4a-4f係描繪從一晶圓利用單次式封裝來封裝半導體晶粒；
圖5a-5d係描繪一利用單次式封裝所做成的半導體封裝；
圖6a-6b係描繪一利用單次式封裝所做成的雙群(gang)封裝；
圖7a-7b係描繪一利用單次式封裝所做成的三群封裝；
圖8a-8d係描繪一用於利用單次式封裝來封裝一半導體晶粒的第二製程流程；
圖9a-9f係描繪一用於利用單次式封裝來封裝一半導體晶粒的第三製程流程；以及
圖10a-10b係描繪一利用該半導體封裝的電子裝置。

Claims (15)

  1. 一種製造半導體裝置之方法，其包括： 提供半導體晶圓； 在該半導體晶圓之上形成複數個柱凸塊； 在該柱凸塊之上沉積焊料，該柱凸塊是在該焊料和該半導體晶圓之間； 在第一載體之上設置該半導體晶圓； 在形成該柱凸塊之後且該半導體晶圓仍然在該第一載體之上時，單粒化該半導體晶圓成為複數個半導體晶粒；以及 在單粒化該半導體晶圓之後，在該半導體晶粒以及該柱凸塊周圍沉積密封劑。
  2. 如申請專利範圍第1項之方法，其進一步包含在沉積該密封劑之前，在第二載體之上設置該半導體晶圓並且移除該第一載體。
  3. 如申請專利範圍第2項之方法，其中該半導體晶圓的背表面在單粒化期間被設置在該第一載體上，並且該半導體晶粒的主動表面在沉積該密封劑時被定向朝向該第二載體。
  4. 如申請專利範圍第2項之方法，其中在沉積該密封劑時，該焊料接觸該第二載體。
  5. 如申請專利範圍第1項之方法，其進一步包含切割穿過該密封劑以將該半導體晶粒分開為複數個半導體封裝，其中在該半導體封裝之一者中，複數個半導體晶粒藉由該密封劑保持連接。
  6. 如申請專利範圍第1項之方法，其進一步包含： 將該半導體晶粒設置在基板之上，而該密封劑接觸該基板；以及 將該焊料回焊到該基板的導電層之上。
  7. 一種製造半導體裝置之方法，其包括： 提供半導體晶圓； 在該半導體晶圓之上形成複數個柱凸塊； 在第一載體之上設置該半導體晶圓； 在該半導體晶圓仍然在該第一載體之上時，單粒化該半導體晶圓成為複數個半導體晶粒； 從該第一載體轉移安裝該半導體晶粒至第二載體；以及 在該半導體晶粒仍然在該第二載體上時，在該半導體晶粒以及該柱凸塊周圍沉積密封劑。
  8. 如申請專利範圍第7項之方法，其進一步包含在沉積該密封劑之前，在該柱凸塊之上沉積焊料。
  9. 如申請專利範圍第8項之方法，其進一步包含： 將該半導體晶粒設置在基板之上，而該密封劑接觸該基板；以及 將該焊料回焊到該基板的導電層之上。
  10. 如申請專利範圍第8項之方法，其中該焊料的表面與該密封劑的表面共平面。
  11. 一種半導體裝置，其包括： 半導體晶粒； 柱凸塊，被形成在該半導體晶粒之上； 焊料蓋，被形成在該柱凸塊之上；以及 密封劑，被沉積在該半導體晶粒、該柱凸塊和該焊料蓋之上。
  12. 如申請專利範圍第11項之半導體裝置，其中該密封劑的表面與該焊料蓋的表面共平面。
  13. 如申請專利範圍第11項之半導體裝置，其進一步包括重新分佈層，被形成在該半導體晶粒和該柱凸塊之間。
  14. 如申請專利範圍第11項之半導體裝置，其進一步包括藉由該密封劑彼此機械式連接的複數個半導體晶粒。
  15. 如申請專利範圍第14項之半導體裝置，其進一步包括基板，其中該複數個半導體晶粒藉由該焊料蓋被機械式連接至該基板。
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US11171099B2 (en) 2021-11-09
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TWI677034B (zh) 2019-11-11
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US10410988B2 (en) 2019-09-10
US20220028813A1 (en) 2022-01-27
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