CN104916592A - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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Publication number
CN104916592A
CN104916592A CN201410447288.7A CN201410447288A CN104916592A CN 104916592 A CN104916592 A CN 104916592A CN 201410447288 A CN201410447288 A CN 201410447288A CN 104916592 A CN104916592 A CN 104916592A
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China
Prior art keywords
wiring substrate
otch
laminate
metallic plate
semiconductor device
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CN201410447288.7A
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川户雅敏
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Toshiba Corp
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Toshiba Corp
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Abstract

本发明为抑制毛边的产生的半导体装置的制造方法及半导体装置。实施方式的半导体装置的制造方法中，以半导体芯片位于配线基板的第一面侧的方式，在配线基板的第一面上搭载积层体，且形成将积层体密封的密封树脂层，所述积层体包括金属板及积层于金属板的一部分之上的半导体芯片，通過以围绕著积层体的方式形成第一切口並以围绕著积层体的方式形成第二切口，而对应积层体将配线基板分离，第一切口是使用第一切割刀片将金属板及配线基板中的一个切断并到达密封树脂层，第二切口是使用第二切割刀片将金属板及配线基板中的另一个切断并到达第一切口。

Description

半导体装置的制造方法及半导体装置
关连申请
本申请享有以日本专利申请2014-52715号(申请日：2014年3月14日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置的制造方法及半导体装置。
背景技术
近年来，伴随通信技术或信息处理技术的发展，半导体装置的小型化及高速化的要求增高。为了应对此要求，半导体装置中，推进如下半导体封装的开发，该半导体封装的目的在于利用使多个半导体芯片积层的3维安装，而缩短零件间的配线的长度从而对应于动作频率的增大，并提高安装面积效率。
例如，在NAND(与非)型快闪存储器等半导体装置中，从小型化及高速化的观点来说，提出有一种在同一配线基板积层存储器控制器与存储器芯片的3维安装构造。作为3维安装构造，例如正研究TSV(Through Silicon Via，硅穿孔)方式的积层构造。
TSV方式的积层构造的半导体装置的制造中，是于金属板上积层多个半导体芯片，使用贯通半导体芯片的贯通电极进行半导体芯片间的电连接，由此形成积层体。然后，将该金属板上的积层体与配线基板加以贴合。此外，通过向半导体芯片与配线基板之间填充密封树脂而将积层体密封，并将外部连接端子形成于配线基板后，进行切割(dicing)从而相应于积层体而将配线基板分离。
切割步骤中，例如使用切割刀片将配线基板切断，但此时，会产生被称作毛边(burr)的突起。毛边是将切断对象物切削时所产生者，存在引起封装的厚膜化或短路等的可能性。因此，切割步骤中，优选尽可能少地产生毛边。
发明内容
实施方式的发明所欲解决的课题在于抑制毛边的产生。
实施方式的半导体装置的制造方法以半导体芯片位于配线基板的第一面侧的方式，对配线基板的第一面上搭载积层体，所述积层体包括金属板及积层于该金属板的一部分之上的半导体芯片，且在配线基板的第一面上形成将积层体密封的密封树脂层，通過以围绕著积层体的方式形成第一切口並以围绕著积层体的方式形成第二切口，而对应积层体将配线基板分离，第一切口是使用第一切割刀片将金属板及配线基板中的一个切断并到达密封树脂层，第二切口是使用第二切割刀片将金属板及配线基板中的另一个切断并到达第一切口。
附图说明
图1是表示半导体装置的制造方法例的流程图。
图2(A)～(C)是用以说明积层体的制造方法例的剖面图。
图3(A)～(C)是用以说明半导体装置的制造方法例的剖面图。
图4(A)及(B)是用以说明第一切入步骤的图。
图5(A)及(B)是用以说明第二切入步骤的图。
图6(A)及(B)是表示半导体装置的构造例的图。
图7(A)及(B)是用以说明半导体装置的制造方法的另一例的剖面图。
图8(A)及(B)是用以说明半导体装置的制造方法的另一例的剖面图。
图9是表示半导体装置的制造方法例的流程图。
图10(A)～(C)是用以说明半导体装置的制造方法例的剖面图。
具体实施方式
以下，参照附图对实施方式进行说明。另外，附图是示意性的图，例如厚度与平面尺寸的关系、各层的厚度的比率等有时与现实的情况有所不同。而且，实施方式中，对实质相同的构成要素附上相同的符号，并省略说明。
(第一实施方式)
图1是表示半导体装置的制造方法例的流程图。图1所示的半导体装置的制造方法例至少具备准备步骤(S1-1)、搭载步骤(S1-2)、密封步骤(S1-3)、端子形成步骤(S1-4)、第一切入步骤(S1-5)、第二切入步骤(S1-6)。另外，本实施方式中的半导体装置的制造方法例的步骤内容及步骤顺序不必限定为图1所示的步骤。
准备步骤(S1-1)是准备积层体的步骤，该积层体具备金属板、及设置于金属板的一部分之上的半导体芯片。积层体例如具有TSV方式的积层构造，且通过如下而形成：例如在金属板上积层多个半导体芯片，利用贯通半导体芯片的贯通电极而将半导体芯片间电连接。
搭载步骤(S1-2)是将所述积层体搭载于配线基板的步骤。此时，利用例如设置于积层体的上表面的凸块电极而与配线基板电连接。
密封步骤(S1-3)是将密封所述积层体的密封树脂层形成于配线基板上的步骤。例如，可使用转移成型法、压缩成型法、注射成型法等成型法而形成密封树脂层。
端子形成步骤(S1-4)是形成外部连接端子的步骤。例如，可在配线基板形成焊球而形成外部连接端子。另外，在利用接合线等将所述半导体装置与其他电子零件电连接的情况下也可不必设置端子形成步骤。
第一切入步骤(S1-5)是使用第一切割刀片形成第一切口的步骤。本步骤中形成第一切口直到密封树脂层的中途为止，并不使配线基板分离。
第二切入步骤(S1-6)是使用第二切割刀片形成第二切口的步骤。利用本步骤将配线基板分离。另外，也可将第一切入步骤(S1-5)与第二切入步骤(S1-6)合并而作为切割步骤。
另外，除所述步骤外，也可设置刻印产品名等产品信息的标记步骤、热处理步骤、在经标记的半导体装置中以至少覆盖密封树脂层的方式形成遮蔽层的遮蔽层形成步骤等。
此外，参照附图对各步骤进行说明。参照图2对准备步骤(S1-1)中准备的积层体11的制造方法例进行说明。图2是用以说明积层体11的制造方法例的剖面图。
首先，如图2(A)所示，在金属板12的一部分之上经由黏着层21而贴合半导体芯片22a。金属板12具有作为用以使例如半导体装置内部的热向外部散逸的散热板的功能。关于金属板12，例如可使用铜、铁、镍等金属或他们的合金等的金属板。例如，铜板因导热性高所以优选。作为黏着层21，例如可使用聚酰亚胺或环氧等树脂膜。
接下来，如图2(B)所示，使半导体芯片22b积层。进而，在最上层的半导体芯片22b上形成配线层26。进而，在配线层26上形成电极垫28。此处，作为一例，形成7层的半导体芯片22b的积层。
半导体芯片22b具有贯通电极25。多个半导体芯片22b经由黏着层24而彼此贴合，利用凸块电极23及贯通电极25而彼此电连接。此外，最下层的半导体芯片22b经由黏着层24而贴合于半导体芯片22a，利用凸块电极23及贯通电极25而与半导体芯片22a电连接。作为半导体芯片22a及半导体芯片22b，例如可使用存储器芯片等。作为存储器芯片，例如可使用NAND型快闪存储器等存储元件。另外，也可在存储器芯片中设置解码器等电路。另外，也可在半导体芯片22a设置贯通电极，利用贯通电极而与半导体芯片22b电连接。
作为凸块电极23，例如可使用金凸块或焊锡凸块，作为焊锡凸块，可使用锡-银系、锡-银-铜系的无铅焊锡。
作为配线层26的具体例，可列举将半导体芯片22b的电极垫进行再配置的再配线层。配线层26是设置于半导体芯片22b上的再配线层，且具有连接配线27。连接配线27与最上层的半导体芯片22b的贯通电极25电连接。
作为连接配线27及电极垫28，例如可使用铜、钛、氮化钛、铬、镍、金、或钯等的层。
接下来，如图2(C)所示，在配线层26上配置半导体芯片29。此外，使用底填充法等向半导体芯片22b间的间隙填充密封树脂30。通过以上而形成积层体11。
作为半导体芯片29，例如可使用倒装芯片型的半导体芯片，经由焊球等外部连接端子而与连接配线27电连接。作为半导体芯片29，例如可使用接口芯片或控制器芯片。例如在半导体芯片22b为存储器芯片的情况下，半导体芯片29使用控制器芯片，利用控制器芯片来控制对存储器芯片的写入及读取。另外，半导体芯片29优选小于半导体芯片22b。即，半导体芯片29优选设置于半导体芯片22b的一部分之上。
如参照图2所说明般，积层体11具备：金属板12，设置于金属板12的一部分之上的半导体芯片(半导体芯片22a及半导体芯片22b)，设置于半导体芯片22b上且具有连接配线27的配线层26，及设置于配线层26上且经由连接配线27而与半导体芯片22b电连接的半导体芯片29。半导体芯片22b具有贯通芯片的贯通电极25，利用贯通电极25将芯片间电连接。如此，通过使用TSV方式的积层构造的积层体11，而可减小芯片面积，可增多连接端子数，因而可抑制连接不良等。另外，也可在一个金属板12形成多个积层体11，针对每个积层体11分离金属板12，由此形成一个积层体11。
接下来，参照图3对搭载步骤(S1-2)、密封步骤(S1-3)及端子形成步骤(S1-4)进行说明。图3是用以说明半导体装置的制造方法例的剖面图，图3(A)是用以说明搭载步骤(S1-2)的图，图3(B)是用以说明密封步骤(S1-3)的图，图3(C)是用以说明端子形成步骤(S1-4)的图。
搭载步骤(S1-2)中，如图3(A)所示，以半导体芯片位于配线基板10的第一面侧的方式，在配线基板10的第一面搭载积层体11。积层体11利用焊锡材料13而与配线基板10电连接。例如，也可在将积层体11与配线基板10临时黏着后，通过回焊进行正式黏着，由此搭载积层体11。
作为配线基板10，例如可使用具有设置于表面的配线层的玻璃环氧等树脂基板等。另外，配线基板10的第一面相当于图3(A)中的配线基板10的上表面，第二面相当于图3(A)中的配线基板10的下表面，配线基板10的第一面及第二面彼此对向。
密封步骤(S1-3)中，如图3(B)所示，以将积层体11密封的方式，在配线基板10的第-面上形成密封树脂层14。例如，可通过填充密封树脂而形成密封树脂层。密封步骤(S1-3)中，优选使金属板12的表面的至少一部分露出。另外，在金属板12上填充密封树脂的情况下，通过研磨等使金属板12露出，可提高半导体装置的散热性。
作为密封树脂，可使用含有SiO2等无机填充材料且例如将无机填充材料与绝缘性的有机树脂材料等加以混合而成者，例如可使用与环氧树脂混合者。无机填充材料含有为整体的80％～95％，且具有对密封树脂层的粘度或硬度等进行调整的功能。
端子形成步骤(S1-4)中，如图3(C)所示，在配线基板10的第二面形成外部连接端子15。例如，在配线基板10的第二面上涂布助焊剂后，搭载焊球，放入到回焊炉中而使焊球熔融，从而与配线基板10所具有的连接垫接合。然后，通过溶剂或纯水洗净而将助焊剂除去，由此可形成外部连接端子15。
接下来，参照图4及图5对第一切入步骤(S1-5)及第二切入步骤(S1-6)进行说明。此处，作为一例，说明将多个配线基板10呈矩阵状连设的构造的集合基板1加以分离的情况。
图4是用以说明第一切入步骤(S1-5)的图，图4(A)表示集合基板1的透视俯视图，图4(B)是图4(A)的线段X-Y的剖面图。第一切入步骤(S1-5)中，以包围积层体11的方式，使用切割刀片B1而形成切口C1。此处，将金属板12切断，并且形成到达密封树脂层14的切口C1(参照图4(A)及图4(B))。例如，可将配线基板10固定于切割带或固定治具等而进行第一切入步骤(S1-5)。
此时，在切口C1的周边部产生毛边。毛边是在利用切割刀片切削对象物的过程中因对象物的一部分被挤压至表面而产生的突起。尤其金属板12因以SiO2等无机填充材料作为主成分，所以与硬的树脂密封层14不同而具有延性。因此，如果欲切削金属板12，则以金属板12的一部分被挤压至表面的方式而容易在切口C1的周边产生毛边。
本实施方式的半导体装置的制造方法中，第一切入步骤(S1-5)中，从金属板12侧切断金属板12并且形成切口仅到密封树脂层14的中途为止，并不使配线基板10分离。由此，可在由以硬度高的无机填充材料作为主成分的密封树脂层14支持的状态下，来切削金属板12。而且，可减少密封树脂层14的切削量。由此，因被挤压至表面的切削物的量减少，所以可减少毛边。毛边的高度优选例如小于等于100μm。另外，配线基板10中因可使用比环氧基板等金属板12柔软的材料，所以在切口C2的周边部极少产生或不会产生毛边。
图5是用以说明第二切入步骤(S1-6)的图，图5(A)表示集合基板1的透视俯视图，图5(B)表示图5(A)中的线段X-Y的剖面图。第二切入步骤(S1-6)中，以包围积层体11的方式使用切割刀片B2形成切口C2。此处，将配线基板10切断并且形成到达切口C1的切口C2(参照图5(A)及图5(B))。通过第二切入步骤(S1-6)，相应于积层体11而将配线基板10分离。例如，可将配线基板10固定于切割带或固定治具等而进行第二切入步骤(S1-6)。另外，例如图5(A)及图5(B)等中，为了方便而以使切割刀片B2从下方向开始进入的方式加以图示，但优选在第一切入步骤(S1-5)之后，使配线基板10的面反转并固定而形成切口C2。
作为切割刀片B1及切割刀片B2，例如可使用金刚石刀片等。可通过切削供旋转的金刚石刀片抵接的对象物而形成切口。此时，切割刀片B1的厚度D1例如小于等于0.2mm，优选小于等于0.15mm，切割刀片B2的厚度D2优选大于等于0.3mm。
如果不使切口C1与切口C2重叠则难以将配线基板10分离，但切口C1及切口C2的位置对准困难。因此，通过设为如下构成，即，在切割刀片B1及切割刀片B2中的一者具有第一厚度时，切割刀片B1及切割刀片B2中的另一者具有比第一厚度厚的第二厚度，从而即便在切口C1与切口C2完全不重叠的情况下，也可容易使切口C1与切口C2中的至少一部分重叠，因而可容易将配线基板10分离。
切口C1的深度及切口C2的深度也可不同。例如，在切断配线基板10而形成的切口(图5(B)中为切口C2)具有第一深度时，切断金属板12而形成的切口(图5(B)中为切口C1)具有比第一深度浅的第二深度，由此可削减将容易出现毛边的金属板12切削时的树脂密封层14的切削量，因此可减少毛边。另外，减少毛边包括降低毛边的高度。
将经过所述第一切入步骤(S1-5)及第二切入步骤(S1-6)而形成的半导体装置的构造例表示于图6中。图6(A)是俯视图，图6(B)是图6(A)中的线段A-B的剖面图。图6(A)及图6(B)所示的半导体装置具备：配线基板10，其具有彼此对向的第一面及第二面；积层体11，其具备金属板12、及积层于金属板12上的半导体芯片(半导体芯片22a、22b、29)，且以半导体芯片位于配线基板10的第一面侧的方式设置于配线基板10的第一面；及密封树脂层14，其在配线基板10的第一面上，使金属板12的第二面露出并且将积层体11密封。
此外，半导体装置包括：侧面F1，其以包围积层体11的方式，从金属板12的侧面不间断地连续设置到密封树脂层14的侧面的一部分为止；以及侧面F2，以包围积层体11的方式，从配线基板10的侧面不间断地连续设置到密封树脂层14的侧面的一部分为止。侧面F1与侧面F2之间设置有阶差L。另外，如所述般使第二深度比第一深度浅可减少毛边，因此使阶差L与金属板12的距离比阶差L与配线基板10的距离小可减少毛边。而且，半导体装置的厚度例如可设为1.2～1.5mm左右。此外，第二切入步骤(S1-6)的后续步骤中，也可通过研磨等除去毛边。
另外，说明如下示例，即，第一切入步骤(S1-5)中，从金属板12侧形成切口，然后第二切入步骤(S1-6)中，从配线基板10侧形成切口，也可使第一切入步骤(S1-5)及第二切入步骤(S1-6)中形成切口的部位相反。
例如，图7是用以说明半导体装置的制造方法的另一例的剖面图，图7(A)是用以说明第一切入步骤(S1-5)的剖面图，图7(B)是用以说明第二切入步骤(S1-6)的剖面图。另外，关于与参照图2至图5说明的半导体装置的制造方法相同的部分，可适当引用该制造方法的说明。
如图7(A)所示，第一切入步骤(S1-5)中，以围绕着积层体11的方式使用切割刀片B2形成切口C2。此处，切断配线基板10并且形成到达密封树脂层14的切口C2。然后，如图7(B)所示，第二切入步骤(S1-6)中，以围绕着积层体11的方式使用切割刀片B1形成切口C1，由此相应于积层体11而将配线基板10分离。此处，切断金属板12并且形成到达切口C2的切口C1。如此，本实施方式的半导体装置的制造方法中，可使第一切入步骤(S1-5)及第二切入步骤(S1-6)中形成切口的部位相反。
此外，图4及图5中，表示如下示例，即，第一切入步骤(S1-5)中，使用切割刀片B1，第二切入步骤(S1-6)中，使用比切割刀片B1厚的切割刀片B2，也可使第一切入步骤(S1-5)及第二切入步骤(S1-6)中所使用的切割刀片相反。
例如，图8是用以说明半导体装置的制造方法的另一例的剖面图，图8(A)是用以说明第一切入步骤(S1-5)的剖面图，图8(B)是用以说明第二切入步骤(S1-6)的剖面图。另外，关于与参照图2至图5说明的半导体装置的制造方法例相同的部分，适当引用该制造方法例的说明。
如图8(A)所示，第一切入步骤(S1-5)中，以围绕着积层体11的方式使用切割刀片B2形成切口C1。此处，切断金属板12并且形成到达密封树脂层14的切口C1。然后，如图8(B)所示，第二切入步骤(S1-6)中，以围绕着积层体11的方式，使用切割刀片B1形成切口C2，由此相应于积层体11而将配线基板10分离。此处，切断配线基板10并且形成到达切口C1的切口C2。如此，本实施方式的半导体装置的制造方法中，可使第一切入步骤(S1-5)及第二切入步骤(S1-6)中所使用的切割刀片相反。
如以上般，本实施方式中，通过将切割步骤分为第一切入步骤及第二切入步骤，而可减少切削金属板时所产生的毛边。由此，可抑制例如半导体封装的厚膜化或短路等的产生。
(第二实施方式)
本实施方式中，对与第一实施方式不同的步骤顺序的半导体装置的制造方法进行说明。
图9是表示半导体装置的制造方法例的流程图。图9所示的半导体装置的制造方法例至少具备准备步骤(S2-1)、搭载步骤(S2-2)、密封步骤(S2-3)、第一切入步骤(S2-4)、端子形成步骤(S2-5)、及第二切入步骤(S2-6)。另外，准备步骤(S2-1)对应于图1的准备步骤(S1-1)，搭载步骤(S2-2)对应于图1的搭载步骤(S1-2)，密封步骤(S2-3)对应于图1的密封步骤(S1-3)。由此，关于准备步骤(S2-1)至密封步骤(S2-3)，可适当引用第一实施方式的半导体装置的制造方法的说明。
此外，参照图10对第一切入步骤(S2-4)、端子形成步骤(S2-5)及第二切入步骤(S2-6)进行说明。
图10是用以说明本实施方式的半导体装置的制造方法的图，图10(A)是用以说明第一切入步骤(S2-4)的剖面图，图10(B)是用以说明端子形成步骤(S2-5)的剖面图，图10(C)是用以说明第二切入步骤(S2-6)的剖面图。
经过准备步骤(S2-1)至密封步骤(S2-3)而形成的半导体装置的一例如图10(A)及图10(B)所示，具备：配线基板10，其具有彼此对向的第一面及第二面；积层体11，其具备金属板12、及积层于金属板12的一部分之上的半导体芯片；及密封树脂层14，其将积层体11密封。另外，关于与参照图2至图5说明的半导体装置的构造相同的部分，可适当引用该半导体装置的说明。
第一切入步骤(S2-4)中，如图10(A)所示，以包围积层体11的方式，使用切割刀片B1形成切口C1。此处，切断金属板12并且形成到达密封树脂层14的切口C1(参照图10(A))。
端子形成步骤(S2-5)中，如图10(B)所示，在配线基板10的第二面形成外部连接端子15。关于外部连接端子15，可适当引用第一实施方式的外部连接端子15的说明。
第二切入步骤(S2-6)中，如图10(C)所示，以包围积层体11的方式，使用切割刀片B2形成切口C2。此处，切断配线基板10并且形成到达切口C1的切口C2。通过第二切入步骤(S2-6)，相应于积层体11而将配线基板10分离。关于切割刀片B1及切割刀片B2，可适当引用参照图4及图5所说明的切割刀片B1及切割刀片B2的说明。
本实施方式的半导体装置的制造方法中，因在进行端子形成步骤(S2-5)前进行第一切入步骤，所以在第一切入步骤(S2-4)中，当将配线基板10固定于切割带或固定治具等时可增大与配线基板10的设置面。又，在第一切入步骤(S2-4)中，通过将金属板12切断，而可在第二切入步骤(S2-6)中，在与固定面为相反侧的面配置形成外部连接端子15的面，因此可使用与第一切入步骤(S2-5)相同的固定治具等。
另外，与第一实施方式同样地，也可使第一切入步骤(S2-5)及第二切入步骤(S2-6)中所使用的切割刀片相反。而且，也可与第一实施方式同样地使切口C1与切口C2的深度不同。
如以上般，本实施方式中，于在配线基板形成外部连接端子前进行切割步骤的一部分(第一切入步骤)，由此除可抑制毛边外，且可提高切割时的稳定性，然后，通过进行切割步骤的剩余部分(第二切入步骤)，而可抑制切割时芯片从切割带等剥离。
另外，各实施方式作为示例而提示，并不旨在限定发明的范围。这些新颖的实施方式可由其他各种形态而实施，在不脱离发明的主旨的范围内，可进行各种省略、置换、变更。这些实施方式或其变形包含于发明的范围或主旨内，并且包含于权利要求所记载的发明及其均等的范围内。
[符号说明]
1   集合基板
10  配线基板
11  积层体
12  金属板
12a 毛边
13  外部连接端子
14  密封树脂层
15  外部连接端子
21  黏着层
22a 半导体芯片
22b 半导体芯片
23  外部连接端子
24  黏着层
25  贯通电极
26  配线层
27  连接配线
28  电极垫
29  半导体芯片
30  密封树脂

Claims (5)

1.一种半导体装置的制造方法，其特征在于：以半导体芯片位于配线基板的第一面侧的方式，在所述配线基板的所述第一面上搭载积层体，所述积层体包括金属板及积层于所述金属板的一部分之上的半导体芯片；
在所述配线基板的所述第一面上形成将所述积层体密封的密封树脂层；
通過以围绕著所述积层体的方式形成第一切口並以围绕著所述积层体的方式形成第二切口，而对应所述积层体将所述配线基板分离，所述第一切口是使用第一切割刀片将所述金属板及所述配线基板中的一个切断并到达所述密封树脂层，所述第二切口是使用第二切割刀片将所述金属板及所述配线基板中的另一个切断并到达所述第一切口。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于：
至少在形成所述第二切口前，在所述配线基板的与所述第一面对向的第二面上形成外部连接端子。
3.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：
所述第一切割刀片及所述第二切割刀片的一侧具有第一厚度；
所述第一切割刀片及所述第二切割刀片的另一侧具有比所述第一厚度厚的第二厚度。
4.根据权利要求1或2所述的半导体装置的制造方法，其特征在于：
所述第一切口及所述第二切口中的将所述配线基板切断而形成的切口具有第一深度；
所述第一切口及所述第二切口中的将所述金属板切断而形成的切口具有比所述第一深度浅的第二深度。
5.一种半导体装置，其特征在于：包括：
配线基板，其包括彼此对向的第一面及第二面；
积层体，其包括金属板及积层于所述金属板上的半导体芯片，且以所述半导体芯片位于所述配线基板的所述第一面侧的方式，搭载于所述配线基板的所述第一面上；
密封树脂层，其以使所述金属板的至少一部分露出并且将所述积层体密封的方式设置于所述配线基板的所述第一面上；
第一侧面，其以围绕着所述积层体的方式，从所述金属板的侧面不间断地连续延伸到所述密封树脂层的侧面的一部分为止；
第二侧面，其以围绕着所述积层体的方式，从所述配线基板的侧面不间断地连续延伸到所述密封树脂层的侧面的一部分为止；且
在所述第一侧面与所述第二侧面之间设置有阶差。
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