TWI621241B - 半導體晶片及具有半導體晶片之半導體裝置 - Google Patents

半導體晶片及具有半導體晶片之半導體裝置 Download PDF

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TWI621241B
TWI621241B TW103109664A TW103109664A TWI621241B TW I621241 B TWI621241 B TW I621241B TW 103109664 A TW103109664 A TW 103109664A TW 103109664 A TW103109664 A TW 103109664A TW I621241 B TWI621241 B TW I621241B
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semiconductor wafer
semiconductor
wafer
substrate
silicon substrate
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TW103109664A
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TW201507097A (zh
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畑澤秋彥
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盧森堡商經度半導體責任有限公司
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
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Abstract

提供一種在層積複數個半導體晶片來形成晶片層積體之際，具有半導體晶片彼此難以在半導體晶片的面方向偏位的構成的半導體晶片；和具有此種半導體晶片的半導體裝置。
本發明的半導體晶片(10)，設有：具有絕緣性的基板(矽基板(21))；和設置在基板之一方的面的複數個凸塊電極(表面凸塊電極(22))；和設置在基板之另一方的面的複數個凹部(23)；和配置在凹部(23)內的焊料層(24)。凹部(23)，是形成開口面積由基板(21)之另一方的面側向著一方的面側變小。

Description

半導體晶片及具有半導體晶片之半導體裝置
本發明是關一種應用於CoC(Chip on Chip：疊層晶片)的半導體晶片、及具有該半導體晶片的CoC型的半導體裝置。
近年隨著電子機器的小型化和高功能化，提供一種層積具有電極的複數個半導體晶片的CoC型的半導體裝置。
作為此種半導體裝置之製造方法的一例，於專利文獻1(日本特開第2010-251347號公報)揭示一種將具有電極的半導體晶片彼此，一邊將凸塊電極彼此互相連接、一邊層積，形成晶片層積體，在該晶片層積體固定在配線基板上，形成半導體裝置的方法。以不會在各半導體晶片，因熱應力產生電極彼此的連接部的破裂和半導體晶片本身的裂痕的方式，在晶片層積體，以覆蓋已層積的半導體晶片彼此之間與各半導體晶片的周圍的方式，填充 底層填材(密封樹脂)。
而且，於專利文獻2(日本特開第2005-277059號公報)揭示一種在背面凹陷的凹部(背面側連接構件)層積具有與表面凸塊電極(表面側連接構件)的接合面的複數個半導體晶片所成的半導體裝置。在已凹陷的凹部設有接合面，藉此在將半導體晶片利用接合工具保持之際，接合工具的表面與接合面並未接觸。即使接合面受接合工具加壓被壓壞，仍難以接觸到相鄰接的配線等。像這樣，即使接合面壓壞仍難以接觸到相鄰接的配線等，因此難以產生短路。
〔先行技術文獻〕 〔專利文獻〕
〔專利文獻1〕日本特開第2010-251347號公報
〔專利文獻2〕日本特開第2005-277059號公報
在CoC型的半導體裝置中，在形成晶片層積體之際，複數個半導體晶片層積成各半導體晶片的電極彼此隔著焊料層而連接。然而，所層積的半導體晶片的電極分別以略平坦的面構成，因此在固定各半導體晶片的電極彼此之際，於加壓時，一旦稍微對半導體晶片的面方向施力，電極彼此就會隔著焊料層而滑動，引起位置偏移。因 此，有可能無法將電極彼此良好的固定。
在專利文獻1揭示的半導體裝置之製造方法中，在形成晶片層積體之際，無法抑制電極彼此之間的滑動。因此，在因加壓及加熱使焊料層硬化的工程中，半導體晶片彼此會隔著焊料層而滑動，很容易在半導體晶片的面方向產生位置偏移。
在專利文獻2所揭示的半導體裝置的構成中，對表面凸塊電極的外形而言，凹部的形狀形成很大，因此在表面凸塊電極與凹部的側面之間產生間隙。因而，在半導體晶片彼此接合之際，表面凸塊電極會在凹部內固定的位置產生落差，結果會有：半導體晶片彼此在半導體晶片的面方向位置偏移而連接的問題。
本發明之目的在於提供一種在層積複數個半導體晶片來形成晶片層積體之際，具有半導體晶片彼此難以在半導體晶片的面方向位置偏移的構成的半導體晶片；和具有此種半導體晶片的半導體裝置。
為了達成前述之目的，本發明的半導體晶片，設有：具有絕緣性的基板；和設在基板之一方的面的複數個凸塊電極；和設在基板之另一方的面的複數個凹部；和配置在凹部內的焊料層。凹部，是開口面積由基板之另一方的面側向著一方的面側變小為其特徵。
若藉由本發明，藉由在凹部設在半導體晶片之另一方的面，在層積複數個半導體晶片之際，表面凸塊電極在凹部內被收容成覆蓋在焊料層，因此難以在半導體晶片的面方向產生位置偏移。除此之外，該凹部是形成開口面積由基板之另一方的面側向著一方一方的面側變小，表面凸塊電極變得很容易配置在凹部的中心部，因此更難以在半導體晶片的面方向產生位置偏移。
1‧‧‧半導體裝置
10‧‧‧半導體晶片
10a‧‧‧第1半導體晶片
10b‧‧‧第2半導體晶片
10c‧‧‧第3半導體晶片
11‧‧‧晶片積層體
12‧‧‧配線基板
12a‧‧‧絕緣基材
12b‧‧‧絕緣膜
13‧‧‧底層填材
14‧‧‧密封樹脂
15‧‧‧連接銲墊
16‧‧‧焊盤
17‧‧‧焊球
18‧‧‧焊線凸塊
19‧‧‧接著構件
20‧‧‧連通部
21‧‧‧矽基板
22‧‧‧表面凸塊電極
23‧‧‧凹部
24‧‧‧焊料層
25‧‧‧導體層
26‧‧‧間隙
27‧‧‧電路形成層
28‧‧‧電極銲墊
29‧‧‧鍍Ni(鎳)層
30‧‧‧鍍Au(金)層
33‧‧‧接合工具
33a‧‧‧吸引孔
34‧‧‧接合工具
34a‧‧‧吸引孔
35‧‧‧分配器
36‧‧‧塗佈平台
37‧‧‧塗佈用薄片
40‧‧‧第1開口部
41‧‧‧第2開口部
42‧‧‧保護膜
43‧‧‧貫通孔
第1圖是表示具有本發明之第1實施形態的半導體晶片之半導體裝置的剖面圖。
第2a圖是表示本發明之第1半導體晶片的平面圖。
第2b圖是第2a圖之A-A’線剖面圖。
第3a圖是表示第1實施形態的第2半導體晶片的平面圖。
第3b圖是第3a圖之B-B’線剖面圖。
第4a圖是表示第1實施形態的第3半導體晶片的平面圖。
第4b圖是第4a圖之C-C’線剖面圖。
第5圖是表示第1實施形態的第2半導體晶片的表面凸塊電極近傍的放大剖面圖。
第6a圖是表示層積第1實施形態的半導體晶片來形 成晶片層積體的工程的剖面圖。
第6b圖是表示層積第1實施形態的半導體晶片來形成晶片層積體的工程的剖面圖。
第6c圖是表示層積第1實施形態的半導體晶片來形成晶片層積體的工程的剖面圖。
第7a圖是表示在層積第1實施形態的半導體晶片之際，抑制位置偏移而層積的程製的剖面圖。
第7b圖是表示在層積第1實施形態的半導體晶片之際，抑制位置偏移而層積的程製的剖面圖。
第8a圖是表示在層積第1實施形態的半導體晶片的晶片層積體填充底層填材的工程的剖面圖。
第8b圖是表示在層積第1實施形態的半導體晶片的晶片層積體填充底層填材的工程的剖面圖。
第9a圖是表示形成構成第1實施形態的半導體晶片的半導體裝置的工程的剖面圖。
第9b圖是表示形成構成第1實施形態的半導體晶片的半導體裝置的工程的剖面圖。
第9c圖是表示形成構成第1實施形態的半導體晶片的半導體裝置的工程的剖面圖。
第9d圖是表示形成構成第1實施形態的半導體晶片的半導體裝置的工程的剖面圖。
第9e圖是表示形成構成第1實施形態的半導體晶片的半導體裝置的工程的剖面圖。
第10圖是表示本發明之第1實施形態的半導體晶片 之變形例的表面凸塊電極近傍的剖面圖。
第11圖是表示本發明之第2實施形態的半導體晶片的表面凸塊電極近傍的剖面圖。
以下針對本發明之實施形態參照圖面做說明。
(第1實施形態)
第1圖是表示使用本發明之第1實施形態的半導體晶片構成的半導體裝置的剖面圖。
本實施形態的半導體裝置1中，由：一片的第1半導體晶片10a、三片的第2半導體晶片10b、一片的第3半導體晶片10c製成的晶片層積體11，是搭載成與第3半導體晶片10c之一方的面和配線基板12之一方的面相對向。在晶片層積體11的各半導體晶片10彼此的間隙填充底層填材13。在第3半導體晶片10c與配線基板12之間填充接著構件19。密封樹脂14覆蓋晶片層積體11的周圍。
以下，詳細說明半導體裝置1的構成。
配線基板12，具有：在兩面形成圖未表示的配線的矩形絕緣基材12a(例如玻璃環氧基板)，除了後述的連接銲墊15和焊盤(land)16之外，各配線覆蓋在絕緣膜12b(例如抗焊膜)。在配線基板12之一方的面 隔著焊線凸塊18，形成著連接在第3半導體晶片10c的複數個連接銲墊15。在配線基板12之另一方的面，與成為外部端子的焊球17連接的複數個焊盤16以既定的間隔形成。連接銲墊15與焊盤16，是藉由形成在絕緣基材12a的配線，電性連接。
形成在配線基板12之一方的面的連接銲墊15和晶片層積體11的第3半導體晶片10c之一方的面的表面凸塊電極22(凸塊電極)，是以隔著焊線凸塊18電性連接的方式，在配線基板12之一方的面搭載著晶片層積體11。晶片層積體11，具有：按照層積在配線基板12的順序，層積著一片的第3半導體晶片10c、三片的第2半導體晶片10b、一片的第1半導體晶片10a的構成。以在第3半導體晶片10c之另一方的面的凹部23內的焊料層24，連接著第2半導體晶片10b之一方的面的表面凸塊電極22的方式，在第3半導體晶片10c之上層積著第2半導體晶片10b。以在第一片的第2半導體晶片10b之另一方的面的凹部23內的焊料層24，連接著第二片的第2半導體晶片10b之一方的面的表面凸塊電極22的方式，層積著第2半導體晶片10b彼此。而且，第三片的第2半導體晶片10b，是與第二片的第2半導體晶片10b相樣的被層積。以在第三片的第2半導體晶片10b之另一方的面的凹部23內的焊料層24，連接著第1半導體晶片10a之一方的面的表面凸塊電極22的方式，層積著第三片的第2半導體晶片10b與第1半導體晶片10a。本實施形態中， 作為構成晶片層積體11的半導體晶片10，採用複數個記憶體晶片與介面晶片。
在晶片層積體11之所層積的半導體晶片10彼此之間與其周圍，填充底層填材13。在配線基板12與晶片層積體11的第3半導體晶片10c之間，填充例如NCP(Non Conductive Paste：非導電性絕緣膠)等的接著構件19。密封樹脂14，是形成覆蓋搭載在配線基板12之一方的面的晶片層積體11的周圍。密封樹脂14，於平面觀看，形成在與配線基板12相同的範圍。
第2a圖、第2b圖是表示構成晶片層積體11的第1半導體晶片10a的圖。第1半導體晶片10a是以矩形的矽基板21(基板)構成，在矽基板21之一方的面，整面設有電路形成層27及圖未表示的絕緣性的保護膜。而且，複數個表面凸塊電極22，是形成在矽基板21之一方的面的中央區域，成為平行於矽基板21之一邊的列。
第3a圖、第3b圖是表示構成晶片層積體11的第2半導體晶片10b的圖。第2半導體晶片10b，是利用與第1半導體晶片10a相同尺寸的矩形矽基板21構成，在矽基板21之一方的面，全面設有電路形成層27及絕緣性的保護膜42(參照第5圖)。而且，複數個表面凸塊電極22，是形成在矽基板21之一方的面的中央區域，成為平行於矽基板21之一邊的列。在矽基板21之另一方的面，是由矽基板21之另一方的面側向著一方的面側而為錐狀的複數個凹部23，是在矽基板21的中央區域 形成成為平行於矽基板21之一邊及矽基板21之一方的面的表面凸塊電極22之列的列。該凹部23，是設於形成在矽基板21之一方的面的表面凸塊電極22的正下方，在內部設有例如：由Sn(錫)/Ag(銀)焊料製成的導電性的焊料層24。而且，由凹部23向著矽基板21之一方的面，在以一定的開口面積貫通的連通部內，收容著例如：由Cu(銅)製成的導電性的導體層25。
第5圖是表示第2半導體晶片10b的表面凸塊電極22的周圍的構成之放大剖面圖。表面凸塊電極22，是形成例如：由Cu製成的圓柱形狀，且設成自矽基板21之一方的面突出。在表面凸塊電極22上，形成著Cu擴散防止用的鍍Ni(鎳)層29與氧化防止用的鍍Au(金)層30。表面凸塊電極22與凹部23內的焊料層24，是隔著收容在電極銲墊28及連通部20的導體層25電性連接。
第4a圖、第4b圖是表示構成晶片層積體11的第3半導體晶片10c的圖。第3半導體晶片10c，是利用平面比第1半導體晶片10a還小的矩形矽基板21構成。在矽基板21之一方的面，全面設有電路形成層27及圖未表示的絕緣性的保護膜。而且，複數個表面凸塊電極22，是形成在與第2半導體晶片10b之一方的面設有表面凸塊電極22的位置相比更靠近矽基板21之一方的面的端部側的位置，成為平行於矽基板21之一邊的列。在矽基板21之另一方的面，由矽基板21之另一方的面側向著一 方的面側而為錐狀的複數個凹部23，是在矽基板21的中央區域形成成為平行於矽基板21之一邊及矽基板21之一方的面的表面凸塊電極22之列的列。該凹部23，是自表面凸塊電極22形成在矽基板21之一方的面的位置的正下方起，設在靠近矽基板21之端部側的位置。除此之外，在凹部23內，設有例如：由Sn/Ag焊料製成的導電性的焊料層24。而且，由凹部23向著矽基板21之一方的面，在以一定的開口面積貫通的連通部20，收容著例如：由Cu製成的導電性的導體層25。表面凸塊電極22與凹部23內的焊料層24，是隔著收容在連通部20的導體層25及電路形成層27電性連接。
其次，針對製造具有以上說明的構成的半導體裝置1的工程，參照第6a圖~第9e圖做說明。
首先，為了形成晶片層積體11，如第6a圖所示，第1半導體晶片10a是配置成使第1半導體晶片10a之另一方的面接觸到具有複數個吸引孔33a的接合平台33。已配置的第1半導體晶片10a，是利用在吸引孔33a產生的負壓而保持在接合平台33。
一方面，第2半導體晶片10b，是利用在接合工具34的吸引孔34a產生的負壓保持在接合工具34，接合工具34會使第2半導體晶片10b往接合平台33的正上方移動。而且，第2半導體晶片10b是在第1半導體晶片10a之上積層成連接著第1半導體晶片10a的表面凸塊電極22和第2半導體晶片10b的凹部23內的焊料層24。 以同樣的順序，在第一片的第2半導體晶片10b之上，層積著第二片及第三片的第2半導體晶片10b。而且，此時，焊料層24，未硬化且具有流動性。
此時，如第7a圖所示，位在下方的半導體晶片的表面凸塊電極22，是在未配置在位於上方的半導體晶片的凹部23之中心的狀態下，一旦半導體晶片10彼此層積層，即為當初在半導體晶片10的面方向位置偏移的狀態。然而，本實施形態的半導體晶片10的凹部23為錐狀，在使半導體晶片10彼此更接近的過程中，如第7b圖所示，表面凸塊電極22沿著凹部23的傾斜滑動，變得易於收容到凹部23的中心。因而，在半導體晶片10彼此之層積時，變得難以在半導體晶片10的面方向產生位置偏移。
接著，如第6b圖所示，層積著第3半導體晶片10b。第3半導體晶片10c，是利用在吸引孔34b產生的負壓保持在接合工具34，接合工具34會使第3半導體晶片10c往接合平台33的正上方移動。而且，第3半導體晶片10c是在第三片的第2半導體晶片10b之上，層積成連接著第三片的第2半導體晶片10b的表面凸塊電極22和第3半導體晶片10b的凹部23內的焊料層24。若層積各半導體晶片10的話，各半導體晶片10的各個的焊料層24會硬化。
如以上所成，層積著複數個半導體晶片10，而形成晶片層積體11。
已形成的晶片層積體11，如第8a圖所示，配置在一方之面以塗佈用薄片37覆蓋的塗佈平台36。而且，藉由分配器35在晶片層積體11的間隙26(參照第7a圖、第7b圖)填充底層填材13。對塗佈用薄片37塗佈氟系薄片和矽系接著劑的薄片等，可使用對底層填材之濕潤性小的材料。然後，晶片層積體11全體是以既定的溫度，例如：150℃左右進行熱處理使底層填材硬化，形成填充著如第8b圖所示的底層填材13的晶片層積體11。在本實施形態中，由於在塗佈用薄片37使用對底層填材13之濕潤性小的材料製成的薄片，在底層填材硬化時，底層填材13難以附著至塗佈用薄片37。
其次，如第9a圖所示，準備配線基板12。在配線基板12，使用兩面形成圖未表示的配線的絕緣基材12a(例如玻璃環氧基板)。在絕緣基材12a之一方的面，形成：複數個連接銲墊15；和設在連接銲墊15的表面，且與第3半導體晶片10c連接的焊線凸塊18。在絕緣基材12a之另一方的面，與成為外部端子的焊球17連接的複數個焊盤16是以既定的間隔形成例如：格子狀。複數個連接銲墊15和複數個焊盤16，是以貫通絕緣基材12a的導電材電性連接。絕緣基材12a的兩面的各配線，除了連接銲墊15與焊盤16，皆利用抗焊膜等的絕緣膜12b覆蓋。而且，配線基板12，是利用切割線39分割成為半導體裝置1的區域。
在配線基板12之一方的面，以覆蓋連接銲墊 15及焊線凸塊18的方式，塗佈硬化前的接著構件19，例如：NCP(非導電性絕緣膠)。在已塗佈的接著構件19硬化之前，如第9b圖所示，以配線基板12之一方的面與晶片層積體11的第3半導體晶片10c之一方的面為相對向的方式，使晶片層積體11層積在配線基板12。此時，連接著：配線基板12的焊線凸塊18；和晶片層積體11的第3半導體晶片10c的表面凸塊電極22。像這樣，使晶片層積體11搭載在配線基板12之一方的面，使晶片層積體11的第1半導體晶片10a，配置在離配線基板12最遠的位置。
在配線基板12搭載晶片層積體11之後，配線基板12，為了以密封樹脂14覆蓋晶片層積體11，因此安裝在由圖未表示的移轉成型裝置的上模與下模製成的模具。在模具的上模形成將複數個半導體晶片10一併覆蓋的圖未表示的模槽，在該模槽內收容晶片層積體11。然後，將已加熱溶融的密封樹脂14注入到模槽內，在模槽內晶片層積體11被密封樹脂14覆蓋。密封樹脂14，使用例如：環氧樹脂等的熱硬化性樹脂。
接著，在將模槽內以密封樹脂14填充的狀態下，以既定的溫度(例如180℃左右)使密封樹脂14硬化。如此一來，如第9c圖所示，形成覆蓋搭載在配線基板12之一方的面的晶片層積體11的密封樹脂14。進而，以既定的溫度烘烤密封樹脂14，使密封樹脂14硬化。在本實施形態，密封樹脂14是在藉由底層填材13及 接著構件19填充各半導體晶片10彼此之間的間隙26之後形成，因此能抑制起因於存在在各半導體晶片10彼此之間的間隙26的空氣所產生的氣泡。
在密封樹脂14形成在配線基板12之一方的面之後，如第9d圖所示，於形成在配線基板12之另一方的面的焊盤16，連接著成為半導體裝置1之外部端子的導電性的金屬球，例如：焊球17。複數個焊球17，可以藉由具備形成與配線基板12的各焊盤16之位置一致的複數個吸附孔之圖未表示的植球工具吸附保持，且一併搭載在各焊盤16上。接著，將配線基板12全體進行回焊，各焊盤16與各焊球17就會連接。一旦焊球17連接到焊盤16，如第9e圖所示，配線基板12會沿著既定的切割線39而切斷分離，以形成複數個CoC型的半導體裝置1。
雖是針對本實施形態所用的晶片層積體11，為由記憶體晶片與介面晶片構成的情形做說明，但也可為適用邏輯晶片等之其他半導體晶片或矽中介層的構成。
如以上說明，構成晶片層積體11的半導體晶片10為具有錐狀的凹部23，藉此在半導體晶片10彼此的層積時，收容在凹部23的表面凸塊電極22，會沿著凹部23的傾斜於凹部23的中心滑動。因此，表面凸塊電極22變得很容易在凹部23的中心連接，半導體晶片10的面方向的半導體晶片10彼此的位置偏移變得難以發生。
而且，焊料層24設在凹部內，形成焊料層24覆蓋表面凸塊電極22的表面全體，表面凸塊電極22與凹 部23就會連接，因此半導體晶片10彼此的連接強度提升。
進而，與將自配線基板12之一方的面突出的表面凸塊電極22彼此連接的專利文獻1的構成相比，本實施形態的構成，為表面凸塊電極22收容在凹部23內的構成，因此可縮小半導體晶片10彼此的間隙26。藉此，半導體裝置1薄型化。
第10圖是表示第1實施形態的變形例的第2半導體晶片10b與第1半導體晶片10a連接之際的表面凸塊電極22的周圍的構成之放大剖面圖。
設在第2半導體晶片10b之另一方的面的凹部23，是構成可完全收容第1半導體晶片10a的表面凸塊電極22的大小。具體而言，凹部23的深度，是構成變得比自表面凸塊電極22的半導體晶片10起的突出高度還大。此種凹部23的構成，並不限於形成在第2半導體晶片10b之另一方的面的凹部23，也適用於形成在第3半導體晶片10c之另一方的面的凹部23。
如以上，凹部23，是構成可將所收容的表面凸塊電極22完全收容，層積成半導體晶片10彼此密著，因此半導體晶片10彼此之間的間隙26變無。藉此，半導體裝置1全體更薄型化，並且不必在半導體晶片彼此之間填充底層填材13，半導體裝置1的製造成本受到抑制。
(第2實施形態)
第11圖是表示本發明之第2實施形態的第2半導體晶片10b的表面凸塊電極22的周圍的構成之放大剖面圖。
本實施形態的第2半導體晶片10b，具有：由矽基板21之一方的面向著另一方的面貫通矽基板21的貫通孔43。該貫通孔43，具有：從矽基板21之另一方的面延伸至矽基板21的內部的第1開口部40；和設在矽基板21之一方的面與第1開口部40之間的第2開口部41。
設在矽基板21之另一方的面的第1開口部40，是形成開口面積由矽基板21之另一方的面側向著一方的面側以第1縮小率變小的錐狀。而且，第1開口部40，是在矽基板21之另一方的面，在矽基板21的中央區域形成成為平行於矽基板21的一邊及矽基板21之一方的面的表面凸塊電極22之列的列。在該第1開口部40，設有例如：由Sn/Ag焊料製成的導電性的焊料層24。
設在矽基板21之一方的面與第1開口部40之間的第2開口部41，是形成由矽基板21之另一方的面側向著一方的面側，開口面積以第2縮小率變小的錐狀。在該第2開口部41，收容著例如：由Cu製成的導電性的導體層25。此時，具有第2開口部41的第2縮小率，比具有第1開口部40的第1縮小率還小。
而且，其他的半導體裝置1的構成及製造方法，與第1實施形態相同，省略之。
在本實施形態中，也可得到與第1實施形態 同樣的效果。
以上，雖是針對本發明之半導體裝置的具體構成根據各實施形態做說明，但本發明並不限於前述的實施形態，在不脫離本發明之主旨的範圍，當然可對前述的實施形態做各種的變更。例如：在前述的各實施形態中，雖是針對在表面凸塊電極為成列配置在中央區域的半導體晶片做說明，但本發明也適用於表面凸塊電極為任意配置的半導體晶片。

Claims (5)

  1. 一種半導體晶片，其包括：半導體基板；設在前述半導體基板之一方的面的複數個凸塊電極；設在前述半導體基板之另一方的面的複數個凹部；和配置在前述凹部內的焊料層，其中前述凹部係被形成以具有開口面積，前述開口面積由前述半導體基板之前述另一方的面朝向著前述一方的面變小，其中前述焊料層係經配置以在前述焊料層具有流動性時接觸另一個半導體晶片的凸塊電極。
  2. 如申請專利範圍第1項所記載的半導體晶片，其包括：連通部，其係形成在前述半導體基板中並且是從前述凹部貫通到前述半導體基板之前述一方的面；和導體層，其係配置在前述連通部內，其中前述凸塊電極係隔著前述導體層而與前述焊料層電性連接。
  3. 如申請專利範圍第1項所記載的半導體晶片，其中，前述凹部係形成為錐狀。
  4. 如申請專利範圍第1項所記載的半導體晶片，其中，前述凸塊電極係以銅製成。
  5. 如申請專利範圍第4項所記載的半導體晶片，其中，以銅製成的前述凸塊電極係形成為圓柱形狀。
TW103109664A 2013-03-14 2014-03-14 半導體晶片及具有半導體晶片之半導體裝置 TWI621241B (zh)

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