CN105428341A - 半导体装置以及半导体装置的制造方法 - Google Patents

半导体装置以及半导体装置的制造方法 Download PDF

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Publication number
CN105428341A
CN105428341A CN201510591584.9A CN201510591584A CN105428341A CN 105428341 A CN105428341 A CN 105428341A CN 201510591584 A CN201510591584 A CN 201510591584A CN 105428341 A CN105428341 A CN 105428341A
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semiconductor chip
chip
layer
sealing resin
semiconductor device
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佐藤隆夫
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Toshiba Corp
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Toshiba Corp
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Abstract

本发明涉及一种半导体装置以及半导体装置的制造方法。本发明的实施方式抑制半导体装置的可靠性降低。实施方式的半导体装置具备：第1半导体芯片；第2半导体芯片，积层在第1半导体芯片上，具有从一面向另一面贯通半导体基板的贯通电极，且以将另一面朝向第1半导体芯片的方式积层；第1凸块，向一面突出设置，且具有露出面；密封树脂，以将露出面露出的方式密封第1半导体芯片与第2半导体芯片、第1凸块；以及第2凸块，设置在露出面上。

Description

半导体装置以及半导体装置的制造方法
[相关申请案]
本申请案享受以日本专利申请2014-188173号(申请日：2014年9月16日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
实施方式的发明涉及一种半导体装置以及半导体装置的制造方法。
背景技术
近年来，随着通信技术及信息处理技术不断发展，而要求半导体装置小型化及高速化。为了应对这种要求，正在推进开发以下半导体封装体：在半导体装置中，通过使多个半导体芯片积层的三维封装，以缩短零件间的配线长度来应对动作频率的增大，且提高封装面积效率。
例如，提出了如下三维封装结构：在NAND(NotAnd，与非)型闪速存储器等半导体装置中，从小型化及高速化的观点出发，将存储器控制器与存储器芯片积层在同一配线基板上。作为三维封装结构，例如有TSV(ThroughSiliconVia，硅穿孔)方式的积层结构。
在三维封装结构的半导体装置的制造中，通过在引线框架等支撑基板上积层多个半导体芯片而形成芯片积层体，在芯片积层体上形成焊球等凸块层，并利用底部填充树脂将半导体芯片之间密封。之后，使芯片积层体翻转，隔着凸块层将芯片积层体与配线基板接合。进而，通过填充密封树脂而密封芯片积层体，在配线基板上形成外部连接端子之后，进行切割而对应于芯片积层体将配线基板单片化。
在三维封装结构的半导体装置中，为实现小型化、薄型化，半导体芯片非常薄，从而易变形。因此，在芯片积层体中，半导体芯片易产生翘曲。如果半导体芯片产生翘曲，则凸块层的高度变得不均，从而易产生芯片积层体与配线基板的连接不良。这样一来，三维封装结构的半导体装置存在因半导体芯片翘曲而可靠性降低等问题。
发明内容
实施方式提供一种能够抑制可靠性降低的半导体装置及其制造方法。
实施方式的半导体装置具备：第1半导体芯片；第2半导体芯片，积层在第1半导体芯片上，具有从一面向另一面贯通半导体基板的贯通电极，且以将另一面朝向第1半导体芯片的方式积层；第1凸块，向一面突出设置，具有露出面；密封树脂，以将露出面露出的方式密封第1半导体芯片与第2半导体芯片、第1凸块；以及第2凸块，设置在露出面上。
附图说明
图1(A)及(B)是表示半导体装置的结构例的图。
图2是表示半导体装置的制造方法例的流程图。
图3是用以说明半导体装置的制造方法例的图。
图4是用以说明半导体装置的制造方法例的图。
图5是用以说明半导体装置的制造方法例的图。
图6是用以说明半导体装置的制造方法例的图。
图7是用以说明半导体装置的制造方法例的图。
图8是用以说明半导体装置的制造方法例的图。
图9(A)及(B)是用以说明半导体装置的制造方法例的图。
图10(A)及(B)是表示半导体装置的结构例的图。
图11是表示半导体装置的制造方法例的流程图。
图12是用以说明半导体装置的制造方法例的图。
图13是用以说明半导体装置的制造方法例的图。
图14是用以说明半导体装置的制造方法例的图。
图15是用以说明半导体装置的制造方法例的图。
图16是用以说明半导体装置的制造方法例的图。
图17是用以说明半导体装置的制造方法例的图。
具体实施方式
以下，参照附图对实施方式进行说明。另外，附图为示意图，例如厚度与平面尺寸的关系、各层厚度的比率等有时与实物不同。而且，在各实施方式中，对实质上相同的构成要素标注相同的符号并省略说明。
(第1实施方式)
图1是表示半导体装置的结构例的图。图1(A)为俯视图，图1(B)为图1(A)中的线段A1-B1间的剖视图。图1所示的半导体装置为扇入(fanin)型半导体装置，具备支撑基板1、粘接剂层2、具有经积层的多个半导体芯片的芯片积层体3、密封树脂层4、凸块层5、密封树脂层6以及凸块层7。另外，图1中，作为一例，以支撑基板1位于下侧、凸块层7位于上侧的方式图示，但半导体装置的上下方向也可以颠倒。而且，凸块层5及凸块层7的数量并不限定于图1所示的数量。
支撑基板1是供芯片积层体3搭载的基板。支撑基板1由例如金属材料、硅等半导体材料、树脂材料、陶瓷材料等构成。作为支撑基板1，也可以使用例如引线框架。作为引线框架，可以使用例如含有42合金等铁及镍的合金材料的引线框架。另外，也可以未必设置支撑基板1。
粘接剂层2设置在支撑基板1上。粘接剂层2具有将支撑基板1与芯片积层体3粘接的功能。作为粘接剂层2，可以使用例如聚酰亚胺等树脂膜。
芯片积层体3隔着粘接剂层2设置在支撑基板1上。芯片积层体3具有积层在支撑基板1上的半导体芯片31a、半导体芯片31b、半导体芯片31c以及半导体芯片31d。另外，半导体芯片的种类并不限定于半导体芯片31a至半导体芯片31d。
半导体芯片31a设置在粘接剂层2上。例如，半导体芯片31a的上表面具有连接垫。另外，也可以在半导体芯片31a中设置从半导体芯片31a的一面向另一面贯通的TSV等的贯通电极。
例如多个半导体芯片31b积层设置在半导体芯片31a上。半导体芯片31b的积层数并不限定于图1所示的积层数。最下层的半导体芯片31b隔着凸块32及粘接层33积层在半导体芯片31a上，且经由凸块32电连接于半导体芯片31a。而且，多个半导体芯片31b隔着凸块32及粘接层33相互积层。
粘接层33具有作为用以维持半导体芯片31a至半导体芯片31c的间隔的间隔件的功能。作为粘接层33，可以使用例如热固性树脂等。另外，也可以使用NCF(Non-ConductiveFilm，非导电膜)等绝缘性粘接材料代替粘接层33，将半导体芯片31a至半导体芯片31c之间密封。NCF等绝缘性粘接材料具有密封与粘接两个功能，因此无需底部填充树脂。
多个半导体芯片31b具有从半导体芯片31b的一面向另一面贯通的TSV等的贯通电极311，且经由贯通电极311及凸块32而相互电连接。例如，半导体芯片31b的上表面(一面)及下表面(另一面)具有连接垫。在半导体芯片31a的一面与半导体芯片31b的另一面的连接垫之间、以及多个半导体芯片31b的连接垫之间设置凸块32。作为贯通电极311，可以使用例如镍、铜、银、金等单质或合金。这样一来，通过使用TSV方式的积层结构的芯片积层体3，能够减小芯片面积，且能够增加连接端子数，因此能够抑制连接不良等。
半导体芯片31c具有从半导体芯片31c的一面向另一面贯通的TSV等的贯通电极311。半导体芯片31c的另一面隔着凸块32及粘接层33积层在半导体芯片31b上，且经由凸块32及贯通电极311而电连接于半导体芯片31b。半导体芯片31c的上表面(一面)具有配线层34。配线层34是用于重新配置半导体芯片31a的配线的配线层(也称为再配线层)。配线层34具有至少包含连接配线34a的多个连接配线、及绝缘层34b。连接配线34a电连接于半导体芯片31c的贯通电极311。在配线层34上设置电极垫35。
作为半导体芯片31a至半导体芯片31c，可以使用例如存储器芯片等。作为存储器芯片，可以使用例如NAND型闪速存储器等存储元件。另外，也可以在存储器芯片中设置解码器等电路。
半导体芯片31d积层在配线层34上，且经由连接配线34a电连接于半导体芯片31c。作为连接配线34a及电极垫35，可以使用例如铜、钛、氮化钛、铬、镍、金或钯等的单层或积层。
作为半导体芯片31d，可以使用例如接口芯片或控制器芯片。例如，在半导体芯片31a至半导体芯片31c为存储器芯片的情况下，可以使用控制器芯片作为半导体芯片31d，利用控制器芯片来控制对存储器芯片的写入及读出。另外，半导体芯片31d优选为小于半导体芯片31a至半导体芯片31c。
密封树脂层4至少密封半导体芯片31a至半导体芯片31d之间。此时，也能以覆盖半导体芯片31a至半导体芯片31d的侧面的方式设置密封树脂层4。作为密封树脂层4，可以使用例如底部填充树脂等。
凸块层5以突出在芯片积层体3的电极垫35上的方式设置，且经由例如配线层34的除连接配线34a以外的连接配线而电连接于半导体芯片31c。
凸块层5可以使用例如锡-银系、锡-银-铜系的无铅焊料。作为凸块层5，也可以使用例如铜、钛、氮化钛、铬、镍、金或钯等的单层或积层。图1中，对凸块层5为焊球的情况进行说明。而且，也可以将电极垫35视为凸块层5的一部分。
密封树脂层6将芯片积层体3密封。另外，也能以覆盖支撑基板1的侧面的方式设置密封树脂层6。而且，通过使支撑基板1的芯片积层体3形成面的相反面露出，能够提高散热性。并不限定于此，也可以为所述相反面被密封树脂层6覆盖。
密封树脂层6至少包含SiO2等无机填充材料。例如，可以使用无机填充材料与环氧树脂等有机树脂的混合物构成密封树脂层6。无机填充材料的含量优选为整体的80％以上且95％以下。这种密封树脂层6因与支撑基板1的密接性高而为宜。
于在芯片积层体上形成凸块层，且由密封树脂层密封芯片积层体的情况下，在芯片积层体中半导体芯片易产生翘曲。半导体芯片不仅具有形成半导体元件等时产生的残留应力等，在变薄时其刚性也会变低，因此例如在芯片积层体上具有凸块层的情况下，像支撑基板1侧凸起那样容易在凹向产生翘曲。在芯片积层体中，越积层半导体芯片，积层于下侧半导体芯片的半导体芯片的应力不断被相加，而翘曲越明显。在已产生翘曲的情况下，凸块层从中心朝向周缘变高，多个凸块层的高度产生不均。
对此，在图1所示的半导体装置中，凸块层5以埋入密封树脂层6的方式设置在芯片积层体3上，且沿着密封树脂层6的上表面具有从密封树脂层6露出的平坦面(露出面)51。平坦面51具有作为凸块层7的焊盘(land)的功能。通过设置平坦面51，可以使凸块层7的形成面的高度与密封树脂层6的上表面的高度一致。此时，多个凸块层5的平坦面51的面积可以是越接近周缘则越大。
凸块层7设置在凸块层5的平坦面51上。凸块层7具有作为外部连接端子的功能。另外，也可以将凸块层5与凸块层7合并而视为凸块。作为凸块层7，可以使用例如锡-银系、锡-银-铜系的无铅焊料。作为凸块层7，也可以使用例如铜、钛、氮化钛、铬、镍、金或钯等的单层或积层。图1中，对凸块层7为焊球的情况进行说明，但并不限定于此。
如上所述，本实施方式的半导体装置具备如下结构：具有埋入密封树脂层且沿着密封树脂层的上表面具有平坦面的第1凸块层，在第1凸块层的平坦面上具有第2凸块层。由此，即便于在芯片积层体中半导体芯片产生翘曲的情况下，也能够降低凸块的高度不均。由此，例如将半导体装置搭载在其它基板等时的接合不良等得以抑制，能够抑制可靠性降低。
而且，本实施方式的半导体装置具有能够将芯片积层体上的凸块层用作外部连接端子的扇入型结构。由此，也可以未必将半导体装置另外搭载于配线基板。因此，可以缩小半导体装置的尺寸。
接下来，参照图2对图1所示的半导体装置的制造方法例进行说明。图2是表示半导体装置的制造方法例的流程图。半导体装置的制造方法例至少具备：积层步骤(S1-1)，通过积层多个半导体芯片而形成芯片积层体；第1密封步骤(S1-2)，形成密封多个半导体芯片之间的第1密封树脂层；第1凸块层形成步骤(S1-3)，在芯片积层体上形成第1凸块层；第2密封步骤(S1-4)，形成覆盖第1凸块层及芯片积层体的第2密封树脂层；研磨步骤(去除步骤)(S1-5)，沿着半导体芯片的积层方向研磨去除第1凸块层的一部分及密封树脂层的一部分，直至第1凸块层从密封树脂层的上表面露出；第2凸块层形成步骤(S1-6)，在第1凸块层的研磨面上形成第2凸块层；以及分离步骤(S1-7)，对应于芯片积层体将支撑基板分离。各步骤可以固定于例如平台、基板或胶带等而进行。另外，各步骤的顺序并不限定于图2所示的顺序。而且，也可以利用同一步骤形成多个半导体装置。
进而，参照图3至图9对所述步骤进行说明。图3至图9是用以说明半导体装置的制造方法例的图。此处，作为一例，对支撑基板1使用引线框架的情况进行说明。
在积层步骤(S1-1)中，如图3所示，通过将半导体芯片31a至半导体芯片31d积层而形成芯片积层体3。例如，可以使用贴片机等将半导体芯片31a至半导体芯片31d积层。
在积层步骤(S1-1)中，首先通过在半导体芯片31a上预先形成粘接剂层2，隔着粘接剂层2在支撑基板1上积层半导体芯片31a，并进行加热处理使粘接剂层2硬化，而将半导体芯片31a粘接。此时，在利用同一步骤制造多个半导体装置的情况下，也可以使用集合基板作为支撑基板1。
接着，将第1面具有凸块32及粘接层33且具有贯通电极311的多个半导体芯片31b隔着凸块32及粘接层33多层积层于半导体芯片31a上。此时，通过进行例如热处理而经由凸块32将半导体芯片31a的连接垫与半导体芯片31b的连接垫接合。凸块32及粘接层33是通过例如在要积层的两个半导体芯片的至少一个上设置构成凸块32的凸块层及构成粘接层33的粘接剂的涂布层而形成。
接着，将第1面具有配线层34及电极垫35、第2面具有凸块32及粘接层33的半导体芯片31c隔着凸块32及粘接层33积层在半导体芯片31b上。此时，通过进行例如热处理而经由贯通电极311及凸块32将半导体芯片31a至半导体芯片31c接合。
接着，在配线层34上积层半导体芯片31d。例如，通过热压接或还原环境下的回焊等将半导体芯片31d经由例如凸块电连接于连接配线34a。可以利用所述步骤形成芯片积层体3。
在第1密封步骤(S1-2)中，如图4所示，在半导体芯片31a至半导体芯片31d之间以及半导体芯片31a至半导体芯片31d的侧面形成密封树脂层4。例如，可以通过在半导体芯片31a至半导体芯片31d之间使用分配器等填充底部填充树脂，而形成密封树脂层4。另外，半导体芯片31a至半导体芯片31c之间的密封步骤、与半导体芯片31c与半导体芯片31d之间的密封步骤也可以为不同步骤。而且，也能以包围芯片积层体3的方式在支撑基板1上形成沟槽。由此，可以抑制例如利用同一步骤制造多个半导体装置的情况下底部填充树脂流出到相邻的芯片积层体3的形成区域。
在第1凸块层形成步骤(S1-3)中，如图5所示，在芯片积层体3上形成凸块层5。例如，可以通过使用植球机等在电极垫35上设置焊球而形成凸块层5。
在第2密封步骤(S1-4)中，如图6所示，形成覆盖芯片积层体3及凸块层5的密封树脂层6。例如，可以通过使用转注成形法、压缩成形法、射出成形法等成形法以覆盖芯片积层体3及凸块层5的方式填充能够应用于密封树脂层6的材料的密封树脂并使其硬化，而形成密封树脂层6。在利用同一步骤制造多个半导体装置的情况下，优选为针对每个芯片积层体3形成密封树脂层6以形成单独的模腔。
在研磨步骤(S1-5)中，如图7所示，沿着半导体芯片的积层方向研磨凸块层5的一部分及密封树脂层6的一部分，直至凸块层5从密封树脂层6的上表面露出。由此，沿着密封树脂层6的上表面在凸块层5上形成平坦面51。例如，可以通过使用磨石等研磨凸块层5的一部分及密封树脂层6的一部分，而形成平坦面51。并不限定于此，也可以通过进行喷击处理或CMP(ChemicalMechanicalPolishing，化学机械抛光)处理，而研磨凸块层5的一部分及密封树脂层6的一部分。
在第2凸块层形成步骤(S1-6)中，如图8所示，在凸块层5的研磨面也就是平坦面51上形成凸块层7。例如，在凸块层5的平坦面51上涂布助焊剂之后，使用植球机等在凸块层5的平坦面51上搭载焊球，放入回焊炉使焊球熔融，而使该焊球与电极垫35接合。之后，可以通过利用溶剂或纯水清洗去除助焊剂而形成凸块层7。
在分离步骤(S1-7)中，如图9所示，对应于芯片积层体3将包含芯片搭载部的支撑基板1的一部分分离。图9(A)是设置着芯片积层体3的引线框架也就是支撑基板1的分离后的俯视图，图9(B)是与图3至图8所示的截面方向不同而沿着延伸部的方向即图9(A)的线段X-Y上的剖视图。
图9所示的支撑基板1具有芯片搭载部11、及支撑芯片搭载部11的延伸部12。在设于支撑基板1的芯片搭载部11上形成芯片积层体3。在分离步骤(S1-7)中，可以通过使用例如切割刀片切断延伸部12而对应于芯片积层体3将包含芯片搭载部11的支撑基板1的一部分分离。通过以上操作而制造半导体装置。另外，在形成多个半导体装置的情况下，针对每个芯片积层体3将包含芯片搭载部11的支撑基板1的一部分分离。在使用集合基板制造半导体装置的情况下，通过将集合基板的一部分分离，而经分离的集合基板的一部分成为支撑基板1。
如上所述，在本实施方式的半导体装置的制造方法中，在芯片积层体上形成第1凸块层之后，形成覆盖第1凸块层及芯片积层体的密封树脂层。之后，沿着半导体芯片的积层方向研磨第1凸块层的一部分及密封树脂层的一部分。由此，可以沿着密封树脂层的上表面在第1凸块层上形成平坦面。进而，通过在第1凸块层的平坦面上形成第2凸块层，即便在芯片积层体中半导体芯片产生翘曲的情况下，也能够抑制凸块的高度不均。
(第2实施方式)
在本实施方式中，对第1凸块层的结构与第1实施方式的半导体装置不同的半导体装置进行说明。另外，对于与第1实施方式的半导体装置相同的部分，可以适当引用第1实施方式的说明。
图10是表示半导体装置的结构例的图。图10(A)为俯视图，图10(B)为图10(A)中的线段A2-B2间的剖视图。图10所示的半导体装置与图1所示的半导体装置同样地为扇入型半导体装置，具备支撑基板1、粘接剂层2、具有经积层的多个半导体芯片的芯片积层体3、密封半导体芯片间的密封树脂层4、设置在芯片积层体3上的凸块层5、密封芯片积层体3的密封树脂层6、以及设置在凸块层5上的凸块层7。另外，图10中，作为一例，以支撑基板1位于下侧、凸块层7位于上侧的方式图示，但半导体装置的上下方向也可以颠倒。而且，凸块层5及凸块层7的数量并不限定于图10所示的数量。支撑基板1、粘接剂层2、芯片积层体3、密封树脂层4、密封树脂层6、凸块层7适当引用第1实施方式的说明，此处对凸块层5进行说明。
凸块层5以埋入密封树脂层6的方式设置，且沿着密封树脂层6的上表面具有从密封树脂层6露出的平坦面51。凸块层5设置在芯片积层体3的电极垫35上，经由例如配线层34的除连接配线34a以外的配线而电连接于半导体芯片31c。
凸块层5可以使用例如锡-银系、锡-银-铜系的无铅焊料。作为凸块层5，也可以使用例如铜、钛、氮化钛、铬、镍、金或钯等的单层或积层。图10中，对凸块层5为埋入电极的情况进行说明。另外，也可以将电极垫35视为凸块层5的一部分。
本实施方式的半导体装置与第1实施方式的半导体装置相比至少在由埋入电极构成第1凸块层的方面不同。通过由埋入电极构成第1凸块层，能够使例如多个第1凸块层的直径相同，因此能够抑制该第1凸块层与第2凸块层的接合不良。由此，能够抑制可靠性降低。
而且，本实施方式的半导体装置与第1实施方式同样地具有能够将芯片积层体上的第2凸块层用作外部连接端子的扇入型结构。由此，也可以未必将半导体装置另外搭载于配线基板。因此，可以缩小半导体装置的尺寸。
接下来，参照图11对图10所示的半导体装置的制造方法例进行说明。图11是表示半导体装置的制造方法例的流程图。半导体装置的制造方法例至少具备：积层步骤(S2-1)，通过积层多个半导体芯片而形成芯片积层体；第1密封步骤(S2-2)，形成密封多个半导体芯片之间的第1密封树脂层；第2密封步骤(S2-3)，形成覆盖芯片积层体的第2密封树脂层；开口部形成步骤(S2-4)，以芯片积层体的一部分露出的方式在第2密封树脂层形成开口部；第1凸块层形成步骤(S2-5)，通过以填埋开口部的方式设置导电层而形成第1凸块层；研磨步骤(S2-6)，沿着半导体芯片的积层方向研磨第1凸块层的一部分及密封树脂层的一部分，直至第1凸块层从密封树脂层的上表面露出；第2凸块层形成步骤(S2-7)，在第1凸块层的研磨面上形成第2凸块层；以及分离步骤(S2-8)，对应于芯片积层体将支撑基板分离。另外，各步骤的顺序并不限定于图11所示的顺序。而且，也可以利用同一步骤形成多个半导体装置。
进而，参照图12至图17对所述步骤进行说明。图12至图17是用以说明半导体装置的制造方法例的图。此处，作为一例，对支撑基板1使用引线框架的情况进行说明。
如图12所示，在积层步骤(S2-1)中，与积层步骤(S1-1)同样地形成芯片积层体3，在第1密封步骤(S2-2)中，与第1密封步骤(S1-2)同样地形成密封树脂层4。关于其它说明，可以适当引用积层步骤(S1-1)及第1密封步骤(S1-2)的说明，因此省略说明。
在第2密封步骤(S2-3)中，如图13所示，形成覆盖芯片积层体3的密封树脂层6。关于其它说明，可以适当引用第2密封步骤(S1-4)的说明，因此省略说明。
在开口部形成步骤(S2-4)中，如图14所示，以芯片积层体3的上表面的一部分(此处为电极垫35的至少一部分)露出的方式在密封树脂层6形成开口部6a。例如，可以对密封树脂层6照射激光而形成开口部6a。并不限定于此，也可以使用例如光刻技术形成开口部6a。
在第1凸块层形成步骤(S2-5)中，如图15所示，在芯片积层体3上形成凸块层5。例如，可以通过使用能够应用于凸块层5的金属导电膏或焊料材料等以填埋开口部6a的方式设置导电层而形成凸块层5。另外，也可以以覆盖密封树脂层6上的方式形成导电层。而且，只要能够以填埋开口部6a的方式形成凸块层5，则也可以使用其它方法形成凸块层5。
在研磨步骤(S2-6)中，如图16所示，沿着半导体芯片的积层方向研磨凸块层5的一部分及密封树脂层6的一部分。由此，沿着密封树脂层6的上表面在凸块层5形成平坦面51。关于其它说明，可以适当引用研磨步骤(S1-5)的说明，因此省略说明。
在第2凸块层形成步骤(S2-7)中，如图17所示，在凸块层5的研磨面也就是平坦面51上形成凸块层7。关于其它说明，可以适当引用第2凸块层形成步骤(S1-6)的说明，因此省略说明。
在分离步骤(S2-8)中，与分离步骤(S1-7)同样地对应于芯片积层体3将包含芯片搭载部的支撑基板1的一部分分离。关于其它说明，可以适当引用分离步骤(S1-7)的说明，因此省略说明。通过以上操作而制造半导体装置。
如上所述，在本实施方式的半导体装置的制造方法中，在形成覆盖芯片积层体的密封树脂层之后，以芯片积层体的一部分露出的方式在密封树脂层形成开口部。之后，通过以填埋开口部的方式设置导电层而形成第1凸块层，之后，沿着半导体芯片的积层方向研磨第1凸块层的一部分及密封树脂层的一部分。由此，可以形成直径偏差少的第1凸块层。而且，可以沿着密封树脂层的上表面在第1凸块层形成平坦面。进而，通过在第1凸块层的平坦面形成第2凸块层，即便在芯片积层体中半导体芯片产生翘曲的情况下，也能够抑制凸块的高度不均。
另外，各实施方式是作为示例而提出的，并非意欲限定发明的范围。这些新颖的实施方式能以其它各种形态实施，在不脱离发明主旨的范围内能够进行各种省略、置换、变更。这些实施方式或其变化包含在发明的范围或主旨中，且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1支撑基板
11芯片搭载部
12延伸部
2粘接剂层
3芯片积层体
31a半导体芯片
31b半导体芯片
31c半导体芯片
31d半导体芯片
32凸块
33粘接层
34配线层
34a连接配线
34b绝缘层
35电极垫
311贯通电极
4密封树脂层
5凸块层
51平坦面
6密封树脂层
6a开口部
7凸块层

Claims (5)

1.一种半导体装置，其特征在于具备：
第1半导体芯片；
第2半导体芯片，积层在所述第1半导体芯片上，具有从一面向另一面贯通半导体基板的贯通电极，且以将所述另一面朝向所述第1半导体芯片的方式积层；
第1凸块，向所述一面突出设置，具有露出面；
密封树脂，以将所述露出面露出的方式密封所述第1半导体芯片与所述第2半导体芯片、所述第1凸块；以及
第2凸块，设置在所述露出面上。
2.根据权利要求1所述的半导体装置，其特征在于还具备支撑基板，
所述第1半导体芯片设置在所述支撑基板上。
3.一种半导体装置的制造方法，其特征在于
将具有从一面向另一面贯通半导体基板的贯通电极的第2半导体芯片，以所述另一面朝向所述第1半导体芯片的方式积层在第1半导体芯片上，
在所述第2半导体芯片的一面上形成第1凸块，
形成覆盖所述第1凸块及所述第1半导体芯片、第2半导体芯片的密封树脂层，
沿着所述第1半导体芯片与第2半导体芯片的积层方向去除所述第1凸块的一部分及所述密封树脂层的一部分，直至所述第1凸块从所述密封树脂层的上表面露出，并且
在所述第1凸块的露出面上形成第2凸块。
4.一种半导体装置的制造方法，其特征在于
将具有从一面向另一面贯通半导体基板的贯通电极的第2半导体芯片，以所述另一面朝向所述第1半导体芯片的方式积层在第1半导体芯片上，
形成覆盖所述第1半导体芯片及第2半导体芯片的密封树脂层，
以所述第2半导体芯片的一面的一部分露出的方式在所述密封树脂层形成开口部，
在所述开口部内形成第1凸块，
沿着所述半导体芯片的积层方向去除所述第1凸块的一部分及所述密封树脂层的一部分，并且
在所述第1凸块层的露出面上形成第2凸块层。
5.根据权利要求3或4所述的半导体装置的制造方法，其特征在于其中
在支撑基板上设置所述第1半导体芯片之后积层所述第2半导体芯片，并且
在形成所述第2凸块之后将所述支撑基板的一部分分离。
CN201510591584.9A 2014-09-16 2015-09-16 半导体装置以及半导体装置的制造方法 Pending CN105428341A (zh)

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