CN107204318B - 半导体装置及半导体装置的制造方法 - Google Patents
半导体装置及半导体装置的制造方法 Download PDFInfo
- Publication number
- CN107204318B CN107204318B CN201710134843.4A CN201710134843A CN107204318B CN 107204318 B CN107204318 B CN 107204318B CN 201710134843 A CN201710134843 A CN 201710134843A CN 107204318 B CN107204318 B CN 107204318B
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- CN
- China
- Prior art keywords
- electric conductivity
- weld pad
- area
- conductivity weld
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
- H01L2224/0901—Structure
- H01L2224/0903—Bonding areas having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (5)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016-052937 | 2016-03-16 | ||
JP2016052937A JP6486855B2 (ja) | 2016-03-16 | 2016-03-16 | 半導体装置および半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107204318A CN107204318A (zh) | 2017-09-26 |
CN107204318B true CN107204318B (zh) | 2019-11-15 |
Family
ID=59904890
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710134843.4A Active CN107204318B (zh) | 2016-03-16 | 2017-03-08 | 半导体装置及半导体装置的制造方法 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP6486855B2 (zh) |
CN (1) | CN107204318B (zh) |
TW (1) | TWI658544B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6486855B2 (ja) * | 2016-03-16 | 2019-03-20 | 東芝メモリ株式会社 | 半導体装置および半導体装置の製造方法 |
CN110690129B (zh) * | 2019-09-24 | 2021-05-28 | 浙江集迈科微电子有限公司 | 一种具有防溢锡结构的三维异构堆叠方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003243818A (ja) * | 2002-02-15 | 2003-08-29 | Denso Corp | 半導体電子部品の実装方法 |
JP2006190902A (ja) * | 2005-01-07 | 2006-07-20 | Denso Corp | 半導体電子部品の実装方法及び半導体電子部品の配線基板 |
JP2007067129A (ja) * | 2005-08-31 | 2007-03-15 | Canon Inc | 半導体装置の実装構造 |
CN107204318A (zh) * | 2016-03-16 | 2017-09-26 | 东芝存储器株式会社 | 半导体装置及半导体装置的制造方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4096774B2 (ja) * | 2003-03-24 | 2008-06-04 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法 |
JP5154271B2 (ja) * | 2008-03-17 | 2013-02-27 | 日本特殊陶業株式会社 | はんだバンプを有する配線基板及びその製造方法 |
-
2016
- 2016-03-16 JP JP2016052937A patent/JP6486855B2/ja active Active
-
2017
- 2017-02-08 TW TW106104039A patent/TWI658544B/zh active
- 2017-03-08 CN CN201710134843.4A patent/CN107204318B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003243818A (ja) * | 2002-02-15 | 2003-08-29 | Denso Corp | 半導体電子部品の実装方法 |
JP2006190902A (ja) * | 2005-01-07 | 2006-07-20 | Denso Corp | 半導体電子部品の実装方法及び半導体電子部品の配線基板 |
JP2007067129A (ja) * | 2005-08-31 | 2007-03-15 | Canon Inc | 半導体装置の実装構造 |
CN107204318A (zh) * | 2016-03-16 | 2017-09-26 | 东芝存储器株式会社 | 半导体装置及半导体装置的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN107204318A (zh) | 2017-09-26 |
TWI658544B (zh) | 2019-05-01 |
JP2017168653A (ja) | 2017-09-21 |
JP6486855B2 (ja) | 2019-03-20 |
TW201810547A (zh) | 2018-03-16 |
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CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo Patentee after: Kaixia Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. Address after: Tokyo Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo Patentee before: Pangea Co.,Ltd. |
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TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20220126 Address after: Tokyo Patentee after: Pangea Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. |