JP5814859B2 - 半導体装置とその製造方法 - Google Patents
半導体装置とその製造方法 Download PDFInfo
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- JP5814859B2 JP5814859B2 JP2012119530A JP2012119530A JP5814859B2 JP 5814859 B2 JP5814859 B2 JP 5814859B2 JP 2012119530 A JP2012119530 A JP 2012119530A JP 2012119530 A JP2012119530 A JP 2012119530A JP 5814859 B2 JP5814859 B2 JP 5814859B2
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Description
第1の実施形態による半導体装置とその製造方法について、図面を参照して説明する。図1は第1の実施形態による半導体装置を示す図、図2、図3および図4は第1の実施形態による半導体装置の製造工程を示す図である。半導体装置1は第1の半導体チップ2と第2の半導体チップ3とを具備している。第1の半導体チップ2の上面(第1の表面)2aは第1の接続領域を有し、第1の接続領域内に第1のバンプ電極4が形成されている。
第2の実施形態による半導体装置について説明する。図9は第2の実施形態の半導体装置を示す図である。第1の実施形態と同一部分については、同一符号を付して一部説明を省略する場合がある。図9に示す半導体装置20は、第1の半導体チップ21と第2の半導体チップ22と第3の半導体チップ23とを積層した構造を有している。ここでは第1ないし第3の半導体チップ21、22、23を積層した半導体装置20について述べるが、半導体チップの積層数は4層以上であってもよい。第3の半導体チップ23の積層工程を繰り返すことで、必要数の半導体チップを積層した半導体装置を得ることができる。
第3の実施形態による半導体装置の構成と製造工程について、図15および図16を参照して説明する。第3の実施形態による半導体装置40は、第1および第2の実施形態におけるストッパ用突起7および接着用突起8に代えて、ストッパ兼接着用突起41を有している。第1および第2の実施形態と同一部分については、同一符号を付して一部説明を省略する場合がある
第4の実施形態による半導体装置の構成について、図20、図21、図22および図23を参照して説明する。第4の実施形態による半導体装置は、第1および第2の実施形態における接着用突起8、または第3の実施形態におけるストッパ兼接着用突起41に、アンダーフィル樹脂のはみ出し抑制機能を持たせたものである。なお、それら以外の構成については、第1ないし第3の実施形態と同一であるため、ここでは説明を省略する。
第5の実施形態による半導体装置の構成と製造工程について、図24、図25および図26を参照して説明する。第5の実施形態による半導体装置50は、ストッパ用突起7および接着用突起8の接触面、もしくはストッパ兼接着用突起41の接触面に設けられた有機絶縁膜(絶縁膜)51を備えている。それ以外の構成は、基本的には第1ないし第3の実施形態と同一である。第1ないし第3の実施形態と同一部分については、同一符号を付して一部説明を省略する場合がある。ここではストッパ兼接着用突起41を用いた半導体装置50について主として説明するが、ストッパ用突起7および接着用突起8を適用する場合も同様である。
Claims (4)
- 第1の接続領域と、前記第1の接続領域を除く第1の非接続領域とを備える第1の表面を有する第1の半導体チップと、
前記第1の接続領域と対向する第2の接続領域と、前記第2の接続領域を除く第2の非接続領域とを備える第2の表面と、第3の接続領域と、前記第3の接続領域を除く第3の非接続領域とを備え、前記第2の表面とは反対側の第3の表面とを有し、前記第1の半導体チップ上に積層された第2の半導体チップと、
前記第3の接続領域と対向する第4の接続領域と、前記第4の接続領域を除く第4の非接続領域とを備える第4の表面を有し、前記第2の半導体チップ上に積層された第3の半導体チップと、
前記第1の半導体チップと前記第2の半導体チップとを電気的に接続するように、前記第1の表面の前記第1の接続領域と前記第2の表面の前記第2の接続領域との間に設けられた第1のバンプ接続部と、
前記第1の表面の前記第1の非接続領域および前記第2の表面の前記第2の非接続領域の少なくとも一方の領域に局所的に設けられ、かつ前記第1の非接続領域および前記第2の非接続領域の他方の領域と非接着状態で接触する第1のストッパ用突起と、
前記第1の表面の前記第1の非接続領域と前記第2の表面の前記第2の非接続領域との間に局所的に設けられ、前記第1および第2の表面に接着された第1の接着用突起と、
前記第2の半導体チップと前記第3の半導体チップとを電気的に接続するように、前記第3の表面の前記第3の接続領域と前記第4の表面の前記第4の接続領域との間に設けられた第2のバンプ接続部と、
前記第3の表面の前記第3の非接続領域および前記第4の表面の前記第4の非接続領域の少なくとも一方の領域に局所的に設けられ、かつ前記第3の非接続領域および前記第4の非接続領域の他方の領域と非接着状態で接触する第2のストッパ用突起と、
前記第3の表面の前記第3の非接続領域と前記第4の表面の前記第4の非接続領域との間に局所的に設けられ、前記第3および第4の表面に接着された第2の接着用突起と、
前記第1の半導体チップの前記第1の表面と前記第2の半導体チップの前記第2の表面との間の隙間、および前記第2の半導体チップの前記第3の表面と前記第3の半導体チップの前記第4の表面との間の隙間に充填された樹脂とを具備し、
前記第2のバンプ接続部は、前記第2の半導体チップ内に設けられた貫通電極を介して、前記第1のバンプ接続部と電気的に接続されており、
前記第1の接着用突起は、前記第1の表面の前記第1の非接続領域および前記第2の表面の前記第2の非接続領域の少なくとも一方の領域に設けられ、前記第1の非接続領域および前記第2の非接続領域の少なくとも他方の領域には、絶縁膜が設けられており、
前記第2の接着用突起は、前記第3の表面の前記第3の非接続領域および前記第4の表面の前記第4の非接続領域の少なくとも一方の領域に設けられ、前記第3の非接続領域および前記第4の非接続領域の少なくとも他方の領域には、絶縁膜が設けられており、
前記第1のストッパ用突起は、前記第1のバンプ接続部より前記第1の表面または前記第2の表面の外周に近い位置に複数設けられており、
前記第2のストッパ用突起は、前記第2のバンプ接続部より前記第3の表面または前記第4の表面の外周に近い位置に複数設けられていることを特徴とする半導体装置。 - 第1の接続領域と、前記第1の接続領域を除く第1の非接続領域とを備える第1の表面を有する第1の半導体チップと、
前記第1の接続領域と対向する第2の接続領域と、前記第2の接続領域を除く第2の非接続領域とを備える第2の表面を有し、前記第1の半導体チップ上に積層された第2の半導体チップと、
前記第1の半導体チップと前記第2の半導体チップとを電気的に接続するように、前記第1の表面の前記第1の接続領域と前記第2の表面の前記第2の接続領域との間に設けられた第1のバンプ接続部と、
前記第1の表面の前記第1の非接続領域および前記第2の表面の前記第2の非接続領域の少なくとも一方の領域に局所的に設けられ、かつ前記第1の非接続領域および前記第2の非接続領域の他方の領域と非接着状態で接触する第1のストッパ用突起と、
前記第1の表面の前記第1の非接続領域と前記第2の表面の前記第2の非接続領域との間に局所的に設けられ、前記第1および第2の表面に接着された第1の接着用突起と、
前記第1の半導体チップの前記第1の表面と前記第2の半導体チップの前記第2の表面との間の隙間に充填された第1の樹脂とを具備し、
前記第1のストッパ用突起は、前記第1のバンプ接続部より前記第1の表面または前記第2の表面の外周に近い位置に複数設けられていることを特徴とする半導体装置。 - さらに、前記第2の半導体チップ上に積層された第3の半導体チップを具備し、
前記第2の半導体チップは、第3の接続領域と、前記第3の接続領域を除く第3の非接続領域とを備え、前記第2の表面とは反対側の第3の表面を有し、
前記第3の半導体チップは、前記第3の接続領域と対向する第4の接続領域と、前記第4の接続領域を除く第4の非接続領域とを備える第4の表面を有し、
前記第2の半導体チップと前記第3の半導体チップとは、前記第3の表面の前記第3の接続領域と前記第4の表面の前記第4の接続領域との間に設けられた第2のバンプ接続部により電気的に接続されており、
前記第2の半導体チップの前記第3の表面と前記第3の半導体チップの前記第4の表面との間には、前記第3の表面の前記第3の非接続領域および前記第4の表面の前記第4の非接続領域の少なくとも一方の領域に局所的に設けられ、かつ前記第3の非接続領域および前記第4の非接続領域の他方の領域と非接着状態で接触する第2のストッパ用突起が配置されており、
前記第2のストッパ用突起は、前記第2のバンプ接続部より前記第3の表面または前記第4の表面の外周に近い位置に複数設けられており、
前記第3の表面の前記第3の非接続領域と前記第4の表面の前記第4の非接続領域との間には、前記第3および第4の表面に接着された第2の接着用突起が局所的に配置されており、
前記第2の半導体チップの前記第3の表面と前記第3の半導体チップの前記第4の表面との間の隙間には第2の樹脂が充填されている、請求項2に記載の半導体装置。 - 第1の接続領域と、前記第1の接続領域を除く第1の非接続領域と、前記第1の接続領域に設けられた第1のバンプ電極とを備える第1の表面を有する第1の半導体チップを用意する工程と、
前記第1の接続領域に対応する第2の接続領域と、前記第2の接続領域を除く第2の非接続領域と、前記第2の接続領域に設けられた第2のバンプ電極とを備える第2の表面を有する第2の半導体チップを用意する工程と、
前記第1の表面の前記第1の非接続領域および前記第2の表面の前記第2の非接続領域の少なくとも一方の領域に、第1のストッパ用突起および第1の接着用突起、あるいは第1のストッパ兼接着用突起を局所的に形成する工程と、
前記第1のバンプ電極と前記第2のバンプ電極とを位置合わせしつつ、前記第1の半導体チップ上に前記第2の半導体チップを積層する工程と、
前記第1のストッパ用突起または前記第1のストッパ兼接着用突起で前記第1の半導体チップの前記第1の表面と前記第2の半導体チップの前記第2の表面との間の隙間を維持しつつ、前記第1のバンプ電極と前記第2のバンプ電極とを接触させると共に、前記第1の接着用突起または前記第1のストッパ兼接着用突起を前記第1の非接続領域および前記第2の非接続領域の他方の領域に接着する工程と、
前記第1の接着用突起または前記第1のストッパ兼接着用突起を接着した後、前記第1のバンプ電極と前記第2のバンプ電極を加熱して接続する工程と、
前記第1の半導体チップの前記第1の表面と前記第2の半導体チップの前記第2の表面との間の隙間に第1の樹脂を充填する工程と
を具備することを特徴とする半導体装置の製造方法。
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JP5017930B2 (ja) * | 2006-06-01 | 2012-09-05 | 富士通株式会社 | 半導体装置、はんだバンプ接続用基板の製造方法及び半導体装置の製造方法 |
JP4435187B2 (ja) | 2007-02-05 | 2010-03-17 | 株式会社東芝 | 積層型半導体装置 |
US8421244B2 (en) * | 2007-05-08 | 2013-04-16 | Samsung Electronics Co., Ltd. | Semiconductor package and method of forming the same |
US7973310B2 (en) * | 2008-07-11 | 2011-07-05 | Chipmos Technologies Inc. | Semiconductor package structure and method for manufacturing the same |
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2012
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- 2012-05-23 TW TW101118423A patent/TWI499022B/zh active
- 2012-05-25 JP JP2012119530A patent/JP5814859B2/ja active Active
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US10811393B2 (en) | 2016-09-23 | 2020-10-20 | Toshiba Memory Corporation | Memory device |
US11270981B2 (en) | 2016-09-23 | 2022-03-08 | Kioxia Corporation | Memory device |
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US9224713B2 (en) | 2015-12-29 |
CN102800662A (zh) | 2012-11-28 |
US8710654B2 (en) | 2014-04-29 |
US20140206144A1 (en) | 2014-07-24 |
TW201301464A (zh) | 2013-01-01 |
CN102800662B (zh) | 2015-04-01 |
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US20130134583A1 (en) | 2013-05-30 |
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