JP4203031B2 - 積層型電子部品の製造方法 - Google Patents
積層型電子部品の製造方法 Download PDFInfo
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- JP4203031B2 JP4203031B2 JP2005048236A JP2005048236A JP4203031B2 JP 4203031 B2 JP4203031 B2 JP 4203031B2 JP 2005048236 A JP2005048236 A JP 2005048236A JP 2005048236 A JP2005048236 A JP 2005048236A JP 4203031 B2 JP4203031 B2 JP 4203031B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Description
具備することを特徴としている。
Claims (7)
- 電極部を有する基板上に第1の接着層を介して第1の電極パッドを有する第1の電子部品を接着する工程と、
前記電極部と前記第1の電極パッドとを、第1のボンディングワイヤを介して電気的に接続する工程と、
前記第1の電子部品と前記第1のボンディングワイヤとの間の空間に、充填時粘度が1Pa・s以上1000Pa・s未満の範囲の熱硬化性樹脂からなる第1の絶縁性樹脂を充填する工程と、
前記第1の電子部品上に第2の電極パッドを有する第2の電子部品を接着する工程であって、接着時粘度が1kPa・s以上100kPa・s以下の範囲の熱硬化性樹脂からなる第2の絶縁性樹脂を前記第1の電子部品と前記第2の電子部品との間に配置し、前記第1の絶縁性樹脂と前記第2の絶縁性樹脂とを同時に硬化させることによって、前記第1の電子部品と前記第2の電子部品との間の空間を前記第1の絶縁性樹脂と前記第2の絶縁性樹脂とを有する第2の接着層で封止しつつ、前記第1の電子部品と前記第2の電子部品とを接着する工程と、
前記電極部と前記第2の電極パッドとを、第2のボンディングワイヤを介して電気的に接続する工程と
を具備することを特徴とする積層型電子部品の製造方法。 - 電極部を有する基板上に第1の接着層を介して第1の電極パッドを有する第1の電子部品を接着する工程と、
前記電極部と前記第1の電極パッドとを、第1のボンディングワイヤを介して電気的に接続する工程と、
前記第1の電子部品と前記第1のボンディングワイヤとの間の空間に、充填時粘度が1Pa・s以上1000Pa・s未満の範囲の熱硬化性樹脂からなる第1の絶縁性樹脂を充填し、前記第1の絶縁性樹脂を硬化させる工程と、
前記第1の電子部品上に第2の電極パッドを有する第2の電子部品を接着する工程であって、接着時粘度が1kPa・s以上100kPa・s以下の範囲の熱硬化性樹脂からなる第2の絶縁性樹脂を前記第1の電子部品と前記第2の電子部品との間に配置し、前記第2の絶縁性樹脂を硬化させることによって、前記第1の電子部品と前記第2の電子部品との間の空間を前記第1の絶縁性樹脂と前記第2の絶縁性樹脂とを有する第2の接着層で封止しつつ、前記第1の電子部品と前記第2の電子部品とを接着する工程と、
前記電極部と前記第2の電極パッドとを、第2のボンディングワイヤを介して電気的に接続する工程と
を具備することを特徴とする積層型電子部品の製造方法。 - 請求項1または請求項2記載の積層型電子部品の製造方法において、
前記第1のボンディングワイヤが前記第2の電子部品と接触しないように、前記第1の電子部品と前記第2の電子部品との間隔を前記第2の接着層で保持することを特徴とする積層型電子部品の製造方法。 - 電極部を有する基板上に第1の接着層を介して第1の電極パッドを有する第1の電子部品を接着する工程と、
前記電極部と前記第1の電極パッドとを、第1のボンディングワイヤを介して電気的に接続する工程と、
前記第1の電子部品と前記第1のボンディングワイヤとの間の空間に光硬化型絶縁性樹脂を充填し、前記光硬化型絶縁性樹脂に光を照射して硬化させる工程と、
前記第1の電子部品上に第2の電極パッドを有する第2の電子部品を接着する工程であって、接着時粘度が1kPa・s以上100kPa・s以下の範囲の熱硬化型絶縁性樹脂を前記第1の電子部品と前記第2の電子部品との間に配置し、前記熱硬化型絶縁性樹脂を硬化させることによって、前記第1の電子部品と前記第2の電子部品との間の空間を前記光硬化型絶縁性樹脂と前記熱硬化型絶縁性樹脂とを有する第2の接着層で封止しつつ、前記第1の電子部品と前記第2の電子部品とを接着する工程と、
前記電極部と前記第2の電極パッドとを、第2のボンディングワイヤを介して電気的に接続する工程と
を具備することを特徴とする積層型電子部品の製造方法。 - 請求項4記載の積層型電子部品の製造方法において、
前記第1のボンディングワイヤが前記第2の電子部品と接触しないように、前記第1の電子部品と前記第2の電子部品との間隔を前記第2の接着層で保持することを特徴とする積層型電子部品の製造方法。 - 請求項1ないし請求項5のいずれか1項記載の積層型電子部品の製造方法において、
前記第1および第2の電子部品は半導体素子および半導体素子を含むパッケージ部品から選ばれる少なくとも1種からなることを特徴とする積層型電子部品の製造方法。 - 請求項1、請求項2または請求項4記載の積層型電子部品の製造方法において、
前記第1のボンディングワイヤを、前記第2の電子部品の前記第1の電子部品との接着面に設けられた絶縁層を介して前記第2の電子部品と当接させ、前記第1のボンディングワイヤを前記基板側に変形させることを特徴とする積層型電子部品の製造方法。
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JP2005048236A JP4203031B2 (ja) | 2004-03-18 | 2005-02-24 | 積層型電子部品の製造方法 |
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JP2004078334 | 2004-03-18 | ||
JP2004078333 | 2004-03-18 | ||
JP2005048236A JP4203031B2 (ja) | 2004-03-18 | 2005-02-24 | 積層型電子部品の製造方法 |
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JP2005303267A JP2005303267A (ja) | 2005-10-27 |
JP4203031B2 true JP4203031B2 (ja) | 2008-12-24 |
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Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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JP4955997B2 (ja) * | 2005-12-27 | 2012-06-20 | 三洋電機株式会社 | 回路モジュールおよび回路モジュールの製造方法 |
JP4621595B2 (ja) * | 2006-01-11 | 2011-01-26 | 株式会社東芝 | 半導体装置の製造方法 |
JP2007242684A (ja) * | 2006-03-06 | 2007-09-20 | Disco Abrasive Syst Ltd | 積層型半導体装置及びデバイスの積層方法 |
JP2008192853A (ja) * | 2007-02-05 | 2008-08-21 | Sharp Corp | 複数の半導体素子を備える半導体装置、および半導体装置の製造方法 |
KR101309811B1 (ko) | 2010-10-08 | 2013-10-14 | 제일모직주식회사 | 반도체 패키지용 접착 필름 |
JP2012237840A (ja) * | 2011-05-11 | 2012-12-06 | Sumitomo Electric Ind Ltd | 光モジュール |
JP2013098240A (ja) * | 2011-10-28 | 2013-05-20 | Toshiba Corp | 記憶装置、半導体装置及び半導体装置の製造方法 |
JP6832282B2 (ja) * | 2015-02-18 | 2021-02-24 | ルミレッズ ホールディング ベーフェー | 複数の積み重ねられた発光デバイスを有するデバイス |
US10147705B2 (en) | 2017-02-21 | 2018-12-04 | Micron Technology, Inc. | Stacked semiconductor die assemblies with die substrate extensions |
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JP3643705B2 (ja) * | 1998-07-31 | 2005-04-27 | 三洋電機株式会社 | 半導体装置とその製造方法 |
JP4454181B2 (ja) * | 2001-05-15 | 2010-04-21 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
JP4206779B2 (ja) * | 2002-02-25 | 2009-01-14 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP2004253529A (ja) * | 2003-02-19 | 2004-09-09 | Nec Electronics Corp | 半導体装置及びその製造方法 |
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