CN110660734B - 半导体结构及其制造方法 - Google Patents
半导体结构及其制造方法 Download PDFInfo
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Abstract
本发明公开一种半导体结构及其制造方法,该半导体结构包括基底、双极结晶体管、第一内连线结构与第二内连线结构。基底具有彼此相对的第一面与第二面。双极结晶体管位于基底的第一面。双极结晶体管包括集极、基极与射极。集极设置在基底中。基极设置在基底上。射极设置在基极上。第一内连线结构位于基底的第一面,且电连接至基极。第二内连线结构位于基底的第二面,且电连接至集极。第一内连线结构更延伸至基底的第二面。第一内连线结构与第二内连线结构分别在基底的第二面电连接至外部电路。上述半导体结构可具有较佳的整体效能。
Description
技术领域
本发明涉及一种半导体结构及其制造方法,且特别是涉及一种可具有较佳整体效能的半导体结构。
背景技术
在一些半导体结构的应用中,半导体结构会整合多种半导体元件。举例来说,射频前端模块(radio frequency front-end module,RF FEM)可整合射频开关(RF switch)、低噪声放大器(low-noise amplifier,LNA)与功率放大器(power amplifier,PA)于其中。因此,如何有效提升半导体结构的整体效能为目前积极努力的目标。
发明内容
本发明的目的在于提出一种半导体结构,其可具有较佳的整体效能。
为达上述目的,本发明提供一种半导体结构,包括基底、双极结晶体管(bipolarJunction transistor,BJT)、第一内连线结构与第二内连线结构。基底具有彼此相对的第一面与第二面。双极结晶体管位于基底的第一面。双极结晶体管包括集极(collector)、基极(base)与射极(emitter)。集极设置在基底中。基极设置在基底上。射极设置在基极上。第一内连线结构位于基底的第一面,且电连接至基极。第二内连线结构位于基底的第二面,且电连接至集极。第一内连线结构更延伸至基底的第二面。第一内连线结构与第二内连线结构分别在基底的第二面电连接至外部电路。
依照本发明的一实施例所述,在上述半导体结构中,还可包括第三内连线结构。第三内连线结构位于基底的第一面,且电连接至射极。第三内连线结构更可延伸至基底的第二面。第三内连线结构可在基底的第二面电连接至外部电路。
依照本发明的一实施例所述,在上述半导体结构中,还可包括互补式金属氧化物半导体(complementary metal oxide semiconductor,CMOS)元件。CMOS元件位于基底的第一面。CMOS元件可包括N型金属氧化物半导体(N-type metal oxide semiconductor,NMOS)晶体管与P型金属氧化物半导体(P-type metal oxide semiconductor,PMOS)晶体管。NMOS晶体管可包括第一导体层、第一介电层、第一N型掺杂区与第二N型掺杂区。第一导体层设置在基底上。第一介电层设置在第一导体层与基底之间。第一N型掺杂区与第二N型掺杂区设置在第一导体层两侧的基底中。PMOS晶体管可包括第二导体层、第二介电层、第一P型掺杂区与第二P型掺杂区。第二导体层设置在基底上。第二介电层设置在第二导体层与基底之间。第一P型掺杂区与第二P型掺杂区设置在第二导体层两侧的基底中。
依照本发明的一实施例所述,在上述半导体结构中,还可包括第四内连线结构、第五内连线结构、第六内连线结构、第七内连线结构、第八内连线结构与第九内连线结构。第四内连线结构位于基底的第一面,且电连接至第一导体层。第五内连线结构位于基底的第一面,且电连接至第一N型掺杂区。第六内连线结构位于基底的第二面,且电连接至第二N型掺杂区。第七内连线结构位于基底的第一面,且电连接至第二导体层。第八内连线结构位于基底的第一面,且电连接至第一P型掺杂区。第九内连线结构位于基底的第二面,且电连接至第二P型掺杂区。第四内连线结构、第五内连线结构、第七内连线结构与第八内连线结构更可延伸至基底的第二面。第四内连线结构至第九内连线结构可分别在基底的第二面电连接至外部电路。
依照本发明的一实施例所述,在上述半导体结构中,还可包括高电阻率材料层(high resistivity material layer)。高电阻率材料层设置于CMOS元件与双极结晶体管上方。
依照本发明的一实施例所述,在上述半导体结构中,高电阻率材料层的电阻率例如是大于4000欧姆·厘米(Ω·cm)。
依照本发明的一实施例所述,在上述半导体结构中,基底可包括绝缘层与位于绝缘层上的半导体层。集极可设置在半导体层中。
依照本发明的一实施例所述,在上述半导体结构中,双极结晶体管例如是异质结双极晶体管(heterojunction bipolar transistor,HBT)。
依照本发明的一实施例所述,在上述半导体结构中,集极与射极可具有第一导电型,且基极可具有第二导电型。
依照本发明的一实施例所述,在上述半导体结构中,集极可包括重掺杂区与轻掺杂区。重掺杂区位于基底中。轻掺杂区位于基底中,且位于重掺杂区与基极之间。
依照本发明的一实施例所述,在上述半导体结构中,还可包括第一掺杂区与第二掺杂区。第一掺杂区与第二掺杂区位于射极两侧的基极中,且具有第二导电型。第一内连线结构可电连接至第一掺杂区或第二掺杂区。
本发明提供一种半导体结构的制造方法,包括以下步骤。提供基底。基底具有彼此相对的第一面与第二面。在基底的第一面形成双极结晶体管。双极结晶体管包括集极、基极与射极。集极设置在基底中。基极设置在基底上。射极设置在基极上。在基底的第一面形成电连接至基极的第一内连线结构。在基底的第二面形成电连接至集极的第二内连线结构。第一内连线结构更延伸至基底的第二面。第一内连线结构与第二内连线结构分别在基底的第二面电连接至外部电路。
依照本发明的一实施例所述,在上述半导体结构的制造方法中,还可包括在基底的第一面形成电连接至射极的第三内连线结构。第三内连线结构更可延伸至基底的第二面。第三内连线结构可在基底的第二面电连接至外部电路。
依照本发明的一实施例所述,在上述半导体结构的制造方法中,还可包括在基底的第一面形成CMOS元件。CMOS元件可包括NMOS晶体管与PMOS晶体管。NMOS晶体管可包括第一导体层、第一介电层、第一N型掺杂区与第二N型掺杂区。第一导体层设置在基底上。第一介电层设置在第一导体层与基底之间。第一N型掺杂区与第二N型掺杂区设置在第一导体层两侧的基底中。PMOS晶体管可包括第二导体层、第二介电层、第一P型掺杂区与第二P型掺杂区。第二导体层设置在基底上。第二介电层设置在第二导体层与基底之间。第一P型掺杂区与第二P型掺杂区设置在第二导体层两侧的基底中。
依照本发明的一实施例所述,在上述半导体结构的制造方法中,还可包括以下步骤。在基底的第一面形成电连接至第一导体层的第四内连线结构。在基底的第一面形成电连接至第一N型掺杂区的第五内连线结构。在基底的第二面形成电连接至第二N型掺杂区的第六内连线结构。在基底的第一面形成电连接至第二导体层的第七内连线结构。在基底的第一面形成电连接至第一P型掺杂区的第八内连线结构。在基底的第二面形成电连接至第二P型掺杂区的第九内连线结构。第四内连线结构、第五内连线结构、第七内连线结构与第八内连线结构更可延伸至基底的第二面。第四内连线结构至第九内连线结构可分别在基底的第二面电连接至外部电路。
依照本发明的一实施例所述,在上述半导体结构的制造方法中,还可包括在CMOS元件与双极结晶体管上方形成高电阻率材料层。
依照本发明的一实施例所述,在上述半导体结构的制造方法中,基底例如是绝缘体上有半导体(semiconductor on insulator,SOI)基底。SOI基底可包括基底层、绝缘层与半导体层。绝缘层设置在基底层上。半导体层设置在绝缘层上。集极可设置在半导体层中。在形成高电阻率材料层之后,可移除基底层。
依照本发明的一实施例所述,在上述半导体结构的制造方法中,集极与所述射极可具有第一导电型,且基极可具有第二导电型。
依照本发明的一实施例所述,在上述半导体结构的制造方法中,集极的形成方法可包括以下步骤。在基底中形成重掺杂区。在重掺杂区与基极之间的基底中形成轻掺杂区。
依照本发明的一实施例所述,在上述半导体结构的制造方法中,还可包括在射极两侧的基极中形成具有第二导电型的第一掺杂区与第二掺杂区。第一内连线结构电连接至第一掺杂区或第二掺杂区。
基于上述,在本发明所提出的半导体结构及其制造方法中,第一内连线结构与第二内连线结构分别电连接至基极与集极,且部分第一内连线结构与第二内连线结构位于基底的不同面。因此,可降低双极结晶体管中的基极与集极之间的电容,进而提升半导体结构的整体效能。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附的附图作详细说明如下。
附图说明
图1A至图1M为本发明一实施例的半导体结构的制造流程剖视图。
符号说明
100:基底
100a:基底层
100b:绝缘层
100c:半导体层
102、106:导体层
104、108、178、188:介电层
110、112、138:间隙壁
114、116、118、120、144、146:掺杂区
122、124、134:保护层
126:图案化光致抗蚀剂层
128:集极
128a:重掺杂区
128b:轻掺杂区
130:基极层
130a:基极
132:开口
136:射极层
136a:射极
140、142:N型掺杂区
148、150:P型掺杂区
152、154、156、158、160、162、164、166、168、182、184、186:金属硅化物层
170:双极结晶体管
172:CMOS元件
174:NMOS晶体管
176:PMOS晶体管
180:高电阻率材料层
190:外部电路
C1、C2:通道
IS1~IS9:内连线结构
ST:隔离结构
具体实施方式
图1A至图1M为本发明一实施例的半导体结构的制造流程剖视图。
请参照图1A,提供基底100。基底100具有彼此相对的第一面S1与第二面S2。第一面S1与第二面S2可为基底100的正面与背面中的一者与另一者。在本实施例中,第一面S1是以基底100的正面为例,且第二面S2是以基底100的背面为例,但本发明并不以此为限。
在本实施例中,基底100是以SOI基底为例,但本发明并不以此为限。SOI基底可为完全空乏型SOI(fully depleted SOI,FD SOI)基底或部分空乏型SOI(partiallydepleted SOI,PD SOI)基底。基底100可包括基底层100a、绝缘层100b与半导体层100c。基底层100a的材料例如是半导体材料,如硅。绝缘层100b设置在基底层100a上。绝缘层100b的材料例如是氧化硅。半导体层100c设置在绝缘层100b上。半导体层106的材料例如是硅。此外,在基底100中可形成有隔离结构ST。隔离结构ST例如是浅沟渠隔离结构(STI)。隔离结构ST的材料例如是氧化硅。
在基底100的第一面S1上可形成有导体层102、介电层104、导体层106、介电层108。导体层102与导体层106分别设置在基底100上。在本实施例中,导体层102与导体层106分别可设置在半导体层100c上。导体层102与导体层106分别可作为栅极。导体层102与导体层106的材料例如分别是掺杂多晶硅。介电层104设置在导体层102与基底100之间。介电层108设置在导体层106与基底100之间。介电层104与介电层108分别可作为栅介电层。介电层104与介电层108的材料例如分别是氧化硅。
此外,在导体层102的侧壁上可形成有间隙壁110,且在导体层106的侧壁上可形成有间隙壁112。间隙壁110与间隙壁112分别可为单层结构或多层结构。间隙壁110与间隙壁112的材料例如分别是氮化硅、氧化硅或其组合。
另外,在基底100中可形成有掺杂区114、掺杂区116、掺杂区118与掺杂区120。在本实施例中,掺杂区114、掺杂区116、掺杂区118与掺杂区120分别可设置在半导体层100c中。掺杂区114、掺杂区116、掺杂区118与掺杂区120分别可用以作为轻掺杂漏极(lightlydoped drain,LDD)。掺杂区114与掺杂区116分别是以具有N型导电型为例,且掺杂区118与掺杂区120分别是以具有P型导电型为例,但本发明并不以此为限。
请参照图1B,可在基底100上形成保护层122。保护层122的材料例如是氧化硅。保护层122的形成方法例如是化学气相沉积法(CVD)。
接着,可在保护层122上形成保护层124。保护层124的材料例如是多晶硅。保护层124的形成方法例如是化学气相沉积法。
然后,可在保护层124上形成图案化光致抗蚀剂层126。图案化光致抗蚀剂层126暴露出部分保护层124。图案化光致抗蚀剂层126例如是通过光刻制作工艺所形成。
接下来,移除图案化光致抗蚀剂层126所暴露出的保护层124。保护层124的移除方法例如是湿式蚀刻法或干式蚀刻法。
之后,在图案化光致抗蚀剂层126所暴露出的区域中的基底100中形成集极128。在本实施例中,集极128可形成在半导体层100c中。集极128的形成方法例如是以图案化光致抗蚀剂层126作为掩模,对半导体层100c进行离子注入制作工艺。
集极128的形成方法可包括以下步骤。以图案化光致抗蚀剂层126作为掩模,在基底100中形成重掺杂区128a。接着,以图案化光致抗蚀剂层126作为掩模,在重掺杂区128a上方的基底100中形成轻掺杂区128b。集极128可包括重掺杂区128a与轻掺杂区128b。相较于重掺杂区128a,轻掺杂区128b更接近而基底100的第一面S1。在本实施例中,虽然是以先形成重掺杂区128a,再形成轻掺杂区128b为例,但本发明并不以此为限。在另一实施例中,可先形成轻掺杂区128b,再形成重掺杂区128a。
集极128可具有第一导电型。以下,所记载的第一导电型与第二导电型可分别为N型导电型与P型导电型中的一者与另一者。在本实施例中,第一导电型是以N型导电型为例,且第二导电型是以P型导电型为例,但本发明并不以此为限。
请参照图1C,移除图案化光致抗蚀剂层126。图案化光致抗蚀剂层126的移除方法例如是干式去光致抗蚀剂法(dry strip method)或湿式去光致抗蚀剂法(wet stripmethod)。
接着,移除保护层124所暴露出的保护层122,而暴露出基底100。保护层122的移除方法例如是湿式蚀刻法。湿式蚀刻法所使用的蚀刻剂例如是稀释氢氟酸。
然后,可在保护层124与基底100上形成基极层130。基极层130可具有第二导电型(如,P型)。基极层130的材料可为经掺杂的半导体材料,如经掺杂的III-V族半导体材料。在本实施例中,基极层130的材料是以经掺杂的SiGe为例,但本发明并不以此为限。基极层130的形成方法例如是临场掺杂(in-situ doping)的外延成长法。
请参照图1D,可在基极层130上形成具有开口132的保护层134。开口132暴露出集极128上方的部分基极层130。保护层134可为单层结构或多层结构。保护层134的材料例如是氧化硅、氮化硅或其组合。保护层134的形成方法例如是先通过化学气相沉积法形成保护材料层(未示出),再通过光刻制作工艺与蚀刻制作工艺对保护材料层进行图案化。
然后,可在保护层134与基极层130上形成射极层136。射极层136穿过开口132,且连接至基极层130。射极层136可具有第一导电型(如,N型)。射极层136的材料例如是经掺杂的半导体材料。在本实施例中,射极层136的材料是以掺杂多晶硅为例,但本发明并不以此为限。掺杂多晶硅的形成方法例如是使用临场(in-situ)掺杂的化学气相沉积法或先形成未掺杂多晶硅,再对未掺杂多晶硅进行掺杂。
请参照图1E,可对射极层136进行图案化制作工艺,而形成射极136a。对射极层136所进行的图案化制作工艺例如是组合使用光刻制作工艺与蚀刻制作工艺。
接着,可在射极136a的侧壁上形成间隙壁138。间隙壁138可为单层结构或多层结构。间隙壁138的材料例如是氮化硅、氧化硅或其组合。
然后,可移除未被射极136a与间隙壁138覆盖的保护层134。未被射极136a与间隙壁138覆盖的保护层134的移除方法例如是干式蚀刻法或湿式蚀刻法。
请参照图1F,可对基极层130进行图案化制作工艺,而形成基极130a。对基极层130所进行的图案化制作工艺例如是组合使用光刻制作工艺与蚀刻制作工艺。
接着,可移除未被基极130a覆盖的保护层124。未被基极130a覆盖的保护层124的移除方法例如是湿式蚀刻法或干式蚀刻法。
请参照图1G,可在导体层102两侧的基底100中形成N型掺杂区140与N型掺杂区142。在本实施例中,N型掺杂区140与N型掺杂区142可形成在导体层102两侧的半导体层100c中。N型掺杂区140与N型掺杂区142的掺杂浓度可大于掺杂区114与掺杂区116的掺杂浓度。N型掺杂区140与N型掺杂区142可使用离子注入掩模进行离子注入制作工艺而形成。
接着,可在射极136a两侧的基极130a中形成具有第二导电型(如,P型)的掺杂区144与掺杂区146。掺杂区144与掺杂区146的掺质浓度可大于基极130a的掺质浓度。另外,可在导体层106两侧的基底100中形成P型掺杂区148与P型掺杂区150。在本实施例中,P型掺杂区148与P型掺杂区150可形成在导体层106两侧的半导体层100c中。P型掺杂区148与P型掺杂区150的掺杂浓度可大于掺杂区118与掺杂区120的掺杂浓度。
在本实施例中,由于掺杂区144与掺杂区146是以P型导电型为例,因此掺杂区144与掺杂区146以及P型掺杂区148与P型掺杂区150可使用相同的离子注入掩模进行离子注入制作工艺而形成,但本发明并不以此为限。在另一实施例中,掺杂区144与掺杂区146以及P型掺杂区148与P型掺杂区150也可分别形成。
此外,所述技术领域具有通常知识者可依据制作工艺需求来调整N型掺杂区140、N型掺杂区142、掺杂区144、掺杂区146、P型掺杂区148与P型掺杂区150的形成顺序,本发明并不限于上述实施例所揭示的内容。
请参照图1H,可移除未被掺杂区144与掺杂区146覆盖的保护层122。未被P型掺杂区148与P型掺杂区150覆盖的保护层122的移除方法例如是湿式蚀刻法。湿式蚀刻法所使用的蚀刻剂例如是稀释氢氟酸。
接着,可分别在射极136a、掺杂区144、掺杂区146、导体层102、N型掺杂区140、N型掺杂区142、导体层106、P型掺杂区148与P型掺杂区150上形成金属硅化物层152、金属硅化物层154、金属硅化物层156、金属硅化物层158、金属硅化物层160、金属硅化物层162、金属硅化物层164、金属硅化物层166与金属硅化物层168。金属硅化物层152、金属硅化物层154、金属硅化物层156、金属硅化物层158、金属硅化物层160、金属硅化物层162、金属硅化物层164、金属硅化物层166与金属硅化物层168的材料例如是硅化钴(cobalt silicide)或硅化镍(nickel silicide)。金属硅化物层152、金属硅化物层154、金属硅化物层156、金属硅化物层158、金属硅化物层160、金属硅化物层162、金属硅化物层164、金属硅化物层166与金属硅化物层168的形成方法例如是进行自动对准金属硅化物制作工艺(salicidationprocess)。
此外,通过上述方法可在基底100的第一面S1形成双极结晶体管170与CMOS元件172,但本发明的双极结晶体管170与CMOS元件172的制造方法并不以此为限。本实施例的半导体结构可应用于射频前端模块(RF FEM)。当本实施例的半导体结构应用于射频前端模块时,CMOS元件172可用于形成射频开关(RF switch),且双极结晶体管170可用于形成功率放大器(PA)。
双极结晶体管170位于基底100的第一面S1。双极结晶体管170包括集极128、基极130a与射极136a。双极结晶体管170例如是异质结双极晶体管(HBT)。集极128设置在基底100中。在本实施例中,集极128可设置在半导体层100c中。集极128可包括重掺杂区128a与轻掺杂区128b。重掺杂区128a位于基底100中。轻掺杂区128b位于基底100中,且位于重掺杂区128a与基极130a之间。基极130a设置在基底100上。射极136a设置在基极130a上。射极136a穿过保护层134的开口132,且连接至基极130a。集极128与射极136a可具有第一导电型,且基极130a可具有第二导电型。
CMOS元件172位于基底100的第一面S1。CMOS元件172包括设置在基底100上的NMOS晶体管174与PMOS晶体管176。
NMOS晶体管174可包括导体层102、介电层104、N型掺杂区140与N型掺杂区142,且还可包括掺杂区114、掺杂区116、间隙壁110、金属硅化物层158、金属硅化物层160与金属硅化物层162中的至少一者。导体层102设置在基底100上。NMOS晶体管174的通道C1可位于导体层102下方的基底100中。介电层104设置在导体层102与基底100之间。N型掺杂区140与N型掺杂区142设置在导体层102两侧的基底100中。N型掺杂区140与N型掺杂区142分别可作为源极与漏极中的一者与另一者。在本实施例中,是以N型掺杂区140作为源极为例,且是以N型掺杂区142作为漏极为例,但本发明并不以此为限。掺杂区114位于N型掺杂区140与通道C1之间。掺杂区116位于N型掺杂区142与通道C1之间。间隙壁110设置于导体层102的侧壁上。金属硅化物层158、金属硅化物层160与金属硅化物层162分别位于导体层102、N型掺杂区140与N型掺杂区142上。
PMOS晶体管176可包括导体层106、介电层108、P型掺杂区148与P型掺杂区150,且还可包括掺杂区118、掺杂区120、间隙壁112、金属硅化物层164、金属硅化物层166与金属硅化物层168中的至少一者。导体层106设置在基底100上。PMOS晶体管176的通道C2可位于导体层106下方的基底100中。介电层108设置在导体层106与基底100之间。P型掺杂区148与P型掺杂区150设置在导体层106两侧的基底100中。P型掺杂区148与P型掺杂区150分别可作为源极与漏极中的一者与另一者。在本实施例中,是以P型掺杂区148作为源极为例,且是以P型掺杂区150作为漏极为例,但本发明并不以此为限。掺杂区118位于P型掺杂区148与通道C2之间。掺杂区120位于P型掺杂区150与通道C2之间。间隙壁112设置于导体层106的侧壁上。金属硅化物层164、金属硅化物层166与金属硅化物层168分别位于导体层106、P型掺杂区148与P型掺杂区150上。
在本实施例中,虽然是以PMOS晶体管176位于NMOS晶体管174与双极结晶体管170之间为例,但本发明并不以此为限。所属技术领域具有通常知识者可依据产品需求调整双极结晶体管170、NMOS晶体管174与PMOS晶体管176的设置方式。
此外,NMOS晶体管174的通道C1的顶面、PMOS晶体管176的通道C2的顶面与双极结晶体管170的集极128的顶面等高,因此可有效地将CMOS元件172与双极结晶体管170进行整合,进而提升半导体结构的整体效能。在本实施例中,NMOS晶体管174的通道C1的顶面、PMOS晶体管176的通道C2的顶面与双极结晶体管170的集极128的顶面例如是位于基底100的第一面S1。
请参照图1I,可形成覆盖双极结晶体管170与CMOS元件172的介电层178。介电层178可为多层结构。介电层178的材料例如是氧化硅。介电层178的形成方法例如是化学气相沉积法。
接着,在基底100的第一面S1形成电连接至基极130a的内连线结构IS1。内连线结构IS1可经由金属硅化物156与掺杂区146电连接至基极130a。可在基底100的第一面S1形成电连接至射极136a的内连线结构IS2。内连线结构IS2可经由金属硅化物152电连接至射极136a。可在基底100的第一面S1形成电连接至导体层102的内连线结构IS3。内连线结构IS3可经由金属硅化物158电连接至导体层102。可在基底100的第一面S1形成电连接至N型掺杂区140的内连线结构IS4。内连线结构IS4可经由金属硅化物160电连接至N型掺杂区140。可在基底100的第一面S1形成电连接至导体层106的内连线结构IS5。内连线结构IS5可经由金属硅化物164电连接至导体层106。可在基底100的第一面S1形成电连接至P型掺杂区148的内连线结构IS6。内连线结构IS6可经由金属硅化物166电连接至P型掺杂区148。内连线结构IS1至内连线结构IS6分别可包括接触窗、导线或其组合。内连线结构IS1至内连线结构IS6可为多层内连线结构。内连线结构IS1至内连线结构IS6的材料例如是钨、铜、铝或其组合。内连线结构IS1至内连线结构IS6可利用金属内连线制作工艺形成在介电层178中。
请参照图1J,可在CMOS元件172与双极结晶体管170上方形成高电阻率材料层180。当本实施例的半导体结构应用于射频前端模块时,高电阻率材料层180可用以降低噪声(noise)。高电阻率材料层180的电阻率例如是大于4000欧姆·厘米(Ω·cm)。高电阻率材料层180的材料例如是高电阻率硅、玻璃、石英或聚合物材料(如,塑胶材料)。高电阻率材料层180的形成方法例如是翻转经上述处理的晶片,且将上述半导体结构接合至高电阻率材料层180。在本实施例中,是以将半导体结构的介电层178接合至高电阻率材料层180为例,但本发明并不以此为限。
请参照图1K,可移除基底层100a。基底层100a的移除方法例如是研磨法、湿式蚀刻法或其组合。
请参照图1L,可对绝缘层100b进行图案化制作工艺,而暴露出集极128、N型掺杂区142与P型掺杂区150。对绝缘层100b所进行的图案化制作工艺例如是组合使用光刻制作工艺与蚀刻制作工艺。
接着,可分别在绝缘层100b所暴露出的集极128、N型掺杂区142与P型掺杂区150上形成金属硅化物层182、金属硅化物层184与金属硅化物层186。金属硅化物层182、金属硅化物层184与金属硅化物层186的材料例如是硅化钴或硅化镍。金属硅化物层182、金属硅化物层184与金属硅化物层186的形成方法例如是进行自动对准金属硅化物制作工艺。
此外,双极结晶体管170更可包括设置在绝缘层100b所暴露出的集极128上的金属硅化物层182。NMOS晶体管174还可包括设置在绝缘层100b所暴露出的N型掺杂区142上的金属硅化物层184。PMOS晶体管176还可包括设置在绝缘层100b所暴露出的P型掺杂区150上的金属硅化物层186。
请参照图1M,可形成覆盖绝缘层100b、金属硅化物层182、金属硅化物层184与金属硅化物层186的介电层188。介电层188的材料例如是氧化硅。介电层188的形成方法例如是化学气相沉积法。
接着,在基底100的第二面S2形成电连接至集极128的内连线结构IS7。内连线结构IS7可经由金属硅化物182电连接至集极128。可在基底100的第二面S2形成电连接至N型掺杂区142的内连线结构IS8。内连线结构IS8可经由金属硅化物184电连接至N型掺杂区142。可在基底100的第二面S2形成电连接至P型掺杂区150的内连线结构IS9。内连线结构IS9可经由金属硅化物186电连接至P型掺杂区150。内连线结构IS7至内连线结构IS9分别可包括接触窗、导线或其组合。内连线结构IS7至内连线结构IS9分别可为单层内连线结构或多层内连线结构。内连线结构IS7至内连线结构IS9的材料例如是钨、铜、铝或其组合。内连线结构IS7至内连线结构IS9可利用金属内连线制作工艺形成在介电层188中,且可延伸至介电层188上。
此外,内连线结构IS1至内连线结构IS6还可分别延伸至基底100的第二面S2。内连线结构IS1至内连线结构IS9可分别在基底100的第二面S2电连接至外部电路190。如此一来,外部电路190可电连接至内连线结构IS1至内连线结构IS9,以分别提供电压至双极结晶体管170与CMOS元件172中所对应的电极。外部电路190电连接到内连线结构IS1至内连线结构IS9的方法可采用所属技术领域所周知的电连接方法,在此不再进行说明。
此外,在图1I至图1M的剖视图中,以虚线绘示的内连线结构为不位于此剖面上的内连线结构。在本实施例中,内连线结构IS1至内连线结构IS9的层数与布局(layout)并不限于附图所绘示的内容,所属技术领域中具有通常知识者可依据产品需求来调整内连线结构IS1至内连线结构IS9的层数与布局。
基于上述可知,内连线结构IS1与内连线结构IS7分别电连接至基极130a与集极128,且部分内连线结构IS1与内连线结构IS7位于基底100的不同面。因此,可降低双极结晶体管170中的基极130a与集极128之间的电容,进而提升半导体结构的整体效能。
此外,内连线结构IS2与内连线结构IS7分别电连接至射极136a与集极128,且部分内连线结构IS2与内连线结构IS7位于基底100的不同面。因此,可降低双极结晶体管170中的射极136a与集极128之间的电容,以进一步提升半导体结构的整体效能。
另外,内连线结构IS4与内连线结构IS8分别电连接至N型掺杂区140(源极)与N型掺杂区142(漏极),且部分内连线结构IS4与内连线结构IS8位于基底100的不同面。因此,可降低NMOS晶体管174中的源极与漏极之间的电容,以进一步提升半导体结构的整体效能。
另一方面,内连线结构IS6与内连线结构IS9分别电连接至P型掺杂区148(源极)与P型掺杂区150(漏极),且部分内连线结构IS6与内连线结构IS9位于基底100的不同面。因此,可降低PMOS晶体管176中的源极与漏极之间的电容,以进一步提升半导体结构的整体效能。
请参照图1K,在一实施例中,半导体结构包括基底100、CMOS元件172与双极结晶体管170,且还可包括掺杂区144与掺杂区146、保护层134、间隙壁138与高电阻率材料层180中的至少一者。基底100可包括绝缘层100b与位于绝缘层100b上的半导体层100c。
CMOS元件172包括设置在基底100上的NMOS晶体管174与PMOS晶体管176。NMOS晶体管174与PMOS晶体管176的详细内容可参照上述实施例,在此不再重复说明。
双极结晶体管170包括集极128、基极130a与射极136a。双极结晶体管170例如是异质结双极晶体管(HBT)。集极128设置在基底100中。在本实施例中,集极128可设置在半导体层100c中。集极128可包括重掺杂区128a与轻掺杂区128b。重掺杂区128a位于基底100中。轻掺杂区128b位于基底100中,且位于重掺杂区128a与基极130a之间。基极130a设置在基底100上。射极136a设置在基极130a上。NMOS晶体管174的通道C1的顶面、PMOS晶体管176的通道C2的顶面与双极结晶体管170的集极128的顶面等高。集极128与射极136a可具有第一导电型(如,N型),且基极130a可具有第二导电型(如,P型)。双极结晶体管170的详细内容可参照上述实施例,在此不再重复说明。
掺杂区144与掺杂区146位于射极136a两侧的基极130a中,且具有第二导电型(如,P型)。保护层134位于基极130a与射极136a之间,且具有开口132。射极136a穿过开口132,且连接至基极130a。间隙壁138设置在射极136a的侧壁上。高电阻率材料层180设置于CMOS元件172与双极结晶体管170上方。高电阻率材料层的电阻率例如是大于4000欧姆·厘米(Ω·cm)。高电阻率材料层180的材料例如是高电阻率硅、玻璃、石英或聚合物材料(如,塑胶材料)。
此外,图1K的半导体结构中的各构件的材料、设置方式、形成方法与功效等,已于上述实施例中进行详尽地说明,在此不再重复说明。
基于上述实施例可知,在图1K的半导体结构及其制造方法中,由于NMOS晶体管174的通道C1的顶面、PMOS晶体管176的通道C2的顶面与双极结晶体管170的集极128的顶面等高,因此可有效地将CMOS元件172与双极结晶体管170进行整合,进而提升半导体结构的整体效能。
请参照图1M,在一实施例中,半导体结构包括基底100、双极结晶体管170、内连线结构IS1与内连线结构IS7,且还可包括CMOS元件172、内连线结构IS2至内连线结构IS6、内连线结构IS8、内连线结构IS9、掺杂区144与掺杂区146、保护层134、间隙壁138与高电阻率材料层180中的至少一者。基底100具有彼此相对的第一面S1与第二面S2。基底100可包括绝缘层100b与位于绝缘层100b上的半导体层100c。
双极结晶体管170位于基底100的第一面S1。双极结晶体管170包括集极128、基极130a与射极136a。双极结晶体管170例如是异质结双极晶体管(HBT)。集极128设置在基底100中。基极130a设置在基底100上。在本实施例中,集极128可设置在半导体层100c中。集极128可包括重掺杂区128a与轻掺杂区128b。重掺杂区128a位于基底100中。轻掺杂区128b位于基底100中,且位于重掺杂区128a与基极130a之间。射极136a设置在基极130a上。集极128与射极136a可具有第一导电型(如,N型),且基极130a可具有第二导电型(如,P型)。双极结晶体管170的详细内容可参照上述实施例,在此不再重复说明。
CMOS元件172位于基底100的第一面S1。CMOS元件172可包括NMOS晶体管174与PMOS晶体管176。NMOS晶体管174与PMOS晶体管176的详细内容可参照上述实施例,在此不再重复说明。此外,在本实施例中,双极结晶体管170与CMOS元件172的结构虽然揭露如上,但本发明并不以此为限。
内连线结构IS1至内连线结构IS6可分别位于基底100的第一面S1,且可分别电连接至基极130a、射极136a、导体层102、N型掺杂区140、导体层106与P型掺杂区148。内连线结构IS7至内连线结构IS9可分别位于基底100的第二面S2,且可分别电连接至集极128、N型掺杂区142与P型掺杂区150。内连线结构IS1至内连线结构IS6还可分别延伸至基底100的第二面S2。内连线结构IS1至内连线结构IS9可分别在基底100的第二面S2电连接至外部电路190。
掺杂区144与掺杂区146位于射极136a两侧的基极130a中,且具有第二导电型(如,P型)。内连线结构IS1可电连接至掺杂区144或掺杂区146。保护层134位于基极130a与射极136a之间,且具有开口132。射极136a穿过开口132,且连接至基极130a。间隙壁138设置在射极136a的侧壁上。高电阻率材料层180设置于CMOS元件172与双极结晶体管170上方。高电阻率材料层的电阻率例如是大于4000欧姆·厘米(Ω·cm)。高电阻率材料层180的材料例如是高电阻率硅、玻璃、石英或聚合物材料(如,塑胶材料)。
此外,图1M的半导体结构中的各构件的材料、设置方式、形成方法与功效等,已于上述实施例中进行详尽地说明,在此不再重复说明。
基于上述实施例可知,在图1M的半导体结构及其制造方法中,内连线结构IS1与内连线结构IS7分别电连接至基极130a与集极128,且部分内连线结构IS1与内连线结构IS7位于基底100的不同面。因此,可降低双极结晶体管170中的基极130a与集极128之间的电容,进而提升半导体结构的整体效能。
综上所述,在一实施例的半导体结构及其制造方法中,可有效地将半导体结构中的CMOS元件与双极结晶体管进行整合,进而提升半导体结构的整体效能。在一实施例的半导体结构及其制造方法中,可降低半导体结构的双极结晶体管中的基极与集极之间的电容,进而提升半导体结构的整体效能。
虽然结合以上实施例公开了本发明,然而其并非用以限定本发明,任何所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应当以附上的权利要求所界定的为准。
Claims (19)
1.一种半导体结构,其特征在于,包括:
基底,具有彼此相对的第一面与第二面,其中所述基底包括绝缘层与位于所述绝缘层上的半导体层;
双极结晶体管,位于所述基底的所述第一面,且包括:
集极,设置在所述基底的所述半导体层中;
基极,设置在所述基底上;以及
射极,设置在所述基极上;
保护层,位于所述基极与所述射极之间,且具有开口,其中所述射极穿过所述开口,且连接至所述基极;
第一内连线结构,位于所述基底的所述第一面,且电连接至所述基极;以及
第二内连线结构,位于所述基底的所述第二面,且电连接至所述集极,其中
所述第一内连线结构更贯穿所述半导体层,以延伸至所述基底的所述第二面,且
所述第一内连线结构与所述第二内连线结构分别在所述基底的所述第二面电连接至外部电路。
2.根据权利要求1所述的半导体结构,其特征在于,还包括:
第三内连线结构,位于所述基底的所述第一面,且电连接至所述射极,其中所述第三内连线结构更延伸至所述基底的所述第二面,且所述第三内连线结构在所述基底的所述第二面电连接至所述外部电路。
3.根据权利要求1所述的半导体结构,其特征在于,还包括:
互补式金属氧化物半导体元件,位于所述基底的所述第一面,且包括N型金属氧化物半导体晶体管与P型金属氧化物半导体晶体管,其中
所述N型金属氧化物半导体晶体管包括:
第一导体层,设置在所述基底上;
第一介电层,设置在所述第一导体层与所述基底之间;以及
第一N型掺杂区与第二N型掺杂区,设置在所述第一导体层两侧的所述基底中,且
所述P型金属氧化物半导体晶体管包括:
第二导体层,设置在所述基底上;
第二介电层,设置在所述第二导体层与所述基底之间;以及
第一P型掺杂区与第二P型掺杂区,设置在所述第二导体层两侧的所述基底中。
4.根据权利要求3所述的半导体结构,其特征在于,还包括:
第四内连线结构,位于所述基底的所述第一面,且电连接至所述第一导体层;
第五内连线结构,位于所述基底的所述第一面,且电连接至所述第一N型掺杂区;
第六内连线结构,位于所述基底的所述第二面,且电连接至所述第二N型掺杂区;
第七内连线结构,位于所述基底的所述第一面,且电连接至所述第二导体层;
第八内连线结构,位于所述基底的所述第一面,且电连接至所述第一P型掺杂区;以及
第九内连线结构,位于所述基底的所述第二面,且电连接至所述第二P型掺杂区,其中
所述第四内连线结构、所述第五内连线结构、所述第七内连线结构与所述第八内连线结构更延伸至所述基底的所述第二面,且
所述第四内连线结构至所述第九内连线结构分别在所述基底的所述第二面电连接至所述外部电路。
5.根据权利要求3所述的半导体结构,其特征在于,还包括:
高电阻率材料层,设置在所述互补式金属氧化物半导体元件与所述双极结晶体管上方。
6.根据权利要求5所述的半导体结构,其特征在于,所述高电阻率材料层的电阻率大于4000欧姆·厘米。
7.根据权利要求1所述的半导体结构,其特征在于,所述双极结晶体管包括异质结双极晶体管。
8.根据权利要求1所述的半导体结构,其特征在于,所述集极与所述射极具有第一导电型,且所述基极具有第二导电型。
9.根据权利要求8所述的半导体结构,其特征在于,所述集极包括:
重掺杂区,位于所述基底中;以及
轻掺杂区,位于所述基底中,且位于所述重掺杂区与所述基极之间。
10.根据权利要求8所述的半导体结构,其特征在于,还包括:
第一掺杂区与第二掺杂区,位于所述射极两侧的所述基极中,且具有所述第二导电型,其中
所述第一内连线结构电连接至所述第一掺杂区或所述第二掺杂区。
11.一种半导体结构的制造方法,其特征在于,包括:
提供基底,其中所述基底具有彼此相对的第一面与第二面,其中所述基底包括绝缘体上有半导体基底,且所述绝缘体上有半导体基底包括:
基底层;
绝缘层,设置在所述基底层上;以及
半导体层,设置在所述绝缘层上;
在所述基底的所述第一面形成双极结晶体管,其中所述双极结晶体管包括:
集极,设置在所述基底的所述半导体层中;
基极,设置在所述基底上;以及
射极,设置在所述基极上;
在所述基极与所述射极之间形成具有开口的保护层,其中所述射极穿过所述开口,且连接至所述基极;
在所述基底的所述第一面形成电连接至所述基极的第一内连线结构;以及
在所述基底的所述第二面形成电连接至所述集极的第二内连线结构,其中
所述第一内连线结构更贯穿所述半导体层,以延伸至所述基底的所述第二面,且
所述第一内连线结构与所述第二内连线结构分别在所述基底的所述第二面电连接至外部电路。
12.根据权利要求11所述的半导体结构的制造方法,其特征在于,还包括:
在所述基底的所述第一面形成电连接至所述射极的第三内连线结构,其中所述第三内连线结构更延伸至所述基底的所述第二面,且所述第三内连线结构在所述基底的所述第二面电连接至所述外部电路。
13.根据权利要求11所述的半导体结构的制造方法,其特征在于,还包括:
在所述基底的所述第一面形成互补式金属氧化物半导体元件,其中所述互补式金属氧化物半导体元件包括N型金属氧化物半导体晶体管与P型金属氧化物半导体晶体管,且
所述N型金属氧化物半导体晶体管包括:
第一导体层,设置在所述基底上;
第一介电层,设置在所述第一导体层与所述基底之间;以及
第一N型掺杂区与第二N型掺杂区,设置在所述第一导体层两侧的所述基底中,且
所述P型金属氧化物半导体晶体管包括:
第二导体层,设置在所述基底上;
第二介电层,设置在所述第二导体层与所述基底之间;以及
第一P型掺杂区与第二P型掺杂区,设置在所述第二导体层两侧的所述基底中。
14.根据权利要求13所述的半导体结构的制造方法,其特征在于,还包括:
在所述基底的所述第一面形成电连接至所述第一导体层的第四内连线结构;
在所述基底的所述第一面形成电连接至所述第一N型掺杂区的第五内连线结构;
在所述基底的所述第二面形成电连接至所述第二N型掺杂区的第六内连线结构;
在所述基底的所述第一面形成电连接至所述第二导体层的第七内连线结构;
在所述基底的所述第一面形成电连接至所述第一P型掺杂区的第八内连线结构;以及
在所述基底的所述第二面形成电连接至所述第二P型掺杂区的第九内连线结构,其中
所述第四内连线结构、所述第五内连线结构、所述第七内连线结构与所述第八内连线结构更延伸至所述基底的所述第二面,且
所述第四内连线结构至所述第九内连线结构分别在所述基底的所述第二面电连接至所述外部电路。
15.根据权利要求13所述的半导体结构的制造方法,其特征在于,还包括:
在所述互补式金属氧化物半导体元件与所述双极结晶体管上方形成高电阻率材料层。
16.根据权利要求15所述的半导体结构的制造方法,其特征在于,还包括:
在形成所述高电阻率材料层之后,移除所述基底层。
17.根据权利要求11所述的半导体结构的制造方法,其特征在于,所述集极与所述射极具有第一导电型,且所述基极具有第二导电型。
18.根据权利要求17所述的半导体结构的制造方法,其特征在于,所述集极的形成方法包括:
在所述基底中形成重掺杂区;以及
在所述重掺杂区与所述基极之间的所述基底中形成轻掺杂区。
19.根据权利要求17所述的半导体结构的制造方法,其特征在于,还包括:
在所述射极两侧的所述基极中形成具有所述第二导电型的第一掺杂区与第二掺杂区,其中
所述第一内连线结构电连接至所述第一掺杂区或所述第二掺杂区。
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6414371B1 (en) * | 2000-05-30 | 2002-07-02 | International Business Machines Corporation | Process and structure for 50+ gigahertz transistor |
KR20020061836A (ko) * | 2001-01-18 | 2002-07-25 | 엘지전자 주식회사 | 이종접합 바이폴라 트랜지스터 및 그 제조방법 |
CN1512595A (zh) * | 2002-12-24 | 2004-07-14 | 国际商业机器公司 | 具有多数载流子累积层作为子集电极的双极晶体管 |
CN101079441A (zh) * | 2006-05-25 | 2007-11-28 | 国际商业机器公司 | 半导体器件及其形成方法 |
CN101371359A (zh) * | 2005-10-28 | 2009-02-18 | Dsm解决方案股份有限公司 | 在硅和硅合金中使用互补结型场效应晶体管和mos晶体管的集成电路 |
CN104517987A (zh) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体存储控制单元、集成电路及集成电路的制造方法 |
CN106601753A (zh) * | 2015-10-19 | 2017-04-26 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100554465B1 (ko) * | 2003-11-19 | 2006-03-03 | 한국전자통신연구원 | SOI 기판 위에 구현된 SiGe BiCMOS 소자 및그 제조 방법 |
KR100586737B1 (ko) | 2003-12-26 | 2006-06-08 | 한국전자통신연구원 | SOI 기판 위에 구현된 NMOS 소자, PMOS 소자및 SiGe BiCMOS 소자 및 그 제조 방법 |
US8404557B2 (en) * | 2011-04-18 | 2013-03-26 | Infineon Technologies Austria Ag | Method for forming a semiconductor device and a semiconductor device |
US9177893B2 (en) * | 2011-05-17 | 2015-11-03 | Infineon Technologies Ag | Semiconductor component with a front side and a back side metallization layer and manufacturing method thereof |
US9040346B2 (en) * | 2012-05-03 | 2015-05-26 | Infineon Technologies Ag | Semiconductor package and methods of formation thereof |
US9673081B2 (en) * | 2012-05-25 | 2017-06-06 | Newport Fab, Llc | Isolated through silicon via and isolated deep silicon via having total or partial isolation |
US9159652B2 (en) * | 2013-02-25 | 2015-10-13 | Stmicroelectronics S.R.L. | Electronic device comprising at least a chip enclosed in a package and a corresponding assembly process |
US9105701B2 (en) * | 2013-06-10 | 2015-08-11 | Micron Technology, Inc. | Semiconductor devices having compact footprints |
US9312369B2 (en) * | 2014-06-04 | 2016-04-12 | Infineon Technologies Dresden Gmbh | Bipolar transistor structure and a method of manufacturing a bipolar transistor structure |
US9543403B2 (en) * | 2015-01-21 | 2017-01-10 | Globalfoundries Inc. | Bipolar junction transistor with multiple emitter fingers |
US9425269B1 (en) * | 2015-06-23 | 2016-08-23 | Globalfoundries Inc. | Replacement emitter for reduced contact resistance |
US20170373175A1 (en) * | 2016-06-24 | 2017-12-28 | Qualcomm Incorporated | Systems and methods for providing vertical access to the collector of a heterojunction bipolar transistor |
US10331844B2 (en) * | 2016-10-11 | 2019-06-25 | Globalfoundries Inc. | Methods of tuning current ratio in a current mirror for transistors formed with the same FEOL layout and a modified BEOL layout |
US10062683B1 (en) * | 2017-02-27 | 2018-08-28 | Qualcomm Incorporated | Compound semiconductor transistor and high-Q passive device single chip integration |
US10170578B2 (en) * | 2017-05-31 | 2019-01-01 | International Business Machines Corporation | Through-substrate via power gating and delivery bipolar transistor |
-
2018
- 2018-06-28 CN CN201810686366.7A patent/CN110660734B/zh active Active
- 2018-08-02 US US16/053,657 patent/US10411110B1/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6414371B1 (en) * | 2000-05-30 | 2002-07-02 | International Business Machines Corporation | Process and structure for 50+ gigahertz transistor |
KR20020061836A (ko) * | 2001-01-18 | 2002-07-25 | 엘지전자 주식회사 | 이종접합 바이폴라 트랜지스터 및 그 제조방법 |
CN1512595A (zh) * | 2002-12-24 | 2004-07-14 | 国际商业机器公司 | 具有多数载流子累积层作为子集电极的双极晶体管 |
CN101371359A (zh) * | 2005-10-28 | 2009-02-18 | Dsm解决方案股份有限公司 | 在硅和硅合金中使用互补结型场效应晶体管和mos晶体管的集成电路 |
CN101079441A (zh) * | 2006-05-25 | 2007-11-28 | 国际商业机器公司 | 半导体器件及其形成方法 |
CN104517987A (zh) * | 2013-09-27 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体存储控制单元、集成电路及集成电路的制造方法 |
CN106601753A (zh) * | 2015-10-19 | 2017-04-26 | 台湾积体电路制造股份有限公司 | 半导体器件及其形成方法 |
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CN110660734A (zh) | 2020-01-07 |
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