CN105702653A - 可靠且强健的电接触件 - Google Patents

可靠且强健的电接触件 Download PDF

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Publication number
CN105702653A
CN105702653A CN201510929195.2A CN201510929195A CN105702653A CN 105702653 A CN105702653 A CN 105702653A CN 201510929195 A CN201510929195 A CN 201510929195A CN 105702653 A CN105702653 A CN 105702653A
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dielectric
strong electric
contact piece
reliable
electric contact
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CN201510929195.2A
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CN105702653B (zh
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H·伯克
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Infineon Technologies North America Corp
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Infineon Technologies North America Corp
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Abstract

本申请涉及可靠且强健的电接触件。在一个实施方式中，可靠且强健的电接触件包括从位于有源裸片的表面上方的第一金属层图案化而成的接触焊盘以及位于接触焊盘上方的多个电介质岛。电介质岛通过形成在电介质岛之间和形成在电介质岛上方的第二金属层的对应部分而相互隔开。接触焊盘、电介质岛和第二金属层提供可靠且强健的电接触件。

Description

可靠且强健的电接触件
相关申请的交叉引用
本申请要求2014年12月15日提交的标题为“ReliableandRobustWireBondingOverGateBusonaDLMStructure”的第62/092,155号临时申请的优先权和权益。在此通过参考将该临时申请的公开内容全部并入本申请中。
技术领域
本申请涉及半导体领域，更具体地涉及可靠且强健的电接触件。
背景技术
在各种应用中使用垂直功率晶体管，诸如基于IV族的沟槽型场效应晶体管(沟槽FET)。例如，基于硅的沟槽金属氧化物半导体FET(沟槽MOSFET)可用于实施功率转换器，诸如同步整流器或者直流(DC)至DC功率转换器。
双层金属(DLM)沟槽MOSFET结构使用两个至少部分重叠的金属层以提供源极接触件和栅极接触件，从而增加器件的有源区域而不增加器件尺寸。在传统的DLM结构中，连续的金属间电介质通常夹置在重叠的金属层之间并用于使源极接触件和栅极接触件相互隔离。然而，例如由于键合接线附接至源极接触件引起的应力会导致断裂穿过连续的金属间电介质层的部分而传播。这种金属间电介质的断裂会不期望地在源极接触件和栅极接触件之间产生短路。
发明内容
本公开涉及一种可靠且强健的电接触件，基本如图中至少一幅图所示和/或如结合图中至少一幅图所述那样，并且如权利要求中所阐述那样。
附图说明
图1是示出根据一个实施方式的用于制造可靠且强健的电接触件的示例性方法的流程图。
图2A示出了根据一个实施方式的执行根据图1的示例性流程图的初始动作的结果的截面图。
图2B示出了根据一个实施方式的执行根据图1的示例性流程图的后续动作的结果的截面图。
图2C示出了根据一个实施方式的图2B所示截面中示出的结构的顶视图。
图2D示出了根据一个实施方式的执行根据图1的示例性流程图的后续动作的结果的截面图。
图2E示出了根据一个实施方式的执行根据图1的示例性流程图的后续动作的结果的截面图。
图2F示出了根据一个实施方式的图2E的截面图中示出的结构的顶视图。
图2G示出了根据一个实施方式的执行根据图1的示例性流程图的后续动作的结果的截面图。
图2H示出了根据一个实施方式的执行根据图1的示例性流程图的最终动作的结果的截面图。
具体实施方式
以下描述包含关于本公开的实施方式的具体信息。本领域技术人员将意识到，本公开可以以与本文具体讨论的不同方式来实施。本申请中的附图及其随附的详细描述仅仅涉及示例性的实施方式。除非另有指定，否则图中类似或对应的元件可以通过类似或相应的参考标号来表示。此外，本申请的附图和说明一般不按比例，并且不旨在对应于实际的相对尺寸。
如上所述，在各种应用中使用垂直功率晶体管，诸如基于IV族的沟槽型场效应晶体管(沟槽FET)。例如，基于硅的沟槽金属氧化物半导体FET(沟槽MOSFET)可用于实施功率转换器，诸如同步整流器或者直流(DC)至DC功率转换器。
进一步如上所述，双层金属(DLM)沟槽MOSFET结构使用两个至少部分重叠的金属层以提供源极接触件和栅极接触件，从而增加器件的有源区域而不增加器件尺寸。在传统的DLM结构中，连续的金属间电介质通常被夹置在重叠的金属层之间并用于使源极接触件和栅极接触件相互隔离。然而，例如由于键合接线附接至源极接触件引起的应力会导致断裂穿过连续的金属间电介质层的部分而传播。这种金属间电介质的断裂会不期望地在源极接触件和栅极接触件之间产生短路。
本申请公开了一种可靠且强健的电接触件，其被设计为避免与传统DLM结构相关联的缺陷。根据本申请中描述的示例性实施方式，这种电接触件包括从位于有源裸片的表面上方的第一金属层图案化而成的接触焊盘。多个电介质岛位于接触焊盘上方，电介质岛通过形成在电介质岛之间和形成在电介质岛上方的第二金属层的对应部分而相互隔开。从第一金属层图案化而成的接触焊盘、电介质岛和第二金属层提供了可靠且强健的电接触件。
图1示出了用于制造可靠且强健的电接触件的示例性方法的流程图100。对有源裸片的一部分执行由流程图100描述的示例性方法，其可以被实施以提供功率晶体管(诸如IV族或III-V族晶体管)或集成电路(IC)。
参照图2A至图2H，这些附图所示的结构201-206示出了根据一个实施方式的执行流程图100的方法的结果。例如，图2A的截面图所示的结构201表示有源裸片210，该有源裸片210具有位于表面222上方的第一金属层220(动作101)。图2B的截面图和图2C的顶视图所示的结构202示出了从第一金属层220图案化而成的接触焊盘234(动作102)。图2D的截面图所示的结构203示出了电介质层250形成在接触焊盘234上方(动作103)，等等。
参照流程图100，在图1中结合图2A，流程图100开始于提供有源裸片210，该有源裸片210具有位于有源裸片210的表面222上方的第一金属层220(动作101)。如图2A的截面图所示，有源裸片210包括位于有源裸片210的底面处的重掺杂N型漏极212以及位于重掺杂N型漏极212上方的N型漂移区214。此外，有源裸片210包括位于N型漂移区214上方的P型本体区216以及位于P型本体区216上方的重掺杂P型本体扩散层218。此外在图2A中示出了电介质部分224和第一金属层220，它们均被示出位于有源裸片210的表面222上方。
使用本领域常用的任何材料和任何技术来形成电介质部分224。例如，电介质部分224可以由形成在有源裸片210的表面222上方的电介质层诸如钝化层图案化而成。电介质部分224例如可以由氮化硅(Si3N4)或二氧化硅(SiO2)形成。
例如，第一金属层220可以是铝(Al)层，或者可以由铝合金形成，诸如铝-硅(Al-Si)或铝-硅-铜(Al-Si-Cu)。在一些实施方式中，第一金属层220可以是相对较薄的金属层，诸如厚度在大约1微米至大约2微米(0.5μm-2.5μm)的范围内。然而，在其他实施方式中，金属层220可具有多达近似10.0μm以上的厚度。
移至图2B和图2C，继续参照流程图100，在图1中，流程图100继续从第一金属层220图案化接触焊盘(动作102)。图2B示出了包括从第一金属层220图案化而成的接触焊盘234的结构202的截面图，而图2C示出了结构202的顶视图，透视线2B-2B对应于图2B所示的截面。从图2C明显看出，图2B所示的截面图在重掺杂P型源极扩散层218内查看，并且平行于重掺杂N型源极区域244以及平行于包括对应栅电极246和栅极电介质248的栅极沟槽240。此外，图2C中示出了栅极焊盘236以及位于电介质部分224上方且基本垂直于图2B所示截面图而定向的栅极总线238。
注意，通过参照本申请的各附图，图2A-图2H中由相同参考标号表示的部件分别相互对应并且可以共享它们所具有的任何特性。换句话说，图2C中包括栅极沟槽240、重掺杂N型源极区域244和重掺杂P型本体扩散层218的有源裸片210对应于图2A和图2B中包括重掺杂N型漏极212、N型漂移区214、P型本体区216和重掺杂P型本体扩散层218的有源裸片210，并且可以共享本申请的对应部件所属的任何特性。
此外，图2C中的接触焊盘234、栅极总线238和电介质部分224分别对应于图2B中的接触焊盘234和栅极总线238以及图2A和图2B中的电介质部分224。如上所述，电介质部分224可以由形成在有源裸片210的表面222上方的电介质层诸如钝化层图案化而成。因此，还应该注意，尽管从图2A、图2B或图2C所示的角度中没有看出，但电介质部分224被图案化为位于栅极沟槽240上方，以使栅电极246与第一金属层222电隔离。
例如，有源裸片210可以使用基于IV族的衬底实施，诸如硅(Si)衬底或碳化硅(SiC)衬底。此外，在一些实施方式中，有源裸片210可以包括形成在外延硅层中的N型漂移区214和P型本体区216。例如，这种外延硅层的形成可以通过本领域已知的任何适当方法来进行，诸如化学气相沉积(CVD)或分子束外延(MBE)。然而，更一般地，N型漂移区214和P型本体区216可以以包括在有源裸片210中的任何适当的元素或化合物半导体层来形成。
因此，在其他实施方式中，N型漂移区214和P型本体区216不需要通过外延生长形成，和/或不需要由硅形成。例如，在一个可选实施方式中，N型漂移区214和P型本体区216可形成在有源裸片210的浮置区硅层中。在其他实施方式中，N型漂移区214和P型本体区216可形成在应变或非应变锗层(被形成为有源裸片210的一部分)中。
P型本体区216和重掺杂P型本体扩散层218可通过注入和热扩散形成。例如，硼(B)掺杂物可被注入到有源裸片210中并扩散到P型本体区216和重掺杂P型本体扩散层218中。参照图2C，重掺杂N型源极区域244可类似地通过适当N型掺杂物在有源裸片210中的注入和热扩散来形成。例如，这种适当的N型掺杂物可包括砷(As)或磷(P)。
可使用本领域常用的任何导电材料来形成栅电极246。例如，栅电极246可由掺杂多晶硅或金属形成。栅极电介质248使栅电极340与重掺杂N型源极区域244绝缘，该栅极电介质248可以使用本领域常用的任何材料和任何技术来形成。例如，栅极电介质248可以由SiO2形成，并且可以被沉积或热生长以产生栅极电介质248。
注意，尽管在图2A-图2C以及后续的图2D-图2H中所示的实施方式示出了有源裸片210提供具有N型漏极212、N型漂移区214、P型本体区216和N型源极区244的n沟道垂直功率FET，但这仅仅是示例性的。在其他实施方式中，可以反转所描述的极性，使得有源裸片210可提供具有P型漏极、P型漂移区、N型本体区和P型源极区的p沟道器件。
进一步注意，为了描述的方便和简明，本发明的原理在一些情况下将通过参照基于硅的垂直功率FET的具体实施方式来描述。然而，应该强调的是，这种实施方式仅仅是示例性的，本文公开的发明原理可广泛用于各种有源裸片。例如，一般对应于有源裸片210的有源裸片可用于实施IC，或者实施被配置为垂直或横向功率器件的基于其他IV族材料或III-V族半导体的功率晶体管。作为具体实例，对应于有源裸片210的有源裸片可包括基于III-氮化物或其他III-V族的异质结构FET(HFET)，诸如高电子迁移率晶体管(HEMT)。
如本文所使用的，术语“III-V族”表示包括至少一种III族元素和至少一种V族元件的化合物半导体。通过实例，III-V族半导体可以采用III-氮化物半导体的形式，其包括氮化物和至少一种III族元素。例如，III-氮化物功率FET可使用氮化镓(GaN)来制造，其中III族元素包括一些或大量锗，但是还可以包括除锗之外的其他III族元素。
再次参照图2A至图2C，第一金属层220(其在图2A中可以为毯式金属层，诸如Al、Al-Si或Al-Si-Cu毯式层)被图案化以产生接触焊盘234以及栅极焊盘236和栅极总线238。因此，根据本示例性实施方式，接触焊盘234形成源极接触件的一部分，而栅极总线238形成用于有源裸片210提供的垂直功率FET的栅极接触件的一部分。
现在移动到图2D，继续参照流程图100，在图1中，流程图100继续在接触焊盘234上方形成电介质层250(动作103)。如结构203所示，电介质层250可形成为覆盖栅极总线238和接触焊盘234的毯式层。电介质层250可以是适合用于半导体制造的任何层间电介质。例如，电介质层250可以是SiO2、Si3N4或旋涂玻璃层。此外，在一些实施方式中，电介质层250可以是包括多于一种的电介质材料的多层电介质叠层。
参照图2E和图2F，流程图100继续图案化电介质层250以形成电介质岛254(例如，电介质岛254a、254b、254c和254d)，电介质岛254在接触焊盘234上通过空隙256(例如，空隙256a-b和256c-d)相互隔开(动作104)。图2E示出了包括电介质岛254a、254b、254c和254d以及空隙256a-b和256c-d的结构204的截面图，而图2F示出了结构204的顶视图，其中透视线2E-2E对应于图2E所示的截面。
除电介质岛254之外，图案化电介质层250还使得基本连续的电介质板252形成在栅极总线238上方并环绕栅极总线238。如图2E和图2F所示，形成在栅极总线238上方并环绕栅极总线238的电介质板252与电介质岛254隔开，即与电介质岛254不连续。
如图2F进一步示出，每个电介质岛254均具有宽度264并且通过对应的空隙256(均具有宽度266)与每个相邻的电介质岛隔开。因此，参照图2E，电介质岛254a具有宽度264并通过具有宽度266的空隙256a-b与电介质岛254b隔开，电介质岛254c具有宽度264并通过具有宽度266的空隙256c-d与电介质岛254d隔开，等等。电介质岛254的宽度264例如可以近似为2.0μm至近似3.0μm，而空隙256的宽度266可以在近似0.5μm至近似10.0μm的范围内。
如上所述，从中图案化电介质岛254的电介质层250可以是基本均匀的电介质材料(诸如SiO2)的单层，或者可以实施为多层电介质叠层。从而，每个电介质岛254均可以由单种电介质材料(例如，SiO2)形成，或者可以形成为包括至少两个子层(由不同电介质材料形成)的电介质叠层。注意，尽管图2E和图2F所示的示例性实施方式将电介质岛254示为当从上面看时基本为方形瓦片，但在其他实施方式中，电介质岛254可具有基本任何期望的形状。
移至图2G，流程图100继续在电介质岛254之间和在电介质岛254上方形成第二金属层258，第二金属层258基本填充隔开电介质岛254的空隙256(动作105)。如图2G的结构205所示，第二金属层258的部分268将电介质岛254隔开，并且能够使第二金属层258与接触焊盘234电接触。如图2G进一步示出的，第二金属层258也形成在栅极总线238上方，但是通过电介质板252与栅极总线238电隔离。
在一些实施方式中，有利地或期望第二金属层258由与第一金属层220相同的材料形成。在这些实施方式中，例如，第二金属层258和第一金属层220可以由Al形成或相同的铝合金(诸如Al-Si或Al-Si-Cu)形成。然而，在其他实施方式中，有利地或期望由与用于形成第一金属层220不同的金属形成第二金属层258。在一些实施方式中，例如，第二金属层258可以是铜(Cu)层，诸如经沉积或电镀的Cu层。此外，除功率FET之外，在对应于有源裸片210的有源裸片提供IC的实施方式中，第二金属层258可以是钨(W)层。
注意，在一些实施方式中，第二金属层258可以被形成为远大于第一金属层220的厚度。例如，如上所述，在第一金属层220可形成近似1.0μm至近似2.0μm的厚度的同时，第二金属层258可以具有近似5.0μm至近似10.0μm的范围内的示例性厚度。
继续到图2H，流程图100可继续将一个或多个电连接件270附接至电介质岛254上方的第二金属层258(动作106)。如结构206所示，电连接件270被示为用于示例性目的的键合接线。然而，更一般地，电连接件270可以对应于任何导电夹、导电带或导电条以及图2H所示的键合接线。
由将电连接件270附接至电介质岛254上方的第二金属层258所引起的应力会使得一个或多个电介质岛254断裂。然而，与连续的金属间电介质层形成在接触焊盘234和栅极总线238上方的传统结构相比，根据本申请公开的实施方式，电介质岛254与形成在栅极总线238上方并环绕栅极总线238的电介质板252隔开。结果，防止由于电连接件270的附接而形成在电介质岛254中的断裂传播至电介质板252，从而保持栅极总线238与接触焊盘234和第二金属层258电隔离。从而，接触焊盘234、电介质岛254和第二金属层258提供用于有源裸片210的可靠且强健的电接触件。
根据图2A-图2H所示的示例性实施方式，有源裸片210提供了IV族功率FET，并且电连接件270通过接触焊盘234以及形成在电介质岛254之间和形成在电介质岛254上方的第二金属层258而耦合至重掺杂P型本体扩散层218和重掺杂N型源极区域244。因此，在图2A-图2H所示的示例性实施方式中，接触焊盘234、电介质岛254和第二金属层258为有源裸片210的IV族功率FET提供了可靠且强健的源极接触件。然而，本领域技术人员应该意识到，接触焊盘234、电介质岛254和第二金属层258还可以容易地被适配以为IV族功率FET提供可靠且强健的漏极接触件。
如上所述，在其他实施方式中，对应于有源裸片210的有源裸片可以提供III-V族HFET。在这些实施方式中，对应于接触焊盘234、电介质岛254和第二金属层258的特征可以为III-V族HFET提供可靠且强健的源极接触件和/或漏极接触件。此外，在对应于有源裸片210的有源裸片用于提供IC的实施方式中，对应于接触焊盘234、电介质岛254和第二金属层258的特征可以提供IC的可靠且强健的键合焊盘。
根据上面的描述，各种技术可用于实施本文描述的概念而不背离其概念的范围。此外，虽然参照特定实施方式描述了该概念，但本领域技术人员应该意识到，在不背离这些概念的精神的情况下可以对形式和细节做出改变。如此，所描述的实施方式被认为是示例性的而非限制性的。还应该理解，本申请不限于本文描述的特定实施方式，而是在不背离本公开的范围的情况下可进行许多再配置、修改和替换。

Claims (20)

1.一种可靠且强健的电接触件，包括：
接触焊盘，从位于有源裸片的表面上方的第一金属层图案化而成；
多个电介质岛，位于所述接触焊盘上方，所述多个电介质岛通过形成在所述多个电介质岛之间和形成在所述多个电介质岛上方的第二金属层的对应部分而相互隔开；
其中，所述接触焊盘、所述多个电介质岛和所述第二金属层提供所述可靠且强健的电接触件。
2.根据权利要求1所述的可靠且强健的电接触件，其中，所述有源裸片包括IV族功率场效应晶体管(FET)，并且所述强健的电接触件是所述IV族功率FET的源极接触件和漏极接触件中的一个。
3.根据权利要求1所述的可靠且强健的电接触件，其中，所述有源裸片包括集成电路(IC)，并且所述强健的电接触件提供所述IC的键合焊盘。
4.根据权利要求1所述的可靠且强健的电接触件，其中，所述有源裸片包括III-V族异质结构FET(HFET)，并且所述强健的电接触件是所述III-V族HFET的源极接触件和漏极接触件中的一个。
5.根据权利要求1所述的可靠且强健的电接触件，还包括：至少一个电连接件，在所述电介质岛上方附接至所述第二金属层，所述至少一个电连接件选自包括夹、带、条和键合接线的组。
6.根据权利要求1所述的可靠且强健的电接触件，其中，所述第一金属层和所述第二金属层中的至少一个包括铝。
7.根据权利要求1所述的可靠且强健的电接触件，其中，所述第一金属层和所述第二金属层中的至少一个包括铜。
8.根据权利要求1所述的可靠且强健的电接触件，其中，所述第二金属层包括钨。
9.根据权利要求1所述的可靠且强健的电接触件，其中，每一个所述电介质岛均包括氧化硅。
10.根据权利要求1所述的可靠且强健的电接触件，其中，每一个所述电介质岛均形成为包括由不同电介质材料形成的至少两个子层的电介质叠层。
11.一种用于制造可靠且强健的电接触件的方法，所述方法包括：
从位于有源裸片的表面上方的第一金属层图案化而成接触焊盘；
在所述接触焊盘上方形成电介质层；
图案化所述电介质层以形成通过对应空隙而相互隔开的多个电介质岛；
在所述多个电介质岛之间和在所述多个电介质岛上方形成第二金属层以基本填充所述对应空隙；
其中，所述接触焊盘、所述多个电介质岛和所述第二金属层提供所述可靠且强健的电接触件。
12.根据权利要求11所述的方法，其中，所述有源裸片包括IV族功率场效应晶体管(FET)，并且所述强健的电接触件是所述IV族功率FET的源极接触件和漏极接触件中的一个。
13.根据权利要求11所述的方法，其中，所述有源裸片包括集成电路(IC)，并且所述强健的电接触件提供所述IC的键合焊盘。
14.根据权利要求11所述的方法，其中，所述有源裸片包括III-V族异质结构FET(HFET)，并且所述强健的电接触件是所述III-V族HFET的源极接触件和漏极接触件中的一个。
15.根据权利要求11所述的方法，还包括：在所述电介质岛上方将至少一个电连接件附接至所述第二金属层，所述至少一个电连接件是选自包括夹、带、条和键合接线的组。
16.根据权利要求11所述的方法，其中，所述第一金属层和所述第二金属层中的至少一个包括铝。
17.根据权利要求11所述的方法，其中，所述第一金属层和所述第二金属层中的至少一个包括铜。
18.根据权利要求11所述的方法，其中，所述第二金属层包括钨。
19.根据权利要求11所述的方法，其中，每一个所述电介质岛均包括氧化硅。
20.根据权利要求11所述的方法，其中，每一个所述电介质岛均形成为包括由不同电介质材料形成的至少两个子层的电介质叠层。
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