CN103065984B - 用于半导体器件的封装方法 - Google Patents

用于半导体器件的封装方法 Download PDF

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Publication number
CN103065984B
CN103065984B CN201210055766.0A CN201210055766A CN103065984B CN 103065984 B CN103065984 B CN 103065984B CN 201210055766 A CN201210055766 A CN 201210055766A CN 103065984 B CN103065984 B CN 103065984B
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packaging
base plate
workpiece
multiple base
tube core
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CN103065984A (zh
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黄贵伟
林威宏
林志伟
林俊成
陈孟泽
郑明达
刘重希
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

发明了用于半导体器件的封装方法。在一个实施例中，封装半导体器件的方法包括：提供包括多个封装基板的工件。去除多个封装基板之间的工件的一部分。管芯附接至多个封装基板的每一个。

Description

用于半导体器件的封装方法
技术领域
本发明一般地涉及半导体领域，更具体地来说，涉及一种半导体器件的封装方法。
背景技术
半导体器件用于各种电子应用，诸如作为实例的个人计算机、手机、数码相机和其他电子设备。通常通过在半导体基板的上方顺序沉积绝缘层或介电层、导电层和半导体材料层以及使用光刻对各种材料层进行图案化来形成其上的电路部件和元件来制造半导体器件。
半导体工业通过最小部件尺寸的持续减小来不断提高各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，这允许更多的部件集成到给定面积中。在一些应用中，这些减小的电子部件还要求比过去的封装件利用更小面积的较小封装件。
一种用于半导体的较小类型的封装为倒装芯片(FC)球栅阵列(BGA)封装，其中，半导体管芯正面向下放置在基板上并使用微凸块接合至基板。基板具有将管芯上的微凸块连接至具有较大占位面积的基板上的接触焊盘的配线。焊球阵列形成在基板的相反面上并用于将封装管芯电连接至端部应用。
然而，一些FC-BGA封装趋于显示出弯曲，其中，由于诸如在回流焊接工艺中的温度应力在加工期间发生基板的翘曲，该回流焊接工艺可以具有大约240至260摄氏度的温度范围。翘曲源于封装件和管芯的各种材料层和部件中的热膨胀系数(CTE)失配。例如，基板膨胀通常大于管芯的膨胀。这种翘曲和弯曲可能会引起可靠性问题、较低的组装成品率、接合破坏或短路以及微凸块的虚焊。例如，扭曲状态对于薄核心封装基板来说存在更多问题，并且可以从室温的凸形翘曲变动到高温的凹形翘曲。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种封装半导体器件的方法，所述方法包括：提供工件，所述工件包括多个封装基板；去除所述多个封装基板之间的所述工件的一部分；以及将管芯附接至所述多个封装基板的每一个。
在该方法中，附接所述管芯包括：提供包括设置其表面上的多个凸块的管芯；以及将所述管芯的表面上的所述多个凸块附接至所述多个封装基板的每一个。
在该方法中，提供所述管芯包括：提供设置在其上的所述多个凸块包括焊料的管芯。
该方法包括：实施焊接工艺、回流焊接工艺或热压接合工艺。
在该方法中，去除所述工件的一部分包括：去除大约20μm或者更多的所述工件。
在该方法中，去除所述工件的一部分包括：去除所述工件接近所述管芯的顶部、去除所述工件与所述管芯相对面上的底部或者去除所述工件接近所述管芯的顶部和去除所述工件与所述管芯相对面上的底部。
该方法还包括：在所述管芯的下方形成底部填充材料；以及在所述管芯和所述底部填充材料的上方形成模塑料。
根据本发明的另一方面，提供了一种封装半导体器件的方法，所述方法包括：提供工件，所述工件包括多个封装基板；在所述工件的上方形成介电材料；在所述介电材料的上方形成焊接掩模；至少去除所述多个封装基板之间的所述焊接掩模；将管芯附接至所述多个封装基板的每一个，所述管芯包括设置在其上的多个凸块；以及将所述管芯的所述多个凸块电连接至所述多个封装基板。
该方法还包括：去除所述多个封装基板之间的所述介电材料的至少一部分。
在该方法中，至少去除所述焊接掩模包括：至少去除所述工件的分离区域中的所述焊接掩模。
在该方法中，提供所述工件包括：提供所述多个封装基板包括多个倒装芯片球栅阵列(FC-BGA)封装件、倒装芯片芯片级封装件(FC-CSP)、接点栅格阵列(LGA)封装件、或迹线上接合(BOT)封装件的工件。
在该方法中，提供所述工件包括：提供所述多个封装基板包括设置在其表面上的多个接触焊盘的工件，还包括将多个焊球连接至所述多个接触焊盘。
在该方法中，至少去除所述焊接掩模包括：使用激光、管芯切割或光刻法。
根据本发明的又一方面，提供了一种封装半导体器件的方法，所述方法包括：提供包括多个封装基板的工件；在所述工件的上方形成介电材料；在所述介电材料的上方形成焊接掩模；去除所述多个封装基板之间的分离区域上的所述多个封装基板之间的所述焊接掩模和所述介电材料的至少一部分；将管芯附接至所述多个封装基板的每一个，所述管芯包括设置在其上的多个凸块，所述多个凸块包括焊料；使用回流焊接工艺对所述管芯的所述多个凸块的焊料进行回流；在所述管芯下方形成底部填充材料；在所述管芯、所述底部填充材料和所述多个封装基板的上方形成模塑料；以及切割所述多个封装基板。
在该方法中，附接所述管芯包括附接集成电路管芯，其中，设置在其上的所述多个凸块包括多个微凸块。
在该方法中，去除所述多个封装基板之间的分离区域上的所述多个封装基板之间的所述焊接掩模和所述介电材料的至少一部分包括：去除所述工件的从顶部向下观察的x轴方向、y轴方向或者x轴方向和y轴方向上的所述焊接掩模和所述介电材料的至少一部分。
在该方法中，形成所述介电材料包括：形成具有大约100μm或者更小的厚度的介电材料。
在该方法中，形成所述焊接掩模包括：形成具有大约10μm至30μm的厚度的焊接掩模。
在该方法中，去除所述介电材料的至少一部分包括：从所述多个封装基板之间去除所有介电材料。
在该方法中，去除所述多个封装基板之间的所述焊接掩模和所述介电材料的至少一部分减少或防止所述回流焊接工艺期间所述多个封装基板或管芯的翘曲。
附图说明
为了更完整地理解本发明及其优点，现在将结合附图所进行以下描述作为参考，其中：
图1至图3a示出了根据本发明实施例的封装集成电路管芯的方法的截面图，其中，在管芯附接至封装基板之前去除工件的顶部；
图3b示出了去除工件的底部的实施例的截面图；
图4示出了图3a的管芯附接至其的工件的俯视图，示出了去除工件顶部的管芯之间的分离区域；
图5示出了集成电路管芯108更加详细的截面图；
图6至图9示出了根据另一实施例的封装集成电路管芯的方法的截面图和透视图(图7)；
图10和图11示出了根据又一实施例的封装集成电路管芯的方法的截面图；以及
图12是示出根据本文所描述实施例的封装半导体器件的方法的流程图。
除非另有指定，不同附图中的对应标号或符号通常是指对应部件。绘制附图以清楚地示出实施例的相关方面而不必须按比例绘制。
具体实施方式
以下详细讨论本发明的实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境下实现的可应用的发明概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制本发明的范围。
本发明的实施例通常涉及半导体器件，更具体地，涉及集成电路的封装。公开了新颖的封装半导体器件，其中，封装基板在附接管芯之前在周围区域中减薄，这减少或消除了封装工艺(诸如热循环和回流焊接工艺)期间的翘曲。
图1至图3a示出了根据本发明实施例的封装集成电路管芯108的方法的截面图，其中，在管芯108附接至封装基板104之前去除工件100的顶部。首先，如图1所示，提供工件100。作为实例，工件100可以包括具有大约0.1μm至大约0.5μm的厚度的陶瓷、塑料和/或有机材料，但是可选地，工件100可以包括其他材料和尺寸。工件100包括多个封装基板104用于集成电路管芯108。如图所示，分离区域102设置在每个封装基板104区域之间。分离区域102包括封装基板104将在封装工艺的结束时切割或彼此分离的区域。例如，在一些实施例中，分离区域102可以包括切割区域或划线。作为实例，工件100的封装基板104可以包括用于倒装芯片球栅阵列(FC-BGA)封装、倒装芯片芯片级封装(FC-CSP)、接点栅格阵列(landgridarray，LGA)封装或迹线上接合(bond-on-trace，BOT)封装的基板，但是可选地，还可以使用其他类型的封装基板104。
如图2所示，在封装基板104之间去除工件100的顶部。接近分离区域102或在分离区域102内去除工件100的顶部。去除的顶部可以包括凹进区域106，该凹进区域具有包括在工件100的顶面下方的尺寸d1的深度和包括尺寸d2的宽度。例如，尺寸d1可以包括大约100μm或者更小，以及尺寸d2可以包括大约20μm或者更大，但是可选地尺寸d1和d2还可以包括其他值。
在一些实施例中，去除工件100的顶部以使用激光或管芯切割创建凹进区域106。类似于没有完全穿过工件100进行划线(scoring)的切割工艺，使用这种切割设备来实施工件100的顶部的部分切割或划线。可选地，例如，在蚀刻掉工件100的顶部的同时通过沉积光刻胶层(或硬掩模和光刻胶的组合)、图案化光刻胶层、然后将光刻胶层用作蚀刻掩模来使用光刻工艺去除工件100的顶部。
接下来，参照图3a，提供多个集成电路管芯108。集成电路管芯108可以包括形成在其上的多个电路和电子部件(未示出)。例如，可以半导体晶圆(未示出)上先前制造集成电路管芯108，该半导体晶圆包括诸如硅或其他半导体的半导体材料，并且在划线(类似于工件100的分离区域102)上进行切割以形成多个单个管芯108。在俯视图中，集成电路管芯108可以包括正方形或长方形的形状(在图3a中未示出，参见图4)。例如，集成电路管芯108还在本文被称为管芯或半导体器件。根据本发明的实施例，多个管芯108连接或附接至工件100的多个封装基板104。
在图1至图3a所示的实施例中，在封装基板之间去除工件100的顶部。可选地，在其他实施例中，在附接管芯108之前，如图3b所示，可以在创建凹进区域106’的分离区域102中的封装基板104之间去除工件100的底部。例如，可以使用与图1至图3a的实施例所描述的类似技术并具有类似尺寸来去除工件100的底部。
在其他实施例中，可以去除工件100的底部和顶部，如图3b在的虚拟件(phantom)所示，在工件的顶部中形成凹进区域106，并且作为另一实例，在工件100的底部中形成凹进区域106’。
图4示出了图3a的工件100的俯视图。如图所示，工件100在俯视图中基本上可以为矩形，或者工件100可以包括其他形状。多个管芯108连接至以工件100上的列和行的阵列状结构进行配置的多个封装基板104。包括凹进区域106(和/或106’)的分离区域102位于封装基板104的周围接近管芯108的边缘处的封装基板104之间。如图所示，在一些实施例中，例如，封装基板104可以以组进行配置，以在工件100上提供未使用区域，其中，在回流焊接工艺期间可以实施夹具(未示出)以利于管芯108的定位。
在一些实施例中，在工件100的俯视图和/或仰视图中的x轴方向以及y轴方向上，可以在位于工件100上的分离区域102中工件100的顶部和/或底部凹进。在其他实施例中，如102a所示，可以仅在x轴方向上的分离区域102中使工件100的顶部和/或底部凹进。在又一些实施例中，如102b所示，可以仅在y轴方向上的分离区域102中使工件100的顶部和/或底部凹进。例如，还可以在管芯108附接至工件100之前，实施沿着工件100的顶部和/或底部上的分离区域102a和/或102b在一些x轴和y轴方向上的去除组合。
在一些实施例中，可以在x轴方向分离区域102a中去除工件100的顶部，以及在y轴方向分离区域102b中去除工件100的底部。在其他实施例中，作为另一实例，可以在y轴方向分离区域102b中去除工件100的顶部，以及在x轴方向分离区域102a中去除工件100的底部。
在管芯108附接至封装基板104之前，去除工件100的顶部和/或底部以在分离区域102中形成凹进区域106和/或106’的优点在于，后续工艺期间减小了机械应力，其中，工件100暴露给诸如可能要求高温的热工艺。凹进区域106和/或106’减少或消除了翘曲，提供了翘曲状态控制。
图5至图9示出了根据另一实施例的封装集成电路电路108的方法。用于描述图1、图2、图3a、图3b和图4的类似标号用于图5至图9(以及图10至图12)中的各个元件以避免重复，图5至图9所示的每个参考标号在本文中不再进行详细描述。
图5示出了集成电路管芯108更加详细的截面图。在图5至图9(以及还在图10和图11)中仅示出了一个管芯108；然而，如先前实施例所描述和示出的，在工件100的表面封装多个集成电路管芯108。集成电路管芯108包括形成在其表面上的多个凸块110。在一些实施例中，例如，凸块110包括微凸块。凸块110形成在管芯108的外围区域中并且可以在外围区域中的一行或多行中进行配置。作为实例，沿着管芯边缘或角部，在图5至图9中的集成电路管芯108的每一侧上的三行中配置凸块110。凸块110可以可选地以其他图案进行配置并且可以位于其他位置。其他实施例可以利用例如沿着管芯的内部的凸块结构的方面。提供凸块结构的放置仅仅是为了示意性的目的，凸块结构的具体位置和图案可以改变并且作为实例可以包括凸块阵列、管芯108的中间区域中凸块线或者交错凸块。提供所示管芯108和凸块110的尺寸和放置仅仅是参考的目的，而不用于表示实际尺寸或实际相对尺寸。
每个凸块110都可以包括金属柱112(可以包括铜、铜合金或其他金属)以及形成在金属柱112上方的焊料114。凸块110可以可选地包括其他材料。金属柱112可以由任何适当的导电材料形成，包括Cu、Ni、Pt、Al、它们的组合，并且可以通过任何数量的适当技术来形成，包括PVD、CVD、电化学沉积(ECD)、分子束外延(MBE)、原子层沉积(ALD)、电镀等。可以在金属柱112和焊料114之间形成任选的导电覆盖层(未示出)。例如，在金属柱112由铜形成的实施例中，可以预期由镍形成的导电覆盖层。还可以使用诸如Pt、Au、Ag、它们的组合等的其他材料。焊料114形成在金属柱112和/或任选导电覆盖层的上方。作为实例，焊料114材料可以包括：SnPb、高Pb材料、Sn基焊料、无铅焊料或其他适当的导电材料。例如，凸块110可以包括大约50μm或者以下的高度(图中的垂直方向)和大约35μm的宽度，但是凸块还可以包括其他尺寸。
管芯108包括工件，该工件包括硅或其他半导体材料。在工件的上方形成绝缘材料和导线(未示出)。例如，导线可以电连接在管芯108的凸块110和工件的电子部件之间。例如，在一些实施例中，导线可以包括铝焊盘，但是还可以使用其他金属。焊球下金属化(underballmetallization，UBM)结构(未示出)可以任选地形成在管芯108的导线上方。
如图6的截面图所示，提供包括多个封装基板104的工件100。在图6至图9中仅示出了一个封装基板104；如先前实施例所示，在工件100的表面上方形成多个封装基板104。如参照图1、图2、图3a、图3b和图4所示实施例所描述的，工件100包括凹进区域106，该凹进区域包括部分划线或去除的分离区域102中顶面的一部分。注意，在图5至图9所示的实施例中，如参照图3b所示和描述的，还可以可选地或附加地去除工件100的底部，以形成凹进区域106’(在图6中未示出)。
多个接合焊盘116设置在封装基板104的顶面上。接合焊盘116用于连接至集成电路管芯108的凸块110并包括类似图案。多个接触焊盘118设置在接近分离区域102的封装基板104的底面上。接触焊盘118用于连接多个焊球136(图6中未示出，参见图11)。
如图7的透视图所示，管芯108附接至封装基板104，并且可以执行焊料回流工艺以回流凸块110的焊料114并将管芯108电连接至封装基板104。使用粘合剂或者通过使用夹具(未示出)来在焊料回流工艺期间将管芯108定位于适当位置，管芯108可以附接至封装基板104，在这种情况下，焊料114还用作与封装基板104的机械附接。作为实例，集成电路管芯108的凸块110可以使用焊接工艺、回流焊接工艺和/或热压接合工艺连接至封装基板104的接合焊盘116。可选地，其他方法可用于将集成电路管芯108电连接至封装基板104。
如图8的截面图所示，任选的底部填充材料120可形成在集成电路管芯108的下方。作为实例，底部填充材料112可以包括填充物、环氧树脂、硬化剂或多层或者它们的组合，但是可选地，底部填充材料120还可以包括其他材料。如图9所示，模塑料122形成在集成电路管芯108、底部填充材料120和封装基板104的上方。例如，模塑料122可以包括环氧树脂、填充物、有机材料或多层或者它们的组合，但是模塑料122还可以包括其他材料。例如，模塑料122可以延伸到集成电路管芯108的顶面上方大约10μm或者以上。在一些实施例中，如果集成电路管芯108较大，则可以使用较大量的模塑料122，以提供用于封装件的更多稳定性。
在一些实施例中，例如，模塑料122可以形成在集成电路管芯108的上方而不包括任选的底部填充材料120。
然后，如图9中的虚线所示，在分离区域102处切割封装管芯138，并且封装管芯138相互分离。在一些实施例中，分离区域102可以设置在工件100的牺牲区域中，其中，在分离工艺期间没有破坏封装管芯138的功能部分。在其他实施例中，牺牲测试电路(未示出)可以形成在分离区域102中，分离区域102在分离封装管芯138的分离工艺期间被破坏。
图10和图11示出了根据本发明又一实施例的封装集成电路管芯108的方法的截面图。在该实施例中示出了工件100和封装基板104的更加详细的示图。在绝缘材料126、124和130内的封装基板104中设置包括配线125、128和134、接触焊盘118以及接合焊盘116的多个电连接。配线125、128和134设置在封装基板104的多个接触焊盘118和多个接合焊盘116之间并且电连接多个接触焊盘118和多个接合焊盘116。例如，电连接可以包括通过光刻形成在封装基板104内的电配线125、128和134的迹线、接触焊盘118以及接合焊盘116。作为实例，电连接可以包括：铜、铝、其他金属或多层或者它们的组合。在一些实施例中，多个电连接可以包括例如接近基板104的表面形成在封装基板104中的再分布层(RDL)(未示出)。RDL可包括配线的扇出区域。集成电路管芯108可以电连接至基板104的RDL。封装基板104可包括连接至RDL的任选UBM结构。例如，任选的UBM可以利于将焊球136(参见图11)连接至封装基板104。
在该实施例中，封装基板104的部分划刻或凹进的区域106(和/或凹进区域106’，未示出；参见图3b)形成在焊接掩模132材料中以及还形成在焊接掩模132材料下方设置的介电材料130的至少一部分中。例如，焊接掩模132材料可以包括通用的焊接掩模材料，诸如聚合物或者不与焊料进行反应的其他介电材料。焊接掩模132可以包括大约10μm至30μm的厚度。作为实例，介电材料130可以包括二氧化硅、氮化硅、低介电常数(k)材料、其他绝缘材料或多层或者它们的组合。介电材料130可以包括大约100μm或者以下的厚度。可选地，封装基板104的焊接掩模132和介电材料130可以包括其他材料和尺寸。
图11示出了焊球136形成在基板104的接触焊盘118上之后的封装半导体器件138的截面图。然后，模塑料122可以形成在封装管芯138的上方，然后可以切割封装管芯138(在图11中未示出，参见图9)。然后，封装半导体器件138可以使用焊球136附接至其他器件、印刷电路板(PCB)或其他端应用。
图12是示出根据本文所描述实施例的封装半导体器件的方法的流程图140。该方法包括提供工件100，工件包括多个封装基板104(步骤142)。在封装基板104之间去除工件100的一部分(步骤144)以在分离区域102中形成凹进区域106。管芯108附接至封装基板104(步骤146)。然后，使用回流焊接工艺(步骤148)或其他方法，以将管芯108电连接至封装基板104。
本发明实施例的优点包括提供了新颖的封装技术，由于在管芯108附接至封装基板104之前的部分去除工件100，因此具有增加的可靠性和更高的产量。由于分离区域102中工件100的部分去除(例如，形成凹进区域106和/或106’)，通过本文所述发明的实施例减少或消除了诸如回流焊接工艺的热应力期间封装基板104和/或管芯108的翘曲和弯曲效应。凹进区域106和/或106’减小了CTE失配和热膨胀，并提供了接合可靠性。减少或最小化凸块110的连接的断裂以及封装的各种材料层(可包括低k介电材料)的分层。在制造和封装工艺流程中可以容易地实施例用于半导体器件的新颖封装方法。
在一个实施例中，封装半导体器件的方法包括：提供工件，工件包括多个封装基板。在多个封装基板之间去除工件的一部分。将管芯附接至多个封装基板的每一个。
在另一实施例中，封装半导体器件的方法包括：提供工件，工件包括多个封装基板；在工件的上方形成介电材料；以及在介电材料的上方形成焊接掩模。该方法包括：至少去除多个封装基板之间的焊接掩模；将管芯附接至多个封装基板的每一个，管芯包括设置在其上的多个凸块；以及将管芯的多个凸块电连接至多个封装基板。
在又一实施例中，封装半导体管芯的方法包括：提供包括多个封装基板的工件；在工件的上方形成介电材料；在介电材料的上方形成焊接掩模；以及去除多个封装基板之间的分离区域上的多个封装基板之间的焊接掩模和介电材料的至少一部分。该方法包括：将管芯附接至多个封装基板的每一个，管芯包括设置在其上的多个凸块，多个凸块包括焊料；以及使用回流焊接工艺对管芯的多个凸块的焊料进行回流。在管芯上形成底部填充材料；在管芯、底部填充材料和多个封装基板的上方形成模塑料。然后，切割多个封装基板。
尽管详细描述了本发明的实施例及其优点，但应该理解，在不背离由所附权利要求定义的发明的主旨和范围的情况下，可以进行各种改变、替换和变化。例如，本领域的技术人员可以容易地理解本文所描述的许多部件、功能、工艺和材料可以被改变同时保持在本发明的范围内。此外，本申请的范围不限于说明书中描述的工艺、机器、制造、物质组成、装置、方法或步骤的特定实施例。本领域的技术人员应该容易地从发明中理解，可以根据发明利用现有或稍后开发的执行与本文所描述对应实施例基本相同的功能或实现基本相同的结果的工艺、机器、制造、物质组成、装置、方法或步骤。因此，所附权利要求用于在它们的范围内包括这些工艺、机器、制造、物质组成、装置、方法或步骤。

Claims (19)

1.一种封装半导体器件的方法，所述方法包括：
提供工件，所述工件包括多个封装基板；
去除所述多个封装基板之间的所述工件的一部分；
将管芯附接至所述多个封装基板的每一个；以及
沿着所述多个封装基板之间的所述工件的去除部分切割所述多个封装基板，
其中，去除所述工件的一部分包括去除所述工件与所述管芯相对面上的底部或者同时去除所述工件接近所述管芯的顶部并去除所述工件与所述管芯相对面上的底部。
2.根据权利要求1所述的方法，其中，附接所述管芯包括：提供包括设置其表面上的多个凸块的管芯；以及将所述管芯的表面上的所述多个凸块附接至所述多个封装基板的每一个。
3.根据权利要求2所述的方法，其中，提供所述管芯包括：提供设置在其上的所述多个凸块包括焊料的管芯。
4.根据权利要求3所述的方法，还包括：实施焊接工艺或热压接合工艺。
5.根据权利要求3所述的方法，其中，去除所述工件的一部分包括：去除20μm或者更多的所述工件。
6.根据权利要求1所述的方法，还包括：在所述管芯的下方形成底部填充材料；以及在所述管芯和所述底部填充材料的上方形成模塑料。
7.一种封装半导体器件的方法，所述方法包括：
提供工件，所述工件包括多个封装基板；
在所述工件的上方形成介电材料；
在所述介电材料的上方形成焊接掩模；
至少去除所述多个封装基板之间的所述焊接掩模；
将管芯附接至所述多个封装基板的每一个，所述管芯包括设置在其上的多个凸块；
将所述管芯的所述多个凸块电连接至所述多个封装基板；以及
沿着所述多个封装基板之间的所述焊接掩膜的去除部分切割所述多个封装基板，
其中，至少去除所述多个封装基板之间的所述焊接掩模包括同时去除所述多个封装基板之间的所述焊接掩模以及所述工件与所述焊接掩模相对面上的底部。
8.根据权利要求7所述的方法，还包括：去除所述多个封装基板之间的所述介电材料的至少一部分。
9.根据权利要求7所述的方法，其中，至少去除所述焊接掩模包括：至少去除所述工件的分离区域中的所述焊接掩模。
10.根据权利要求7所述的方法，其中，提供所述工件包括：提供所述多个封装基板包括多个倒装芯片球栅阵列(FC-BGA)封装件、倒装芯片芯片级封装件(FC-CSP)、接点栅格阵列(LGA)封装件、或迹线上接合(BOT)封装件的工件。
11.根据权利要求7所述的方法，其中，提供所述工件包括：提供所述多个封装基板包括设置在其表面上的多个接触焊盘的工件，还包括将多个焊球连接至所述多个接触焊盘。
12.根据权利要求7所述的方法，其中，至少去除所述焊接掩模包括：使用激光或光刻法。
13.一种封装半导体器件的方法，所述方法包括：
提供包括多个封装基板的工件；
在所述工件的上方形成介电材料；
在所述介电材料的上方形成焊接掩模；
去除所述多个封装基板之间的分离区域上的所述多个封装基板之间的所述焊接掩模和所述介电材料的至少一部分；
将管芯附接至所述多个封装基板的每一个，所述管芯包括设置在其上的多个凸块，所述多个凸块包括焊料；
使用回流焊接工艺对所述管芯的所述多个凸块的焊料进行回流；
在所述管芯下方形成底部填充材料；
在所述管芯、所述底部填充材料和所述多个封装基板的上方形成模塑料；以及
沿着所述多个封装基板之间的所述分离区域切割所述多个封装基板，
其中，去除所述多个封装基板之间的分离区域上的所述多个封装基板之间的所述焊接掩模和所述介电材料的至少一部分包括同时去除所述多个封装基板之间的所述焊接掩模和所述介电材料的至少一部分以及所述工件与所述焊接掩模相对面上的底部。
14.根据权利要求13所述的方法，其中，附接所述管芯包括附接集成电路管芯，其中，设置在其上的所述多个凸块是多个微凸块。
15.根据权利要求13所述的方法，其中，去除所述多个封装基板之间的分离区域上的所述多个封装基板之间的所述焊接掩模和所述介电材料的至少一部分包括：去除所述工件的从顶部向下观察的x轴方向、y轴方向或者x轴方向和y轴方向上的所述焊接掩模和所述介电材料的至少一部分。
16.根据权利要求13所述的方法，其中，形成所述介电材料包括：形成具有100μm或者更小的厚度的介电材料。
17.根据权利要求13所述的方法，其中，形成所述焊接掩模包括：形成具有10μm至30μm的厚度的焊接掩模。
18.根据权利要求13所述的方法，其中，去除所述介电材料的至少一部分包括：从所述多个封装基板之间去除所有介电材料。
19.根据权利要求13所述的方法，其中，去除所述多个封装基板之间的所述焊接掩模和所述介电材料的至少一部分减少或防止所述回流焊接工艺期间所述多个封装基板或管芯的翘曲。
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