JP5465042B2 - パッケージ基板の加工方法 - Google Patents
パッケージ基板の加工方法 Download PDFInfo
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- JP5465042B2 JP5465042B2 JP2010043663A JP2010043663A JP5465042B2 JP 5465042 B2 JP5465042 B2 JP 5465042B2 JP 2010043663 A JP2010043663 A JP 2010043663A JP 2010043663 A JP2010043663 A JP 2010043663A JP 5465042 B2 JP5465042 B2 JP 5465042B2
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- 239000000758 substrate Substances 0.000 title claims description 79
- 238000003672 processing method Methods 0.000 title claims description 8
- 239000011347 resin Substances 0.000 claims description 36
- 229920005989 resin Polymers 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 10
- 239000002390 adhesive tape Substances 0.000 description 11
- 239000002184 metal Substances 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Dicing (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
4 金属フレーム
6a,6b,6c チップ領域
8a,8b 分割予定ライン
10 チップ形成部
12 電極
14 半導体チップ
16 モールド樹脂
20 パッケージ基板(BGA基板)
24a,24b 分割予定ライン
26 チップ形成部
28 ボール電極
30 モールド樹脂
15 DAF
32 切削ブレード
34 切削溝
36 保護部材(保護テープ)
40 研削ホイール
44 半導体デバイス
46 ピックアップコレット
50 粘着テープ
52 環状フレーム
54 切削溝
Claims (1)
- 格子状に形成された複数の分割予定ラインで区画された基板上の各領域に半導体チップが固定されて樹脂で封止され、樹脂面と該樹脂面の反対側の電極面とを有するパッケージ基板の加工方法であって、
該パッケージ基板の該電極面側に支持部材を配設する支持部材配設ステップと、
該支持部材配設ステップを実施した後、該樹脂面側から該分割予定ラインに沿って切削ブレードで該パッケージ基板に切り込み、該支持部材に至る切削溝を形成することで、該パッケージ基板の反りを補正する反り補正ステップと、
該反り補正ステップを実施した後、該パッケージ基板の該電極面側を保持テーブルで保持して該樹脂面を研削し、該パッケージ基板を所定の厚みへと薄化する研削ステップと、
を具備したことを特徴とするパッケージ基板の加工方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010043663A JP5465042B2 (ja) | 2010-03-01 | 2010-03-01 | パッケージ基板の加工方法 |
TW100102627A TWI524404B (zh) | 2010-03-01 | 2011-01-25 | Packaging substrate processing methods |
US13/023,165 US8198175B2 (en) | 2010-03-01 | 2011-02-08 | Processing method for package substrate |
CN201110049720.3A CN102194704B (zh) | 2010-03-01 | 2011-03-01 | 封装基板的加工方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010043663A JP5465042B2 (ja) | 2010-03-01 | 2010-03-01 | パッケージ基板の加工方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011181641A JP2011181641A (ja) | 2011-09-15 |
JP5465042B2 true JP5465042B2 (ja) | 2014-04-09 |
Family
ID=44505507
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010043663A Active JP5465042B2 (ja) | 2010-03-01 | 2010-03-01 | パッケージ基板の加工方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8198175B2 (ja) |
JP (1) | JP5465042B2 (ja) |
CN (1) | CN102194704B (ja) |
TW (1) | TWI524404B (ja) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10522452B2 (en) | 2011-10-18 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging methods for semiconductor devices including forming trenches in workpiece to separate adjacent packaging substrates |
JP2015085414A (ja) * | 2013-10-29 | 2015-05-07 | 株式会社ディスコ | パッケージ基板の加工方法 |
JP2015093338A (ja) * | 2013-11-11 | 2015-05-18 | 株式会社ディスコ | パッケージ基板の加工方法 |
JP6257291B2 (ja) * | 2013-12-04 | 2018-01-10 | 株式会社ディスコ | パッケージ基板の加工方法 |
JP6282194B2 (ja) * | 2014-07-30 | 2018-02-21 | 株式会社ディスコ | ウェーハの加工方法 |
JP6448302B2 (ja) * | 2014-10-22 | 2019-01-09 | 株式会社ディスコ | パッケージ基板の研削方法 |
JP2016082192A (ja) * | 2014-10-22 | 2016-05-16 | 株式会社ディスコ | パッケージ基板の分割方法 |
JP6495054B2 (ja) * | 2015-03-04 | 2019-04-03 | 株式会社ディスコ | パッケージ基板の研削方法 |
CN105403441A (zh) * | 2015-11-02 | 2016-03-16 | 广东威创视讯科技股份有限公司 | Led失效分析方法及其过程中封装树脂的减薄方法 |
JP6887722B2 (ja) * | 2016-10-25 | 2021-06-16 | 株式会社ディスコ | ウェーハの加工方法及び切削装置 |
JP6896326B2 (ja) * | 2017-03-06 | 2021-06-30 | 株式会社ディスコ | 加工装置 |
JP2019121722A (ja) * | 2018-01-10 | 2019-07-22 | 株式会社ディスコ | パッケージ基板の製造方法 |
JP7075791B2 (ja) * | 2018-03-20 | 2022-05-26 | 株式会社ディスコ | 半導体パッケージの製造方法 |
JP2020088262A (ja) * | 2018-11-29 | 2020-06-04 | 株式会社ディスコ | パッケージ基板の分割方法 |
JP7313259B2 (ja) | 2019-10-30 | 2023-07-24 | 株式会社ディスコ | 樹脂基板の加工方法 |
JP2021190462A (ja) | 2020-05-26 | 2021-12-13 | 株式会社ディスコ | パッケージ基板の製造方法 |
CN114603417B (zh) * | 2022-03-31 | 2023-01-24 | 生益电子股份有限公司 | 一种pcb磨板方法、pcb返磨装置及pcb |
CN117352399A (zh) * | 2023-09-28 | 2024-01-05 | 昆山国显光电有限公司 | 封装方法和芯片封装结构、电子设备 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001094005A (ja) * | 1999-09-22 | 2001-04-06 | Oki Electric Ind Co Ltd | 半導体装置及び半導体装置の製造方法 |
JP2001267344A (ja) * | 2000-03-17 | 2001-09-28 | Matsushita Electric Ind Co Ltd | 樹脂封止型半導体装置の製造方法 |
JP4856328B2 (ja) * | 2001-07-13 | 2012-01-18 | ローム株式会社 | 半導体装置の製造方法 |
JP4595265B2 (ja) * | 2001-08-13 | 2010-12-08 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置の製造方法 |
JP2005209719A (ja) * | 2004-01-20 | 2005-08-04 | Disco Abrasive Syst Ltd | 半導体ウエーハの加工方法 |
JP2007311378A (ja) * | 2006-05-16 | 2007-11-29 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
JP5064102B2 (ja) | 2007-04-27 | 2012-10-31 | 株式会社ディスコ | 基板の研削加工方法および研削加工装置 |
JP2009070880A (ja) * | 2007-09-11 | 2009-04-02 | Nec Electronics Corp | 半導体装置の製造方法 |
JP2009194345A (ja) * | 2008-02-18 | 2009-08-27 | Spansion Llc | 半導体装置の製造方法 |
-
2010
- 2010-03-01 JP JP2010043663A patent/JP5465042B2/ja active Active
-
2011
- 2011-01-25 TW TW100102627A patent/TWI524404B/zh active
- 2011-02-08 US US13/023,165 patent/US8198175B2/en active Active
- 2011-03-01 CN CN201110049720.3A patent/CN102194704B/zh active Active
Also Published As
Publication number | Publication date |
---|---|
TWI524404B (zh) | 2016-03-01 |
CN102194704A (zh) | 2011-09-21 |
JP2011181641A (ja) | 2011-09-15 |
CN102194704B (zh) | 2015-06-10 |
US20110212574A1 (en) | 2011-09-01 |
US8198175B2 (en) | 2012-06-12 |
TW201140674A (en) | 2011-11-16 |
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