JP6298723B2 - 貼り合わせウェーハ形成方法 - Google Patents
貼り合わせウェーハ形成方法 Download PDFInfo
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- JP6298723B2 JP6298723B2 JP2014122053A JP2014122053A JP6298723B2 JP 6298723 B2 JP6298723 B2 JP 6298723B2 JP 2014122053 A JP2014122053 A JP 2014122053A JP 2014122053 A JP2014122053 A JP 2014122053A JP 6298723 B2 JP6298723 B2 JP 6298723B2
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- Prior art keywords
- wafer
- center position
- outer peripheral
- wafers
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000000034 method Methods 0.000 title claims description 25
- 235000012431 wafers Nutrition 0.000 claims description 225
- 230000002093 peripheral effect Effects 0.000 claims description 31
- 238000005520 cutting process Methods 0.000 claims description 18
- 238000003384 imaging method Methods 0.000 claims description 12
- 230000001070 adhesive effect Effects 0.000 description 11
- 239000000853 adhesive Substances 0.000 description 10
- 238000009966 trimming Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000001514 detection method Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000010030 laminating Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000005336 cracking Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
Landscapes
- Mechanical Treatment Of Semiconductor (AREA)
Description
11a 表面
11b 裏面
12 分割予定ライン
13 デバイス
14 アライメントマーク
15 面取り部
21 ベースウェーハ
32 撮像手段
33 切削ブレード
51 貼り合わせウェーハ
A1 デバイス領域
A2 外周余剰領域
C1 中心位置
Claims (1)
- 表面に複数の分割予定ラインが格子状に形成され該複数の分割予定ラインによって区画された複数の領域にデバイスが形成されたデバイス領域と該デバイス領域を囲繞し外周に面取り部を備えた外周余剰領域とを有する複数のウェーハを薄化してベースウェーハに貼り合わせて貼り合わせウェーハを形成する貼り合わせウェーハ形成方法であって、
ウェーハの表面には、該ベースウェーハと複数のウェーハとを積層させる位置を合わせ用のアライメントマークが少なくとも2個形成されており、
該アライメントマークを撮像手段で検出し、検出した該アライメントマークを基準にウェーハの中心を算出する中心位置検出ステップと、
該中心位置検出ステップで検出された中心位置を基準に切削ブレードを該外周余剰領域に位置付けて切り込み、ウェーハを相対的に回転させて該外周余剰領域の面取り部を除去する外周余剰領域除去ステップと、
該外周余剰領域除去ステップを実施した後に、該アライメントマークを使用して該ベースウェーハと積層させるウェーハとの位置合わせを行い貼り合わせるウェーハ貼り合わせステップと、
該外周余剰領域除去ステップを実施した後で且つ該ウェーハ貼り合わせステップを実施する前又は後に、ウェーハ裏面側を研削して薄化する薄化ステップと、
から構成される貼り合わせウェーハ形成方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014122053A JP6298723B2 (ja) | 2014-06-13 | 2014-06-13 | 貼り合わせウェーハ形成方法 |
Applications Claiming Priority (1)
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JP2014122053A JP6298723B2 (ja) | 2014-06-13 | 2014-06-13 | 貼り合わせウェーハ形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016004795A JP2016004795A (ja) | 2016-01-12 |
JP6298723B2 true JP6298723B2 (ja) | 2018-03-20 |
Family
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JP2014122053A Active JP6298723B2 (ja) | 2014-06-13 | 2014-06-13 | 貼り合わせウェーハ形成方法 |
Country Status (1)
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JP (1) | JP6298723B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109534283A (zh) * | 2018-11-15 | 2019-03-29 | 赛莱克斯微系统科技(北京)有限公司 | 一种微机电器件制备方法及装置 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6635860B2 (ja) * | 2016-04-07 | 2020-01-29 | 株式会社ディスコ | 加工方法 |
JP7051421B2 (ja) * | 2017-12-22 | 2022-04-11 | 株式会社ディスコ | ウェーハの加工方法および貼り合わせウェーハの加工方法 |
CN113826195A (zh) * | 2019-06-25 | 2021-12-21 | 株式会社村田制作所 | 复合部件及其制造方法 |
JP7398242B2 (ja) * | 2019-10-28 | 2023-12-14 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理システム |
CN112071747B (zh) * | 2020-09-17 | 2024-02-27 | 武汉新芯集成电路制造有限公司 | 晶圆键合方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2006032661A (ja) * | 2004-07-16 | 2006-02-02 | Disco Abrasive Syst Ltd | 切削装置 |
JP2009255214A (ja) * | 2008-04-15 | 2009-11-05 | Disco Abrasive Syst Ltd | 加工装置 |
JP5487621B2 (ja) * | 2009-01-05 | 2014-05-07 | 株式会社ニコン | 半導体装置の製造方法及び半導体製造装置 |
JP5656609B2 (ja) * | 2010-12-20 | 2015-01-21 | 株式会社ディスコ | 治具プレートを使用した半導体デバイスチップの積層方法 |
JP5755043B2 (ja) * | 2011-06-20 | 2015-07-29 | 株式会社ディスコ | 半導体ウエーハの加工方法 |
SG2014012934A (en) * | 2012-06-12 | 2014-09-26 | Erich Thallner | Substrate-product substrate combination as well as device and process for producing a substrate-product substrate combination |
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- 2014-06-13 JP JP2014122053A patent/JP6298723B2/ja active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109534283A (zh) * | 2018-11-15 | 2019-03-29 | 赛莱克斯微系统科技(北京)有限公司 | 一种微机电器件制备方法及装置 |
CN109534283B (zh) * | 2018-11-15 | 2020-09-25 | 赛莱克斯微系统科技(北京)有限公司 | 一种微机电器件制备方法及装置 |
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JP2016004795A (ja) | 2016-01-12 |
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