JP5755043B2 - 半導体ウエーハの加工方法 - Google Patents
半導体ウエーハの加工方法 Download PDFInfo
- Publication number
- JP5755043B2 JP5755043B2 JP2011136072A JP2011136072A JP5755043B2 JP 5755043 B2 JP5755043 B2 JP 5755043B2 JP 2011136072 A JP2011136072 A JP 2011136072A JP 2011136072 A JP2011136072 A JP 2011136072A JP 5755043 B2 JP5755043 B2 JP 5755043B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- chip
- semiconductor device
- semiconductor
- grinding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 113
- 238000003672 processing method Methods 0.000 title claims description 7
- 238000000227 grinding Methods 0.000 claims description 65
- 238000000034 method Methods 0.000 claims description 22
- 230000001681 protective effect Effects 0.000 claims description 16
- 230000002093 peripheral effect Effects 0.000 claims description 14
- 239000000945 filler Substances 0.000 claims description 7
- 235000012431 wafers Nutrition 0.000 description 80
- 239000000853 adhesive Substances 0.000 description 16
- 230000001070 adhesive effect Effects 0.000 description 16
- 239000000758 substrate Substances 0.000 description 7
- 238000005520 cutting process Methods 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 239000007788 liquid Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Dicing (AREA)
Description
10 研削ユニット
11 半導体ウエーハ
15 半導体デバイス
17 デバイス領域
19 外周余剰領域
23 保護テープ
24 研削砥石
36 チャックテーブル
44 円形凹部
46 環状凸部
54 半導体デバイスチップ
55 チップ積層ウエーハ
56 充填材
60 貫通電極
62 再配線層
68 積層デバイスチップ
Claims (2)
- 複数の交差する分割予定ラインで区画された各領域にそれぞれ半導体デバイスが形成されたデバイス領域と該デバイス領域を囲繞する外周余剰領域とを表面に有する半導体ウエーハの加工方法であって、
半導体ウエーハの該表面に保護テープを貼着する保護テープ貼着ステップと、
該保護テープ貼着ステップを実施した後、該デバイス領域に対応する半導体ウエーハの裏面を研削して円形凹部を形成するとともに該円形凹部を囲繞する環状凸部を形成する研削ステップと、
該研削ステップを実施した後、該半導体ウエーハの該各半導体デバイスに対応させて半導体デバイスチップのデバイス面を該円形凹部の底面に配設するとともに、少なくとも該半導体デバイスチップの仕上げ厚みに至る深さまで該円形凹部内に充填材を充填してチップ積層ウエーハを形成するチップ積層ウエーハ形成ステップと、
該チップ積層ウエーハ形成ステップを実施した後、該チップ積層ウエーハの裏面を研削して該半導体デバイスチップを所定の厚みへ薄化する薄化ステップと、
該薄化ステップを実施した後、半導体ウエーハの該各半導体デバイスに貫通電極を形成する貫通電極形成ステップと、
を具備したことを特徴とする半導体ウエーハの加工方法。 - 前記貫通電極形成ステップを実施した後、前記チップ積層ウエーハを前記分割予定ラインに沿って分割する分割ステップを更に具備した請求項1記載の半導体ウエーハの加工方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011136072A JP5755043B2 (ja) | 2011-06-20 | 2011-06-20 | 半導体ウエーハの加工方法 |
US13/527,850 US8765579B2 (en) | 2011-06-20 | 2012-06-20 | Semiconductor wafer processing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011136072A JP5755043B2 (ja) | 2011-06-20 | 2011-06-20 | 半導体ウエーハの加工方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013004836A JP2013004836A (ja) | 2013-01-07 |
JP5755043B2 true JP5755043B2 (ja) | 2015-07-29 |
Family
ID=47353988
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011136072A Active JP5755043B2 (ja) | 2011-06-20 | 2011-06-20 | 半導体ウエーハの加工方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8765579B2 (ja) |
JP (1) | JP5755043B2 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102043378B1 (ko) * | 2012-10-22 | 2019-11-12 | 삼성전자주식회사 | 캐비티를 갖는 웨이퍼 캐리어 |
US9136173B2 (en) | 2012-11-07 | 2015-09-15 | Semiconductor Components Industries, Llc | Singulation method for semiconductor die having a layer of material along one major surface |
US9484260B2 (en) | 2012-11-07 | 2016-11-01 | Semiconductor Components Industries, Llc | Heated carrier substrate semiconductor die singulation method |
JP6071702B2 (ja) * | 2013-03-29 | 2017-02-01 | 株式会社ディスコ | ウエーハの加工方法 |
JP6366351B2 (ja) * | 2014-05-13 | 2018-08-01 | 株式会社ディスコ | ウェーハの加工方法 |
JP6385131B2 (ja) * | 2014-05-13 | 2018-09-05 | 株式会社ディスコ | ウェーハの加工方法 |
JP6298723B2 (ja) * | 2014-06-13 | 2018-03-20 | 株式会社ディスコ | 貼り合わせウェーハ形成方法 |
JP2017073472A (ja) * | 2015-10-07 | 2017-04-13 | 株式会社ディスコ | 半導体装置の製造方法 |
GB2551732B (en) * | 2016-06-28 | 2020-05-27 | Disco Corp | Method of processing wafer |
JP6791579B2 (ja) * | 2016-09-09 | 2020-11-25 | 株式会社ディスコ | ウェーハ及びウェーハの加工方法 |
US10373869B2 (en) | 2017-05-24 | 2019-08-06 | Semiconductor Components Industries, Llc | Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3792954B2 (ja) | 1999-08-10 | 2006-07-05 | 株式会社東芝 | 半導体装置の製造方法 |
JP3833858B2 (ja) * | 1999-08-23 | 2006-10-18 | ローム株式会社 | 半導体装置およびその製造方法 |
JP2007250599A (ja) * | 2006-03-14 | 2007-09-27 | Disco Abrasive Syst Ltd | デバイスパッケージの製造方法 |
JP4927484B2 (ja) * | 2006-09-13 | 2012-05-09 | 株式会社ディスコ | 積層用デバイスの製造方法 |
US20080242052A1 (en) * | 2007-03-30 | 2008-10-02 | Tao Feng | Method of forming ultra thin chips of power devices |
US7989318B2 (en) * | 2008-12-08 | 2011-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for stacking semiconductor dies |
JP5431777B2 (ja) * | 2009-04-20 | 2014-03-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP5442394B2 (ja) * | 2009-10-29 | 2014-03-12 | ソニー株式会社 | 固体撮像装置とその製造方法、及び電子機器 |
-
2011
- 2011-06-20 JP JP2011136072A patent/JP5755043B2/ja active Active
-
2012
- 2012-06-20 US US13/527,850 patent/US8765579B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
JP2013004836A (ja) | 2013-01-07 |
US8765579B2 (en) | 2014-07-01 |
US20120322231A1 (en) | 2012-12-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5755043B2 (ja) | 半導体ウエーハの加工方法 | |
JP5943544B2 (ja) | 積層デバイスの製造方法及び積層デバイス | |
JP4927484B2 (ja) | 積層用デバイスの製造方法 | |
JP2009021462A (ja) | ウェーハの加工方法 | |
US8129277B2 (en) | Method of machining wafer | |
JP4933233B2 (ja) | ウエーハの加工方法 | |
US10818607B2 (en) | Semiconductor device and method of manufacture | |
US9953871B2 (en) | Wafer processing method | |
JP5959188B2 (ja) | ウエーハの加工方法 | |
TWI771913B (zh) | 半導體裝置及半導體裝置之製造方法 | |
JP5885396B2 (ja) | デバイスチップの製造方法 | |
US11164802B2 (en) | Wafer manufacturing method and multilayer device chip manufacturing method | |
JP5545640B2 (ja) | 研削方法 | |
JP5840003B2 (ja) | ウエーハの加工方法 | |
US8652939B2 (en) | Method and apparatus for die assembly | |
JP5748198B2 (ja) | 積層デバイスの製造方法及び積層デバイス | |
JP5995616B2 (ja) | ウエーハの加工方法 | |
JP2014165339A (ja) | 積層ウエーハの加工方法 | |
JP2014053348A (ja) | ウエーハの加工方法 | |
JP6558541B2 (ja) | ウエーハの加工方法 | |
JP2014053350A (ja) | ウエーハの加工方法 | |
JP2014053354A (ja) | ウエーハの加工方法 | |
JP7313968B2 (ja) | ウエーハの加工方法 | |
JP7262903B2 (ja) | キャリア板の除去方法 | |
JP6594243B2 (ja) | ウェーハの加工方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140519 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150522 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20150526 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150526 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5755043 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |