TWI771913B - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

Info

Publication number
TWI771913B
TWI771913B TW110105709A TW110105709A TWI771913B TW I771913 B TWI771913 B TW I771913B TW 110105709 A TW110105709 A TW 110105709A TW 110105709 A TW110105709 A TW 110105709A TW I771913 B TWI771913 B TW I771913B
Authority
TW
Taiwan
Prior art keywords
semiconductor device
semiconductor
columnar
columnar electrode
electrode
Prior art date
Application number
TW110105709A
Other languages
English (en)
Other versions
TW202203393A (zh
Inventor
本間荘一
右田達夫
三浦正幸
前田竹識
加藤和弘
山本進
Original Assignee
日商鎧俠股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商鎧俠股份有限公司 filed Critical 日商鎧俠股份有限公司
Publication of TW202203393A publication Critical patent/TW202203393A/zh
Application granted granted Critical
Publication of TWI771913B publication Critical patent/TWI771913B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02377—Fan-in arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0239—Material of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05024—Disposition the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05611—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05613—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05618—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05664—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05671—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13171—Chromium [Cr] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73217—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H01L2225/06586—Housing with external bump or bump-like connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/145—Read-only memory [ROM]
    • H01L2924/1451—EPROM
    • H01L2924/14511—EEPROM
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

本實施方式之半導體裝置具備半導體晶片，該半導體晶片具有第1面、及與該第1面為相反之側之第2面，且於第1面上設置有半導體元件。柱狀電極設置於第1面之上方，且電性連接於半導體元件之任一個。第1構件於第1面之上方，設置於柱狀電極之周邊。絕緣材料被覆柱狀電極及第1構件。第1構件較柱狀電極及絕緣材料硬。第1構件及柱狀電極自絕緣材料之表面露出。

Description

半導體裝置及半導體裝置之製造方法
本發明之實施方式係關於一種半導體裝置及半導體裝置之製造方法。
業界開發出一種技術，將複數個半導體晶片及控制器晶片作為1個半導體封裝(CSP(Chip Scale Package，晶片規模封裝))進行樹脂密封。
然而，於對樹脂進行研磨而調整半導體封裝之厚度時，存在半導體封裝之厚度不均之問題。若半導體封裝過薄，則導致半導體封裝翹曲。又，一面測定樹脂之厚度一面對樹脂進行研磨會導致產量降低。
一實施方式提供一種能夠抑制產量降低、且抑制半導體封裝之厚度不均或半導體封裝之翹曲之半導體裝置及半導體裝置之製造方法。
實施方式之半導體裝置具備一種半導體裝置，其包括：半導體晶片(10)，其具有第1面及與上述第1面為相反之側之第2面，且於上述第1面側設置有半導體元件；柱狀電極(60)，其於將自上述第2面向上述第1面之方向設為上方向時，設置於上述第1面之上方，且電性連接於上述半導體元 件之任一個；第1構件(80)，其於上述第1面之上方，設置於上述柱狀電極之周邊；以及第1絕緣材料(90、122)，其設置於上述柱狀電極及上述第1構件之周圍；上述第1構件較上述柱狀電極及上述絕緣材料硬，上述第1構件及上述柱狀電極自上述絕緣材料之上方向側之表面露出。
根據上述構成，可提供一種能夠抑制產量降低、且抑制半導體封裝之厚度不均或半導體封裝之翹曲之半導體裝置及半導體裝置之製造方法。
1:半導體裝置
5:支持基板
10:半導體晶片
12:接著層
20:第1絕緣膜
30:電極墊
40:第2絕緣膜
45:障壁金屬
50:障壁金屬
55:電極
60:柱狀電極
60a:柱狀電極
60b:柱狀電極
60c:虛設柱狀電極
60d:虛設柱狀電極
70:樹脂層
70a~70c:樹脂層
80:虛設構件
80a~80c:構件
81:虛設構件
85:絕緣膜
90:第3絕緣膜
100:金屬凸塊
100A:金屬凸塊
121:配線層
122:絕緣層
120:再配線層
130:凹部
200:配線基板
300:轉盤
310:研磨墊
320:旋轉軸
330:馬達
340:電流感測器
350:信號轉換器
360:運算部
370:渦電流感測器
380:反射光感測器
400:模具
401:模具
410:插入口
420:脫模膜
500:絕緣材料
510:底部填充膠
F10a:第1面
F10b:第2面
F80a:上表面
F80a_1:第3面
F80b:背面
F80c:側面
H60b:孔
Hst:高度
P10:電極墊
PR:光阻劑
ST:階差
W:半導體晶圓
Φ1:開口徑
Φ2:直徑
Φ3:直徑(寬度)
圖1係表示第1實施方式之半導體裝置之構成之一例之剖視圖。
圖2係表示第1實施方式之半導體裝置之製造方法之一例之剖視圖。
圖3係表示接在圖2之後之半導體裝置之製造方法之一例之剖視圖。
圖4係表示接在圖3之後之半導體裝置之製造方法之一例之剖視圖。
圖5係表示接在圖4之後之半導體裝置之製造方法之一例之剖視圖。
圖6係表示接在圖5之後之半導體裝置之製造方法之一例之剖視圖。
圖7係表示接在圖6之後之半導體裝置之製造方法之一例之剖視圖。
圖8係表示接在圖7之後之半導體裝置之製造方法之一例之剖視圖。
圖9係表示接在圖8之後之半導體裝置之製造方法之一例之剖視圖。
圖10係表示接在圖9之後之半導體裝置之製造方法之一例之剖視圖。
圖11係表示接在圖10之後之半導體裝置之製造方法之一例之剖視圖。
圖12係表示接在圖11之後之半導體裝置之製造方法之一例之剖視圖。
圖13係表示第2實施方式之半導體裝置之製造方法及構成之一例之剖視圖。
圖14係表示第2實施方式之半導體裝置之製造方法及構成之一例之剖視圖。
圖15係表示第3實施方式之半導體裝置之製造方法及構成之一例之剖視圖。
圖16係表示第3實施方式之半導體裝置之製造方法及構成之一例之剖視圖。
圖17係表示第4實施方式之半導體裝置之製造方法及構成之一例之剖視圖。
圖18係表示第4實施方式之半導體裝置之製造方法及構成之一例之剖視圖。
圖19係表示第5實施方式之半導體裝置之製造方法及構成之一例之剖視圖。
圖20係表示第5實施方式之半導體裝置之製造方法及構成之一例之剖視圖。
圖21係表示第6實施方式之半導體裝置之構成之一例之剖視圖。
圖22係表示第7實施方式之半導體裝置之製造方法之一例之剖視圖。
圖23係表示接在圖22之後之半導體裝置之製造方法之一例之剖視圖。
圖24係表示第7實施方式之半導體裝置之構成例之剖視圖。
圖25係表示第8實施方式之半導體裝置之構成之一例之剖視圖。
圖26係表示第9實施方式之半導體裝置之構成之一例之剖視圖。
圖27係表示第10實施方式之半導體裝置之構成之一例之剖視圖。
圖28係表示第11實施方式之半導體裝置之構成之一例之剖視圖。
圖29係表示第11實施方式之半導體裝置之製造方法之一例之剖視圖。
圖30係表示接在圖29之後之半導體裝置之製造方法之一例之剖視圖。
圖31係表示接在圖31之後之半導體裝置之製造方法之一例之剖視圖。
圖32係表示將第11實施方式之半導體裝置安裝於配線基板上之狀態之剖視圖。
圖33係表示第12實施方式之半導體裝置之構成之一例之剖視圖。
圖34係表示第13實施方式之半導體裝置之構成之一例之剖視圖。
圖35係表示變化例1之樹脂密封工序之情況之圖。
圖36係表示變化例2之樹脂密封工序之情況之圖。
圖37係表示第14實施方式之半導體裝置之構成例之剖視圖。
圖38係表示第14實施方式之半導體裝置之製造方法之一例之剖視圖。
圖39係表示接在圖38之後之半導體裝置之製造方法之一例之剖視圖。
圖40係表示接在圖39之後之半導體裝置之製造方法之一例之剖視圖。
圖41係表示第15實施方式之半導體裝置之構成例之剖視圖。
圖42係表示第16實施方式之半導體裝置之構成例之剖視圖。
圖43係表示第17實施方式之半導體裝置之構成例之剖視圖。
圖44係表示第17實施方式之半導體裝置之構成例之俯視圖。
圖45係表示第18實施方式之半導體裝置之構成例之剖視圖。
圖46係表示第19實施方式之半導體裝置之構成例之剖視圖。
圖47係表示第20實施方式之半導體裝置之構成例之剖視圖。
圖48係表示第21實施方式之半導體裝置之構成例之剖視圖。
圖49係表示第22實施方式之半導體裝置之構成例之剖視圖。
圖50係表示第22實施方式之半導體裝置之構成例之剖視圖。
圖51係表示第22實施方式之半導體裝置之構成例之剖視圖。
圖52係表示第22實施方式之半導體裝置之構成例之剖視圖。
圖53係表示第23實施方式之半導體裝置之構成例之剖視圖。
圖54係表示第24實施方式之半導體裝置之構成例之剖視圖。
圖55係表示第25實施方式之半導體裝置之構成例之剖視圖。
圖56係表示第26實施方式之半導體裝置之構成例之剖視圖。
圖57係表示第27實施方式之半導體裝置之構成例之剖視圖。
圖58係表示第28實施方式之半導體裝置之構成例之剖視圖。
圖59係表示第29實施方式之半導體裝置之構成例之剖視圖。
圖60A係表示第30實施方式中之研磨裝置之構成例之圖。
圖60B係表示第30實施方式中之研磨裝置之構成例之圖。
圖60C係表示渦電流感測器之概略性構成之概念圖。
圖60D係表示第30實施方式中之研磨裝置之構成例之圖。
現在參考附圖說明實施例。本發明不限於該等實施例。於實施例中，“上方向”或“下方向”係指將與設置有半導體元件或半導體晶片之半導體基板之表面垂直之方向假設為“上方向”時之相對方向。因此，術 語“上方向”或“下方向”有時與基於重力加速度方向之上方向或下方向不同。於本說明書和附圖中，與前述附圖中描述之元件相同之元件用相同之附圖標記表示，並適當地省略其詳細說明。
本實施方式之半導體裝置具備半導體晶片，該半導體晶片具有第1面及與該第1面相反之側之第2面，且於第1面上設置有半導體元件。柱狀電極設置於第1面之上方，且電性連接於半導體元件之任一個。第1構件於第1面之上方，設置於柱狀電極之周邊。絕緣材料被覆柱狀電極及第1構件。第1構件較柱狀電極及絕緣材料硬。第1構件及柱狀電極自絕緣材料之表面露出。以下，於各實施方式中所謂之“硬”，亦可指於所謂之布氏硬度、維氏硬度等試驗中硬。
(第1實施方式)
圖1係表示第1實施方式之半導體裝置1之構成之一例之剖視圖。半導體裝置1具備半導體晶片10、第1絕緣膜20、電極墊30、第2絕緣膜40、障壁金屬50、柱狀電極60、樹脂層70、作為第1構件之虛設構件80、作為絕緣材料之第3絕緣膜90、以及金屬凸塊100。半導體裝置1例如亦可係NAND(Not And，與非)型快閃記憶體、LSI(Large Scale Integration，大規模積體電路)等半導體封裝。
半導體晶片10具有第1面F10a、及與第1面為相反之側之第2面F10b。電晶體或電容器等半導體元件(未圖示)形成於半導體晶片10之第1面F10a上。半導體晶片10例如亦可係NAND型快閃記憶體之記憶體晶片 或搭載有任意之LSI之半導體晶片。
第1絕緣膜20設置於半導體晶片10之第1面F10a上，被覆且保護上述半導體元件。第1絕緣膜20例如使用氧化矽膜、氮化矽膜等無機系絕緣材料。
電極墊30設置於半導體晶片10之第1面F10a上，且電性連接於半導體元件之任一個。電極墊30例如使用Al、Cu、Au、Ni、Pd、W等單體、其等之中2種以上之複合膜、或者其等之中2種以上之合金等低電阻金屬。第1絕緣膜20被局部地去除，以使電極墊30之一部分露出。
第2絕緣膜40設置於第1絕緣膜20上，且介置於第1絕緣膜20與第3絕緣膜90之間。第2絕緣膜40例如使用酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、環氧系、PBO(p-phenylenebenzobisoxazole，p-苯撐-苯并二噁唑)系、矽酮系、苯并環丁烯系等樹脂、或該等樹脂之混合材料、複合材料等有機系絕緣材料。
作為金屬膜之障壁金屬50設置於柱狀電極60與電極墊30或第2絕緣膜40之間。障壁金屬50用作形成柱狀電極60時之鍍覆電極。障壁金屬50例如使用Ti、TiN、Cr、CrN、Cu、Ni、Au、Pd、W等單體或其等之中2種以上之複合膜、或者其等之中2種以上之合金。
柱狀電極60設置於半導體晶片10之第1面F10a之上方之障壁金屬50 上。柱狀電極60自障壁金屬50向相對於第1面F10a大致垂直之方向延伸。柱狀電極60之下端經由障壁金屬50及電極墊30而電性連接於半導體晶片10之任一個半導體元件。又，柱狀電極60之上端連接於金屬凸塊100。柱狀電極60例如使用Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al等單體、其等之中2種以上之複合膜、或者其等之中2種以上之合金等導電性金屬。
柱狀電極60由於係利用鍍覆法或打線法等形成，故而形成於柱狀電極60之形成工序中露出之障壁金屬50之上方。再者，於打線法之情形時，亦可直接形成於電線30上。
樹脂層70設置於虛設構件80與第2絕緣膜40之間，且將虛設構件80於第1面F10a上接著於第2絕緣膜40。樹脂層70例如使用包含酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、環氧系、PBO(p-phenylenebenzobisoxazole)系、矽酮系、苯并環丁烯系等樹脂、或該等樹脂之混合材料、複合材料之DAF(Die Attach Film，晶粒黏著薄膜)或DAP(Die Attach Paste，晶粒黏著膏)。
作為第1構件之虛設構件80於第1面F10a之上方，設置於柱狀電極60之周邊。虛設構件80及柱狀電極60形成於距第1面F10a大致相同高度水準，虛設構件80及柱狀電極60之上表面自第3絕緣膜90之表面以大致相同之面露出。虛設構件80為了作為第3絕緣膜90之研磨工序中之研磨擋止層發揮功能，而由較柱狀電極60及第3絕緣膜90之兩者硬之材料構成。第3 絕緣膜90例如使用環氧系、酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、PBO系、矽酮系、苯并環丁烯系等樹脂、該等樹脂之混合材料、複合材料。虛設構件80例如使用矽、玻璃、氧化鋁、SiC、AlN、陶瓷、金屬等。
第3絕緣膜90於第1面F10a之上方，被覆且填埋柱狀電極60及虛設構件80之周圍。第3絕緣膜90之表面與柱狀電極60及虛設構件80之表面為大致同一平面，且露出柱狀電極60及虛設構件80之表面。
金屬凸塊100設置於柱狀電極60上。金屬凸塊100例如使用焊料等導電性金屬。
如上所述，本實施方式之半導體裝置1中，虛設構件係80設置於柱狀電極60之周圍，且與柱狀電極60一起埋入於第3絕緣膜90內。虛設構件80由較柱狀電極60及第3絕緣膜90硬之材料構成，且作為第3絕緣膜90之研磨工序中之擋止層發揮功能。藉此，當虛設構件80自第3絕緣膜90露出時，能夠阻止研磨處理。其結果，第3絕緣膜90之厚度不會不均，半導體裝置1之封裝之厚度穩定。
又，能夠根據虛設構件80之厚度來控制第3絕緣膜90之厚度。因此，於研磨之中途，無須測定第3絕緣膜90之厚度，能夠提高產量。
又，由於虛設構件80由較柱狀電極60及第3絕緣膜90硬之材料構成， 故而半導體裝置1被增強，不易翹曲。藉此，有助於提高半導體裝置1之可靠性。又，藉由改變半導體裝置內之虛設構件80之體積，亦能夠調整翹曲，進而能夠提高可靠性。
接下來，對本實施方式之半導體裝置1之製造方法進行說明。
圖2~圖12係表示第1實施方式之半導體裝置1之製造方法之一例之剖視圖。再者，於圖中，表示了半導體晶片，但該半導體晶片係切割前之晶圓狀態之一部分。
首先，於半導體晶圓W之第1面F10a上形成半導體元件(未圖示)。半導體晶圓W例如可係矽基板等半導體基板。接下來，於第1面F10a上，形成與半導體元件電性連接之電極墊30。電極墊30例如使用Al、Cu、Au、Ni、Pd、W等單體、其等之中2種以上之複合膜、或者其等之中2種以上之合金等。接下來，以被覆半導體元件之方式，於第1面F10a上形成第1絕緣膜20。利用微影技術及蝕刻技術對第1絕緣膜20進行加工，使電極墊30之一部分露出。第1絕緣膜20例如使用氧化矽膜、氮化矽膜等無機系絕緣材料。接下來，於第1絕緣膜20上形成第2絕緣膜40。亦對第2絕緣膜40進行加工，以使電極墊30之一部分露出。第2絕緣膜40例如使用酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、環氧系、PBO(p-phenylenebenzobisoxazole)系、矽酮系、苯并環丁烯系等樹脂、或該等樹脂之混合材料、複合材料等有機系絕緣材料。藉此，獲得圖2所示之結構。
接下來，如圖3所示，利用濺鍍法、蒸鍍法或無電解鍍覆法，於電極墊30及第2絕緣膜40上形成障壁金屬50。障壁金屬50例如使用Ti、TiN、Cr、CrN、Cu、Ni、Au、Pd、W等單體、其等之中2種以上之複合膜、或者其等之中2種以上之合金。例如，障壁金屬50使用利用濺鍍法形成之0.1μm之厚度之Ti膜與0.3μm之厚度之Cu膜之積層膜。
接下來，如圖4所示，於障壁金屬50上塗佈光阻劑PR。利用微影技術，將光阻劑PR加工為柱狀電極60之圖案。例如，光阻劑PR之厚度約為40μm，於電極墊30上形成約100μm見方之開口。鄰接之開口間之間距約為300μm。為了去除開口底部之殘渣，亦可進行O2灰化處理。藉此，處於柱狀電極60之形成位置之障壁金屬50確實地露出。
接下來，於露出之障壁金屬50上，利用電鍍法等堆積Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al等單體、其等之中2種以上之複合膜、或者其等之中2種以上之合金。藉此，如圖5所示，於柱狀電極60之形成區域選擇性地鍍覆金屬，而形成柱狀電極60。例如，柱狀電極60係藉由將Cu以約35μm之厚度鍍覆來形成。
接下來，如圖6所示，將光阻劑PR剝離。於剝離之後，為了去除殘渣，亦可進行O2灰化處理。
接下來，如圖7所示，使用柱狀電極60作為遮罩，對障壁金屬50進行蝕刻。例如，於障壁金屬50為Cu之情形時，利用檸檬酸及過氧化氫之混 合溶液進行濕式蝕刻即可。於障壁金屬50為Ti之情形時，利用氫氟酸或過氧化氫水等進行蝕刻即可。
接下來，如圖8所示，將晶片狀之虛設構件80介隔樹脂層70貼附於第1面F10a上。樹脂層70例如使用包含酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、環氧系、PBO(p-phenylenebenzobisoxazole)系、矽酮系、苯并環丁烯系等樹脂之DAF(Die Attach Film)或DAP(Die Attach Paste)之單體、該等之中2種以上之混合材料、該等之中2種以上之積層材料。虛設構件80係較柱狀電極60及圖9所示之第3絕緣膜90硬之材料。虛設構件80例如使用矽、玻璃、氧化鋁、SiC、AlN、陶瓷、金屬等單體、該等之中2種以上之混合材料、或者該等之中2種以上之積層材料。虛設構件80之維氏硬度理想之係0.85GPa以上30GPa以下。若小於0.85GPa，則接近第3絕緣膜、柱狀電極之維氏硬度，難以阻止研磨。相反，若超過30GPa，則材料價格高且特殊，不易使用。更理想的是可使維氏硬度為5GPa以上25GPa以下。虛設構件80以預先成為規定高度之方式設計。虛設構件80之上表面定位於較柱狀電極60之上表面低之位置。藉此，於研磨第3絕緣膜90時，虛設構件80於柱狀電極60露出之後，可使研磨停止。例如，若柱狀電極60之厚度約為35μm，則將樹脂層70之厚度設為約5μm，將虛設構件80之厚度設為約25μm，將整體之厚度設為約30μm。再者，於使用金屬作為虛設構件80之情形時，亦可利用鍍覆法形成。例如，於形成柱狀電極60之後，亦可利用鍍覆法形成與柱狀電極60不同之金屬作為虛設構件80。於此情形時，亦可不使用貼附虛設構件80之樹脂層70。
接下來，如圖9所示，於第1面F10a上，利用模塑法等形成第3絕緣膜90。第3絕緣膜90之形成方法可係塗佈液狀樹脂之方法，或者亦可係使用片狀膜之片材模塑法。第3絕緣膜90使用環氧系、酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、PBO系、矽酮系、苯并環丁烯系等樹脂、該等樹脂之混合材料、複合材料。環氧樹脂之例子並不特別限定，例如，可列舉雙酚A型、雙酚F型、雙酚AD型、雙酚S型等雙酚型環氧樹脂、酚系酚醛清漆、甲酚酚醛清漆型等酚醛清漆型環氧樹脂、間苯二酚型環氧樹脂、三酚甲三縮水甘油醚等芳香族環氧樹脂、萘型環氧樹脂、茀型環氧樹脂、二環戊二烯型環氧樹脂、聚醚改性環氧樹脂、二苯甲酮型環氧樹脂、苯胺型環氧樹脂、NBR改性環氧樹脂、CTBN改性環氧樹脂、及該等樹脂之氫化物等。其中，自與Si之密接性良好之方面而言，較佳為萘型環氧樹脂、二環戊二烯型環氧樹脂。又，自容易獲得速硬化性之方面而言，亦較佳為二苯甲酮型環氧樹脂。該等環氧樹脂可單獨使用，亦可將2種以上一併使用。又，亦可於第3絕緣膜90中包含二氧化矽等填料。第3絕緣膜90以埋入柱狀電極60及虛設構件80之方式形成。於第3絕緣膜90係利用烘箱等之加熱或UV(ultraviolet，紫外線)硬化類型樹脂之情形時，藉由利用紫外線等固化來硬化。
接下來，如圖10所示，利用機械研磨法、CMP(Chemical Mechanical Polishing，化學機械拋光)法等，對第3絕緣膜90及柱狀電極60進行研磨，而使虛設構件80露出。虛設構件80由於由較硬化後之第3絕緣膜90及柱狀電極60硬之材料構成，故而於虛設構件80露出時，能夠使第3絕緣膜90及柱狀電極60之研磨停止。例如，於虛設構件80及其下方之 樹脂層70之厚度約為30μm情形時，第3絕緣膜90之厚度亦能夠一致為約30μm。由於虛設構件80之上表面較柱狀電極60之上表面低，故而虛設構件80於柱狀電極60露出之後能夠使研磨停止。
接下來，如圖11所示，於柱狀電極60上塗佈助焊劑，形成金屬凸塊100。金屬凸塊100使用以Sn為主成分之焊料等金屬。例如，使用Sn、Ag、Cu、Au、Pd、Bi、Zn之單體、其等之中之2種以上之複合膜、或合金。接下來，藉由將金屬凸塊100回流焊，而將金屬凸塊100連接於柱狀電極60。
接下來，利用刀片切割法或雷射切割法等，將半導體晶圓W切割，而單片化為半導體晶片10。藉此，完成圖11所示之半導體裝置1。然後，如圖12所示，於配線基板200上搭載半導體裝置1，將金屬凸塊100連接於配線基板200之電極墊。亦可於配線基板200上搭載其他半導體裝置，並模組化。又，亦可於半導體晶圓W之狀態下，搭載於配線基板200上，然後，將半導體晶圓W與配線基板200一起切割。金屬凸塊100亦可形成於配線基板200上。於該情形時，將柱狀電極60之露出面與形成於配線基板200之金屬凸塊100連接。
如以上所述，根據本實施方式，虛設構件80與柱狀電極60一起設置於第1面F10a上。虛設構件80由較柱狀電極60及第3絕緣膜90硬之材料構成，且作為第3絕緣膜90之研磨工序中之擋止層發揮功能。藉此，第3絕緣膜90之厚度不會不均，而半導體裝置1之封裝之厚度穩定。
又，能夠根據虛設構件80之厚度來控制第3絕緣膜90之厚度。因此，於研磨之中途，無須測定第3絕緣膜90之厚度，能夠提高產量。
又，由於虛設構件80由較柱狀電極60及第3絕緣膜90硬之材料構成，故而半導體裝置1被增強，不易翹曲。藉此，有助於提高半導體裝置1之可靠性。
例如，對本實施方式之半導體裝置1進行溫度循環試驗(Thermal Cycle Test)，調查其可靠性。溫度循環試驗係將-55℃(30min)、25℃(5min)、125℃(30min)作為1個循環進行。其結果，即便於3000個循環之後，半導體裝置1亦無問題。
(第2實施方式)
圖13及圖14係表示第2實施方式之半導體裝置1之製造方法及構成之一例之剖視圖。圖13表示半導體裝置1之製造中途之構成，且表示了與第1實施方式之圖9對應之狀態。圖14表示了完成後之半導體裝置1之構成。
於第2實施方式中，虛設構件80被分割成自第1面F10a之上方觀察之面積互不相同之作為複數個第2構件之構件80a~80c，成為將構件80a~80c積層而構成之積層體。藉由使構件80a~80c之面積不同，虛設構件80之研磨面積變化。由於研磨阻力會基於虛設構件80之研磨面積之變化而變化，故而研磨裝置(未圖示)能夠特定出正在研磨之構件80a~80c。研磨裝 置於虛設構件80之研磨面積(或者研磨阻力)成為規定值時停止研磨處理。只要預先設定與虛設構件80之研磨面積(或者研磨阻力)對應之構件80a~80c及樹脂層70a~70c之厚度，便能夠控制研磨中之虛設構件80之剩餘膜厚(第3絕緣膜90之剩餘膜厚)。
對第2實施方式之製造方法更詳細地進行說明。
經過圖2~圖7所示之工序之後，構件80a利用樹脂層70a接著於第2絕緣膜40上，構件80b利用樹脂層70b接著於構件80a上，構件80c利用樹脂層70c接著於構件80b上。例如，將構件80a~80c之厚度分別設定為約10μm，將樹脂層70a~70c之厚度分別設定為約5μm。於該情形時，虛設構件80之高度成為約45μm。又，自第1面F10a之上方觀察時，構件80a~80c中之構件80a之面積最大，並按照構件80b、80c之順序變小。藉此，如圖13所示，構成為構件80a~80c之側面階梯狀地具有階差。構件80a~80c之材料可與第1實施方式之虛設構件80之材料相同。又，樹脂層70a~70c之材料可與第1實施方式之樹脂層70之材料相同。
接下來，如參照圖9所說明，第3絕緣膜90以埋入構件80a~80c及柱狀電極60之方式形成。藉此，獲得圖13所示之結構。
接下來，對第3絕緣膜90及柱狀電極60進行研磨，使虛設構件80露出。此時，虛設構件80自構件80c起依次被研磨。因此，虛設構件80之研磨面積最初較小，但逐漸變大。由於研磨阻力會根據虛設構件80之研磨面 積變化而變化，故而研磨裝置能夠檢測出構件80a~80c之哪一個露出。藉此，能夠控制第3絕緣膜90之厚度。例如，當於構件80b露出之時間點停止研磨之情形時，構件80c及樹脂層70c被研磨之後，於構件80b露出之時間點研磨裝置停止研磨。藉此，如圖14所示，第3絕緣膜90之厚度係可控制在與構件80a、80b及樹脂層70a、70b之合計厚度(於上述例子之情形時，例如為30μm)大致相等。
接下來，於柱狀電極60上塗佈助焊劑，形成金屬凸塊100。接下來，將半導體晶圓W切割，而單片化為半導體晶片10。藉此，完成圖14所示之半導體裝置1。
研磨亦可於構件80a露出之時間點停止。又，虛設構件80亦可係2層構件之積層體，或亦可係4層以上構件之積層體。各構件80a~80c之厚度只要預先判明，則亦可互不相同。
根據第2實施方式，虛設構件80於俯視時成為面積互不相同之複數個構件80a~80c之積層體。又，構件80a~80c及樹脂層70a~70c之厚度預先設定。藉此，容易控制第3絕緣膜90之膜厚。第2實施方式之其他構成可與第1實施方式相同。因此，第2實施方式亦能獲得與第1實施方式相同之效果。
(第3實施方式)
圖15及圖16係表示第3實施方式之半導體裝置1之製造方法及構成之 一例之剖視圖。圖15表示半導體裝置1之製造中途之構成，且表示與第1實施方式之圖9對應之狀態。圖16表示完成後之半導體裝置1之構成。
於第3實施方式中，虛設構件80於其側面F80c具有階梯狀之階差ST。利用虛設構件80之側面F80c之階差ST，而使自第1面F10a觀察時之各階差ST中之面積不同，藉此，虛設構件80之研磨面積變化。研磨裝置係由於基於虛設構件80之研磨面積之變化而研磨阻力變化，故而能夠特定出正在研磨之虛設構件80之階差ST之高度。若預先設定虛設構件80之各階差ST之厚度(高度)，則能夠控制研磨中之虛設構件80之剩餘膜厚(第3絕緣膜90之剩餘膜厚)。
就第3實施方式之製造方法進一步詳細說明。
於經過圖2~圖7所示之工序之後，虛設構件80利用樹脂層70a接著於第2絕緣膜40上。虛設構件80具有上表面F80a、背面F80b、及側面F80c。於虛設構件80之側面F80c，形成有階差ST。階差ST亦可利用微影技術及蝕刻技術形成。或者，階差ST亦可利用加工技術、切割刀片形成。階差ST既可於將虛設構件80貼附於第2絕緣膜40上之後形成，亦可於將虛設構件80貼附於第2絕緣膜40上之前形成。例如，將各階差ST之厚度分別設為約10μm，將階差ST之段數設為5個。於該情形時，自虛設構件80之階差ST之最下段到最上段為止之高度Hst成為約40μm。又，於自第1面F10a之上方觀察時，虛設構件80之研磨面積於虛設構件80之最上段中最小，越向下段前進越大。虛設構件80之材料可與第1實施方式之虛設構件80之材 料相同。
接下來，如參照圖9所說明，第3絕緣膜90以埋入虛設構件80及柱狀電極60之方式形成。藉此，獲得圖15所示之結構。
接下來，對第3絕緣膜90及柱狀電極60進行研磨，而使虛設構件80露出。此時，虛設構件80自上段起向下段依次被研磨。因此，虛設構件80之研磨面積最初較小，但逐漸變大。由於根據虛設構件80之研磨面積變化而研磨阻力變化，故而研磨裝置能夠檢測哪個高度之階差部分露出。藉此，能夠控制第3絕緣膜90之厚度。例如，當於自虛設構件80之最上段起第4段之上表面露出之時間點停止研磨之情形時，於自虛設構件80之最上段起第3段被研磨之後，於第4段之上表面露出之時間點研磨裝置停止研磨。藉此，如圖16所示，可控制為第3絕緣膜90之厚度與第4段以下之虛設構件80及樹脂層70之合計厚度大致相等。此時，例如，Hst成為10μm。
接下來，於柱狀電極60上塗佈助焊劑，形成金屬凸塊100。接下來，將半導體晶圓W切割，而單片化為半導體晶片10。藉此，完成圖16所示之半導體裝置1。
使研磨停止之階差並不特別限定。研磨亦可於自虛設構件80之最上段起第3段露出之時間點停止。階差ST之段數亦並不特別限定。又，各階差ST之高度只要預先判明，則亦可互不相同。
如此，根據第3實施方式，虛設構件80具備自第3絕緣膜90露出之第3面(研磨面)F80a_1、與半導體晶片之第1面F10a對應之第4面F80b、以及處於第3面F80a_1與第4面F80b之間之側面F80c，側面F80c階梯狀具有階差ST。而且，階差ST之高度(厚度)預先設定。藉此，第3絕緣膜90之膜厚之控制變得容易。第3實施方式之其他構成可與第1實施方式相同。因此，第3實施方式亦能夠獲得與第1實施方式相同之效果。
(第4實施方式)
圖17及圖18係表示第4實施方式之半導體裝置1之製造方法及構成之一例之剖視圖。圖17表示半導體裝置1之製造中途之構成，且表示了與第1實施方式之圖9對應之狀態。圖18表示了完成後之半導體裝置1之構成。
於第4實施方式中，虛設構件80於其上表面F80a之中心部具有凹部，於該凹部之兩側具有階梯狀之階差ST。自第1面F10a之上方觀察時之各階差ST中之虛設構件80之面積因據階差ST而不同，藉此，虛設構件80之研磨面積變化。研磨裝置之研磨阻力會基於虛設構件80之研磨面積之變化而變化，故而能夠特定出正在研磨之虛設構件80之階差ST之高度。只要預先設定虛設構件80之各階差ST之厚度(高度)，便能夠與第3實施方式同樣地，控制研磨中之虛設構件80之剩餘膜厚(第3絕緣膜90之剩餘膜厚)。
根據第4實施方式，階差ST於上表面F80a之中心部設置於凹部之兩側。包含階差ST之段數、高度、形成方法在內之第4實施方式之其他構成 及製造方法可與第3實施方式相同。因此，第4實施方式能夠獲得與第3實施方式相同之效果。
(第5實施方式)
圖19及圖20係表示第5實施方式之半導體裝置1之製造方法及構成之一例之剖視圖。圖19表示半導體裝置1之製造中途之構成，且表示了與第1實施方式之圖9對應之狀態。圖20表示了完成後之半導體裝置1之構成。
於第5實施方式中，虛設構件80於其側面F80c具有傾斜。側面F80c自相對於第1面F10a垂直之方向傾斜。利用虛設構件80之側面F80c之傾斜，而自第1面F10a之上方觀察時之面積根據虛設構件80之研磨面之高度位置而不同，藉此，虛設構件80之研磨面積變化。研磨裝置由於基於虛設構件80之研磨面積之變化而研磨阻力變化，故而能夠特定出正在研磨之虛設構件80之研磨面之高度。若預先設定虛設構件80之上表面F80a之面積及側面F80c之傾斜，則能夠控制研磨中之虛設構件80之剩餘膜厚(第3絕緣膜90之剩餘膜厚)。
於第5實施方式中，由於虛設構件80之側面F80c成為連續之傾斜面，故而能夠更細地控制第3絕緣膜90之厚度。第5實施方式之其他構成及製造方法可與第3或第4實施方式相同。因此，第5實施方式能夠獲得與第3或第4實施方式相同之效果。
再者，虛設構件80例如可係使三角錐、四角錘、多角錘、圓錐等任 一個上部平坦之形狀。虛設構件80例如能夠藉由將半導體晶圓自相對於其表面傾斜之方向切割來形成。
(第6實施方式)
圖21係表示第6實施方式之半導體裝置1之構成之一例之剖視圖。於第6實施方式中，再配線層(RDL(Redistribution Layer))120設置於第3絕緣膜90上。再配線層120設置於第3絕緣膜90、柱狀電極60及虛設構件80上，且具有配線層121與絕緣層122積層而成之多層配線結構。配線層121例如使用Ti、TiN、Cr、CrN、Cu、Ni、Au、Pd、W、Al、Ag等單體、其等之中2種以上之複合膜、或者其等之中2種以上之合金。絕緣層122例如使用酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、環氧系、PBO系、矽酮系、苯并環丁烯系等樹脂、其等之中2種以上之複合膜、或者其等之中2種以上之化合物。柱狀電極60電性連接於配線層121之一部分。金屬凸塊100設置於配線層121之電極墊上，且電性連接於配線層121之一部分。藉此，電極凸塊100經由再配線層120而電性連接於柱狀電極60及半導體元件之任一個。藉由使用再配線層120，能夠提高柱狀電極60之配置自由度。進而，與圖12所示之結構同樣地，第6實施方式之半導體裝置1亦可搭載於配線基板200上。
第6實施方式之其他構成可與第1實施方式之對應之構成相同。藉此，第6實施方式能夠獲得與第1實施方式相同之效果。又，第6實施方式亦可與第2~第5實施方式之任一個實施方式組合。
(第7實施方式)
圖22~圖24係表示第7實施方式之半導體裝置1之製造方法及構成之一例之剖視圖。圖22及圖23表示半導體裝置1之製造中途之構成。圖24表示了完成後之半導體裝置1之構成。
於第6實施方式中，再配線層120設置於柱狀電極60及虛設構件80上。相對於此，於第7實施方式中，再配線層120設置於柱狀電極60及虛設構件80之下。
對第7實施方式之製造方法更詳細地進行說明。
於經過圖2~圖7所示之工序之後，利用絕緣膜85被覆電極55及第2絕緣膜40。再者，於第7實施方式中，由於障壁金屬50及柱狀電極60形成於再配線層120上，故而圖7之障壁金屬50及柱狀電極60於此處分別稱為障壁金屬45及電極55。又，於該階段中，不形成虛設構件80。絕緣膜85為使用酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、環氧系、PBO(p-phenylenebenzobisoxazole)系、矽酮系、苯并環丁烯系等樹脂、或該等樹脂之混合材料、複合材料等之第3絕緣膜90。又，障壁金屬45及電極55之材料可分別與障壁金屬50及柱狀電極60之材料相同。
於利用絕緣膜85被覆電極55及第2絕緣膜40之後，藉由曝光、顯影等微影，使電極55露出。藉此，獲得圖22之結構。
接下來，如圖23所示，於電極55及絕緣膜85上，形成再配線層120。
然後，如第1實施方式中所說明，將障壁金屬50、柱狀電極60形成於配線層121上，將虛設構件80利用樹脂層70接著於絕緣層122上。將柱狀電極60及虛設構件80利用第3絕緣膜90埋入，對第3絕緣膜90進行研磨直至虛設構件80露出為止。將金屬凸塊100形成於柱狀電極60上。藉此，完成圖24所示之半導體裝置1。
如此，再配線層120亦可設置於柱狀電極60及虛設構件80之下。金屬凸塊100及柱狀電極60經由再配線層120而與半導體晶片10之半導體元件之任一個電性連接。於該情形時，柱狀電極60、虛設構件80及金屬凸塊100之佈局配置之自由度變高。
第7實施方式之其他構成及製造方法可與第6實施方式之對應之構成及製造方法相同。藉此，第7實施方式亦能夠獲得第6實施方式之效果。又，第7實施方式亦可與第2~第5實施方式之任一個實施方式組合。
(第8實施方式)
圖25係表示第8實施方式之半導體裝置1之構成之一例之剖視圖。於第8實施方式中，柱狀電極60使用金屬線利用打線接合法來形成之方面與第1實施方式不同。以下，亦將柱狀電極60稱為金屬線60。於由金屬線構成柱狀電極60之情形時，金屬線60利用打線接合法接合於電極墊30上。於該情形時，金屬線60之直徑(寬度)Φ3小於自第1絕緣膜20、40露出之電 極墊30之開口徑Φ1。又，自第3絕緣膜90露出之金屬線60之面積，小於金屬線60對於半導體晶片10之接觸面積(接合面積)。進而，金屬線60由於能夠利用打線接合法形成，故而與利用鍍覆法形成之電極相比製造成本低廉。於柱狀電極60使用金屬線之情形時，獲得此種特徵。金屬線60之材料使用Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al等單體、其等之中2種以上之複合膜、或者其等之中2種以上之合金等低電阻金屬。例如亦可係對Cu被覆Pd而成之材料。為了於形成第3絕緣膜90時不使金屬線60倒塌，較佳為金屬線60使用相對較硬之Cu、CuPd合金、對Cu被覆Pd而成之材料。
對第8實施方式之製造方法進行說明。
於經過圖2所示之工序之後，使用打線接合機，將金屬線60之一端接合於電極墊30。接下來，將金屬線60向第1面F10a之上方向大致垂直方向拉出並切斷。藉此，金屬線60形成為於相對於第1面F10a大致垂直之方向直立之柱狀電極。然後，與第1實施方式同樣地，形成虛設構件80、第3絕緣膜90及金屬凸塊100。亦可於金屬線60露出之後，於形成大於露出面之電極墊之後，形成金屬凸塊100。藉此，完成圖25所示之半導體裝置1。
於第8實施方式中，由於柱狀電極60使用金屬線利用打線接合法形成，故而能夠較鍍覆法低廉且簡單地形成。第8實施方式之其他構成及製造方法可與第1實施方式之對應之構成及製造方法相同。因此，第8實施方 式亦能夠獲得與第1實施方式相同之效果。第8實施方式亦可與第1~第7實施方式之任一個實施方式組合。
(第9實施方式)
圖26係表示第9實施方式之半導體裝置1之構成之一例之剖視圖。於第9實施方式中，柱狀電極60包含利用鍍覆法之柱狀電極60a及利用打線接合法之柱狀電極(金屬線)60b這兩者之方面與第1實施方式不同。即，於柱狀電極60中利用鍍覆法之柱狀電極60a與利用打線接合法之柱狀電極60b混合存在。
自第3絕緣膜90露出之柱狀電極60a之面積，亦可大於柱狀電極60a對於半導體晶片10之接觸面積。另一方面，自第3絕緣膜90露出之柱狀電極60b之面積，亦可小於柱狀電極60b對於半導體晶片10之接觸面積。
即，利用鍍覆法之柱狀電極60a之直徑Φ2亦可大於自第1絕緣膜20、40露出之電極墊30之開口徑Φ1。利用接合法之金屬線60b之直徑Φ3亦可小於自第1絕緣膜20、40露出之電極墊30之開口徑Φ1。
第9實施方式之其他構成及製造方法可與第1實施方式之對應之構成及製造方法相同。因此，第9實施方式亦能夠獲得與第1實施方式相同之效果。第9實施方式亦可與第1~第7實施方式之任一個實施方式組合。
(第10實施方式)
圖27係表示第10實施方式之半導體裝置1之構成之一例之剖視圖。於第10實施方式中，虛設構件80為導電體，於虛設構件80之下設置有電極墊30及障壁金屬50。虛設構件80接觸於障壁金屬50，且經由障壁金屬50而電性連接於電極墊30及半導體晶片10之半導體元件之任一個。
於第10實施方式中，虛設構件80兼備作為研磨擋止層之功能及作為電極之功能。虛設構件80亦可作為電源電極將電力供給至半導體晶片10。例如，亦可將虛設構件80使用焊料或導電膏等連接。或者，虛設構件80亦可作為接地電極對半導體晶片10供給接地電壓。進而，虛設構件80亦可具有作為吸收半導體晶片10之熱並釋放之散熱板之功能。
第10實施方式之其他構成及製造方法可與第1實施方式之對應之構成及製造方法相同。因此，第10實施方式亦能夠獲得與第1實施方式相同之效果。第10實施方式亦可與第1~第9實施方式之任一個實施方式組合。
以下，對半導體晶片10之積層體之封裝之實施方式進行說明。
(第11實施方式)
圖28係表示第11實施方式之半導體裝置1之構成之一例之剖視圖。於第11實施方式中，積層有複數個半導體晶片10，柱狀電極60自各半導體晶片10向相對於半導體晶片10之表面大致垂直之方向延伸。於半導體晶片10之積層體上配置虛設構件80，虛設構件80之上表面處於較最上段之半導體晶片10之表面高之位置。因此，最上段之半導體晶片10之表面不 自第3絕緣膜90露出，而由第3絕緣膜90被覆。
複數個半導體晶片10例如亦可係NAND型快閃記憶體之記憶體晶片或搭載有任意之LSI之半導體晶片。複數個半導體晶片10既可為具有相同構成之半導體晶片，亦可係具有分別不同之構成之半導體晶片。例如，複數個半導體晶片10之中最上段之半導體晶片10為控制記憶體晶片之控制器晶片，其他半導體晶片10可係記憶體晶片。半導體晶片10利用接著層12而相互接著。於半導體晶片10中，表面F10a成為形成有半導體元件之元件形成面。表面F10a之相反側之背面F10b利用接著層12接著於其他半導體晶片10。
接著層12為了將複數個半導體晶片10積層，而設置於半導體晶片10間。接著層12例如使用包含酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、環氧系、PBO(p-phenylenebenzobisoxazole)系、矽酮系、苯并環丁烯系等樹脂、或該等樹脂之混合材料、複合材料之DAF(Die Attach Film)或DAP(Die Attach Paste)。
柱狀電極60向相對於半導體晶片10之表面F10a大致垂直之方向延伸，且連接於各半導體晶片10。柱狀電極60之一端連接於半導體晶片10之電極墊P10，另一端連接於金屬凸塊100。例如，半導體晶片10階梯狀地錯開積層，柱狀電極60自設置於複數個半導體晶片10端部之階差部分之各電極墊P10延伸。藉此，各半導體晶片10能夠經由柱狀電極60而連接於金屬凸塊100，且不經由其他半導體晶片10，與再配線層或外部裝置直 接交換信號。其結果，能夠使半導體晶片10與控制器等之間之通信資料量或通信速度增大。柱狀電極60例如既可為用於接合線之金屬線，亦可係利用鍍覆法形成之柱狀電極。例如，亦可如下所述，最上段之半導體晶片10之柱狀電極60係利用鍍覆法形成之柱狀電極，其下方之半導體晶片10之柱狀電極60由用於接合線之金屬線構成。柱狀電極60例如使用Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al等單體、其等之中2種以上之複合膜、或者其等之中2種以上之合金等低電阻金屬。
虛設構件80利用樹脂層70貼附於複數個半導體晶片10之積層體上，且配置於最上段之半導體晶片10之旁邊。虛設構件80之上表面處於較最上段之半導體晶片10之表面高之位置，且作為第3絕緣膜90之研磨擋止層發揮功能。
第3絕緣膜90被覆並保護半導體晶片10及柱狀電極60。第3絕緣膜90被覆最上段之半導體晶片10之表面使其不露出。
金屬凸塊100設置於柱狀電極60上，用來與其他元件取得電性之連接。金屬凸塊100例如使用以Sn為主成分之焊料等低電阻金屬。亦可於露出金屬線60後，於形成大於露出面之電極墊之後，形成金屬凸塊100。
接下來，對第11實施方式之半導體裝置1之製造方法進行說明。
圖29~圖31係表示第11實施方式之半導體裝置1之製造方法之一例之 剖視圖。
首先，如圖29所示，於支持基板5上積層複數個半導體晶片10。此時，半導體晶片10利用接著層12接著於其他半導體晶片10上。
接下來，將虛設構件80利用樹脂層70接著於半導體晶片10之積層體上。此時，虛設構件80之上表面定位得較最上層之半導體晶片10之上表面高。
接下來，如圖30所示，於半導體晶片10之電極墊P10上利用打線接合法將金屬線接合，向相對於第1面F10a大致垂直之方向拉出而形成柱狀電極60。再者，亦可改變幾個金屬線之柱狀電極60之材料，來代替虛設構件80使用。
接下來，如圖31所示，利用第3絕緣膜90被覆半導體晶片10之積層體、虛設構件80及柱狀電極60。例如，第3絕緣膜90為模塑樹脂，並將半導體晶片10之積層體、虛設構件80及柱狀電極60利用該樹脂密封。接下來，使第3絕緣膜90硬化。
接下來，使用機械研磨法、CMP法等，對第3絕緣膜90進行研磨直至虛設構件80露出為止。接下來，將支持基板5去除之後，於柱狀電極60上形成金屬凸塊100。金屬凸塊100例如只要使用球搭載、鍍覆法、印刷法即可。藉此，完成圖28所示之半導體裝置1。又，亦可於形成金屬凸塊 100之後將支持基板5去除。
再者，如下所述，柱狀電極60亦可利用鍍覆法形成。於該情形時，於形成第3絕緣膜90之後，使用微影技術及蝕刻技術，於第3絕緣膜90形成達到電極墊30之孔。進而，於該孔利用鍍覆法埋入金屬。如此，亦可形成柱狀電極60。又，亦可於半導體晶片10預先利用鍍覆法等形成柱狀電極60，搭載半導體晶片10。又，亦可將支持基板5自半導體裝置1去除，但亦可於半導體裝置1作為散熱板殘留。
又，半導體裝置1亦可搭載於配線基板200。圖32係表示將第11實施方式之半導體裝置1安裝於配線基板200上之狀態之剖視圖。半導體裝置1將金屬凸塊100朝向配線基板200安裝，經由金屬凸塊100而與配線基板200之配線之一部分電性連接。藉此，半導體裝置1可與其他半導體裝置一起模組化。金屬凸塊100亦可形成於配線基板200上。於該情形時，將柱狀電極60之露出面與形成於配線基板200之金屬凸塊100連接。
(第12實施方式)
圖33係表示第12實施方式之半導體裝置1之構成之一例之剖視圖。於第12實施方式中，虛設構件80為導電體，於虛設構件80上設置有金屬凸塊100。虛設構件80經由金屬凸塊100而電性連接於配線基板200之配線之一部分。虛設構件80兼備作為研磨擋止層之功能及作為電極之功能。虛設構件80亦可作為電源電極將電力供給至半導體晶片10。或者，虛設構件80亦可作為接地電極對半導體晶片10供給接地電壓。進而，虛設構件80 亦具有作為吸收半導體晶片10之熱並釋放之散熱板之功能。
進而，於半導體晶片10之積層體之中最下段之半導體晶片10(於圖33中最上方所示之半導體晶片10)之背面F10b殘置支持基板5。支持基板5接觸於最下段之半導體晶片10之背面F10b，作為散熱板發揮功能。又，支持基板5亦可作為接地電極對半導體晶片10供給接地電壓。支持基板5例如亦可係金屬等導電體或包含導熱性之材料之引線框架。
第12實施方式之其他構成及製造方法可與第11實施方式之對應之構成及製造方法相同。因此，第12實施方式亦能夠獲得與第11實施方式相同之效果。
(第13實施方式)
圖34係表示第13實施方式之半導體裝置1之構成之一例之剖視圖。於第13實施方式中，進而設置有虛設構件81之方面與第11實施方式不同。虛設構件81貫通第3絕緣膜90而設置於半導體晶片10之積層方向，且與半導體晶片10之積層體相鄰而設置。虛設構件81由與虛設構件80相同之材料構成，且較第3絕緣膜90及柱狀電極60硬。藉由追加虛設構件81，能夠進而抑制半導體裝置1之封裝之翹曲。
虛設構件81於形成第3絕緣膜90之前之圖29或圖30之工序中，以直立於支持基板5上之方式配置虛設構件81。虛設構件80、81之高度較佳為大致相等。然後，如第11實施方式中所說明，利用第3絕緣膜90埋入半導體 晶片10，對第3絕緣膜90進行研磨。此時，虛設構件80、81成為研磨擋止層。第13實施方式之其他構成及製造方法可與第11實施方式之對應之構成及製造方法相同。第13實施方式亦可與第1~第12實施方式之任一個實施方式組合。
(變化例1)
於將熔融之樹脂流入至模具而形成第3絕緣膜90之情形時，樹脂較佳為自圖31之箭頭A1所示之方向流入。箭頭A1之方向為自半導體晶片10之積層體觀察柱狀電極60存在之方向，利用半導體晶片10之積層體來緩和樹脂之流動，抑制直接影響柱狀電極60。藉此，藉由樹脂之流動，能夠抑制柱狀電極60倒塌或彎曲。
圖35係表示變化例1之樹脂密封工序之情況之圖。將熔融之樹脂自插入口410向箭頭A1方向導入，封入至模具400、401內。此時，密封之半導體晶片10之積層體以保護柱狀電極60之方式位於較柱狀電極60靠上游側，抑制柱狀電極60倒塌或彎曲。
(變化例2)
圖36係表示變化例2之樹脂密封工序之情況之圖。於將熔融之樹脂流入至模具400、401而形成第3絕緣膜90之情形時，於模具400、401之內面設置有脫模膜420。脫模膜420係為了將樹脂密封之半導體晶片10自模具卸除而設置，且由樹脂等構成。
於變化例2中，表示了利用壓縮成形法之樹脂密封之例子。於模具400、401內配置脫模膜420，於其中塗佈樹脂。然後，將形成有柱狀電極60之半導體晶片10反轉後放入至樹脂內，進行壓縮成形。柱狀電極60物理地刺入至模具400、401內之脫模膜420。柱狀電極60既可壓入至脫模膜420，或者亦可貫通。藉此，於樹脂密封工序中，能夠將柱狀電極60之兩端固定，抑制柱狀電極60因樹脂之流動而倒塌或彎曲。
脫模膜420之拉伸強度例如較佳為1MPa~100MPa。若脫模膜420之拉伸強度低於1MPa，則脫模膜420難以固定柱狀電極60。若脫模膜420之拉伸強度高於100MPa，則難以將柱狀電極60刺入至脫模膜420。因此，藉由使脫模膜420之拉伸強度為1MPa~100MPa，於樹脂密封工序中，脫模膜420能夠抑制柱狀電極60之倒塌或彎曲。
(第14實施方式)
圖37係表示第14實施方式之半導體裝置1之構成例之剖視圖。於第14實施方式中，柱狀電極60包含利用接合線之柱狀電極60a與利用鍍覆法形成之柱狀電極60b這兩者。例如，於最上段之半導體晶片10b上，利用鍍覆法形成柱狀電極60b。於除此以外之半導體晶片10a上，利用打線接合法形成柱狀電極60a。半導體晶片10a例如為記憶體晶片，半導體晶片10b例如為控制器晶片。
圖38~圖40係表示第14實施方式之半導體裝置1之製造方法之一例之剖視圖。柱狀電極60a係參照圖29~圖31所說明般地形成。藉此，獲得圖 38所示之結構。然後，如圖39所示，使用雷射加工技術等，削掉第3絕緣膜90之柱狀電極60b之形成位置。藉此，於第3絕緣膜90形成孔H60b。孔H60b自第3絕緣膜90之上表面，形成至半導體晶片10b之電極墊P10為止。
接下來，於將障壁金屬形成於半導體晶片10b之電極墊P10上之後，如圖40所示，使用鍍覆法，將柱狀電極60b之金屬材料填埋於孔H60b。藉此，形成柱狀電極60b。又，亦可於半導體晶片10預先利用鍍覆法等形成柱狀電極60之後，搭載半導體晶片10。
然後，使用機械研磨法、CMP法，對第3絕緣膜90及柱狀電極60a、60b進行研磨，直至虛設構件80露出為止。進而，藉由將金屬凸塊100形成於柱狀電極60a、60b上，完成圖37所示之半導體裝置1。
(第15實施方式)
圖41係表示第15實施方式之半導體裝置1之構成例之剖視圖。於變化例3中，柱狀電極60a、60b自第3絕緣膜90之表面向金屬凸塊100突出。藉由將柱狀電極60a、60b向金屬凸塊100刺入，而於將半導體裝置1向配線基板200覆晶連接時，半導體裝置1相對於配線基板200穩定地連接，有助於抑制不良。
柱狀電極60a、60b之突出形狀能夠藉由於對第3絕緣膜90進行研磨之後，進而利用等離子體等僅對第3絕緣膜90進行蝕刻而形成。虛設構件80 亦成為突出之形狀。
第15實施方式之其他構成可與第14實施方式之對應之構成相同。第15實施方式亦可與第12~第13實施方式之任一個實施方式組合。
(第16實施方式)
圖42係表示第16實施方式之半導體裝置1之構成例之剖視圖。第16實施方式之半導體裝置1進而具備虛設柱狀電極60c、60d。虛設柱狀電極60c之一端接合於支持基板5，另一端設置到第3絕緣膜90之表面為止。虛設柱狀電極60d之一端接合於半導體晶片10之任一個，另一端設置到第3絕緣膜90之表面為止。於虛設柱狀電極60c、60d之另一端設置有金屬凸塊100，且連接於配線基板200。虛設柱狀電極60c、60d於柱狀電極60偏向半導體裝置1一側之情形時，設置於半導體裝置1之另一側。藉此，半導體裝置1與配線基板200之間之金屬凸塊100之配置位置相對均勻，溫度循環試驗中之應力得到緩和。其結果，有助於提高可靠性。再者，虛設柱狀電極60c、60d既可電性連接於半導體晶片10及配線基板200，或者亦可不連接於半導體晶片10及配線基板200。
虛設柱狀電極60c、60d之佈局配置、數量以半導體裝置1與配線基板200之間之金屬凸塊100之配置位置相對均勻之方式設定。又，虛設柱狀電極60c、60d之直徑、材質與柱狀電極60a、60b之直徑、材質可相同，亦可不同。例如，亦可將虛設柱狀電極60c、60d之材料改變為柱狀電極60a、60b之材料，使其發揮虛設構件80之作用。第16實施方式之其他構 成可與第15實施方式之對應構成相同。第16實施方式亦可與第12~第13實施方式之任一個實施方式組合。
(第17實施方式)
圖43係表示第17實施方式之半導體裝置1之構成例之剖視圖。圖44係表示第17實施方式之半導體裝置1之構成例之俯視圖。根據第17實施方式，複數個虛設柱狀電極60c設置於半導體裝置1之兩側或角部。虛設柱狀電極60c之構成可與第16實施方式之構成相同。藉此，與第16實施方式同樣地，半導體裝置1與配線基板200之間之金屬凸塊100之配置位置相對均勻化，溫度循環試驗中之應力得到緩和。其結果，有助於提高可靠性。又，虛設柱狀電極60c於將半導體裝置1向配線基板200覆晶連接時，可成為對準標記。
虛設柱狀電極60c之佈局配置、數量並不限定於此，只要以半導體裝置1與配線基板200之間之金屬凸塊100之配置位置相對均勻化之方式設定即可。又，複數個虛設柱狀電極60c之直徑、材質既可相互相同，亦可不同。第17實施方式之其他構成可與第14實施方式之對應之構成相同。第17實施方式亦可與第12~第13實施方式之任一個實施方式組合。
(第18實施方式)
圖45係表示第18實施方式之半導體裝置1之構成例之剖視圖。根據第18實施方式，於第3絕緣膜90之表面設置有凹部130，於凹部130內設置有金屬凸塊100。藉由將金屬凸塊100形成於凹部130內，即便金屬凸塊100 因回流焊等熔融，亦能夠使金屬凸塊100滯留於凹部130內。因此，金屬凸塊100能夠將柱狀電極60與配線基板200之間確實地連接。第18實施方式之其他構成可與第14實施方式之對應之構成相同。又，凹部130只要於經過圖31之工序之後，對第3絕緣膜90進行研磨，使用微影技術及蝕刻技術或雷射加工技術，將柱狀電極60之周圍之第3絕緣膜90去除即可。第18實施方式亦可與第12~第17實施方式之任一個實施方式組合。
(第19實施方式)
圖46係表示第19實施方式之半導體裝置1之構成例之剖視圖。根據第19實施方式，柱狀電極60於第3絕緣膜90內，自相對於第1面F10a垂直之方向傾斜地設置。柱狀電極60隨著自相對於半導體晶片10之連接部接近第3絕緣膜90之表面，而自半導體裝置1之中心部向外側擴展，柱狀電極60間之間隔亦擴展。藉此，擴大配線基板200中之配線間隔，配線基板200之配線之設計之自由度變高。第19實施方式之其他構成可與第14實施方式之對應之構成相同。第19實施方式亦可與第12~第18實施方式之任一個實施方式組合。
(第20實施方式)
圖47係表示第20實施方式之半導體裝置1之構成例之剖視圖。根據第20實施方式，柱狀電極60於第3絕緣膜90內自相對於第1面F10a垂直之方向傾斜地設置之方面與第19實施方式相同。然而，於第20實施方式中，柱狀電極60隨著自相對於半導體晶片10之連接部接近第3絕緣膜90之表面，自半導體裝置1之中心部朝向內側變窄，柱狀電極60間之間隔亦變 窄。藉此，例如，作為控制器之半導體晶片10b與作為記憶體晶片之其他半導體晶片10a之間之配線距離變短，半導體裝置1之電特性得到改善。第20實施方式之其他構成可與第14實施方式之對應之構成相同。第20實施方式亦可與第12~第18實施方式之任一個實施方式組合。
(第21實施方式)
圖48係表示第21實施方式之半導體裝置1之構成例之剖視圖。根據第21實施方式，柱狀電極60於第3絕緣膜90內自相對於第1面F10a垂直之方向傾斜且彎曲地設置之方面與第19實施方式不同。柱狀電極60之彎曲較佳為以於導入第3絕緣膜90時柱狀電極60不受影響之方式，彎曲為能夠增強柱狀電極60之形狀。例如，柱狀電極60亦可向與圖31之A1方向大致平行之方向回折而成形為Z型。藉此，柱狀電極60成為彈簧狀，能夠相對於第3絕緣膜90之流動獲得機械性之耐性。第21實施方式之其他構成可與第19實施方式之對應之構成相同。第21實施方式亦可與第12~第18實施方式之任一個實施方式組合。
(第22實施方式)
圖49~圖52係表示第22實施方式之半導體裝置1之構成例之剖視圖。根據圖49及圖50之第22實施方式，半導體裝置1於配線基板200上，由底部填充膠510及絕緣材料500被覆。底部填充膠510填充至半導體裝置1與配線基板200之間，被覆且保護金屬凸塊100之周圍。藉此，半導體裝置1與配線基板200之連接部之可靠性提高。底部填充膠510例如使用樹脂。絕緣材料500以被覆半導體裝置1及底部填充膠510之整體之方式設置。絕 緣材料500保護半導體裝置1及底部填充膠510。絕緣材料500例如與第3絕緣膜90同樣地使用樹脂。藉此，半導體裝置1之可靠性進而提高。第22實施方式之其他構成可與第14實施方式之對應之構成相同。
又，絕緣材料500亦可如圖49所示，設置至支持基板5之上為止，被覆支持基板5，但亦可如圖50所示，以使支持基板5之上表面露出之方式設置。於該情形時，能夠提高支持基板5之散熱性。
絕緣材料500及底部填充膠510亦可僅設置一者。例如，亦可如圖51及圖52所示，省略底部填充膠510，絕緣材料500被覆半導體裝置1。於該情形時，代替底部填充膠而將絕緣材料500填埋於半導體裝置1與配線基板200之間，被覆並保護金屬凸塊100。第22實施方式亦可與上述實施方式之任一個實施方式組合。
圖28至圖52中表示了使用線作為柱狀電極60之例子。當然，亦可如通常之使用打線接合法之製品般，將晶片間直接連接之線與使用線之柱狀電極60混合存在。又，亦可將晶片間直接連接之線與使用線之柱狀電極60、應用鍍覆法等之柱狀電極60混合存在。
(第23實施方式)
圖53係表示第23實施方式中之半導體裝置1之構成例之剖視圖。第23實施方式於將複數個虛設構件80配置於一個半導體晶片10內之方面與第1實施方式不同。第23實施方式之其他構成可與第1實施方式之對應之構成 相同。藉由配置複數個虛設構件80，而複數個虛設構件80更加能夠發揮作為擋止層之作用，並且亦能夠調整半導體裝置1之翹曲。其結果，能夠提高可靠性。
(第24實施方式)
圖54係表示第24實施方式中之半導體裝置1之構成例之剖視圖。第24實施方式於進而具備配置於再配線層120內之虛設構件80之方面與第6實施方式不同。第24實施方式之其他構成可與第6實施方式之對應之構成相同。藉由除了虛設構件80以外將虛設構件80配置於再配線層120內，能夠調整半導體裝置1之翹曲。其結果，能夠提高可靠性。亦可將複數個虛設構件80配置於再配線層120內之複數個配線層間。藉此，進而能夠調整半導體裝置1之翹曲。
(第25實施方式)
圖55係表示第25實施方式中之半導體裝置1之構成例之剖視圖。第25實施方式於半導體裝置1之柱狀電極60上具備再配線層120之方面與第11實施方式不同。再配線層120於對第3絕緣膜90進行研磨之後，形成於第3絕緣膜90及柱狀電極60上。金屬凸塊100形成於再配線層120上。藉由設置再配線層120，即便於柱狀電極60間之間距狹窄之情形時，亦能夠擴大金屬凸塊100間之間距。進而，再配線層120能夠將半導體晶片10間經由再配線層120內之配線而電性連接。亦可於再配線層120內形成虛設構件80。又，亦可設置複數個再配線層120，於複數個再配線層120內形成虛設構件80。
(第26實施方式)
圖56係表示第26實施方式中之半導體裝置1之構成例之剖視圖。本實施方式為將半導體裝置1應用於所謂扇出型晶圓級CSP(Chip Size Package，晶片尺寸封裝)之例子。扇出型晶圓級CSP之製程大致分為RDL Last與RDL First。RDL Last為於將半導體晶片利用第4絕緣膜(絕緣材料)150覆蓋之後形成再配線層120之方式，RDL First為於將半導體晶片利用第4絕緣膜150覆蓋之狀態之前形成再配線層120之方式。第4絕緣膜150使用環氧系、酚系、聚醯亞胺系、聚醯胺系、丙烯酸系、PBO系、矽酮系、苯并環丁烯系等樹脂、該等樹脂之混合材料、複合材料。作為環氧樹脂之例子並不特別限定，例如，可列舉雙酚A型、雙酚F型、雙酚AD型、雙酚S型等雙酚型環氧樹脂、酚系酚醛清漆、甲酚酚醛清漆型等酚醛清漆型環氧樹脂、間苯二酚型環氧樹脂、三酚甲三縮水甘油醚等芳香族環氧樹脂、萘型環氧樹脂、茀型環氧樹脂、二環戊二烯型環氧樹脂、聚醚改性環氧樹脂、二苯甲酮型環氧樹脂、苯胺型環氧樹脂、NBR改性環氧樹脂、CTBN改性環氧樹脂、及該等樹脂之氫化物等。其中，自與Si之密接性良好之方面而言，較佳為萘型環氧樹脂、二環戊二烯型環氧樹脂。又，自容易獲得速硬化性之方面而言，較佳為二苯甲酮型環氧樹脂。該等環氧樹脂既可單獨使用，亦可將2種以上一併使用。又，亦可於第3絕緣膜90中包含二氧化矽等填料。
圖56表示於RDL Last中於再配線層120形成虛設構件80之例子。於RDL Last方式中，於支持基板上形成剝離層，然後搭載半導體晶片10， 利用第4絕緣膜150覆蓋半導體晶片10。然後將支持基板剝離，將再配線層120形成於半導體晶片10之元件面。於形成柱狀電極60之後，形成第3絕緣膜90，將第3絕緣膜90利用機械研磨法、CMP等平坦化。於該情形時，直至使柱狀電極60露出為止對第3絕緣膜90進行研磨，此時，虛設構件80作為擋止層發揮功能。於半導體晶片10之周圍存在第4絕緣膜150，於半導體晶片10之元件面形成再配線層120。再配線層120設置於半導體晶片10之第1面F10a、及與該第1面F10a為同一平面之第4絕緣膜150上。於再配線層120內形成虛設構件80，於再配線層120上形成金屬凸塊100。金屬凸塊100電性連接於配線基板200。藉由於包含扇出型晶圓級CSP之第3絕緣膜之再配線層120內設置虛設構件80，能夠進行半導體裝置1之翹曲之矯正，從而能夠提高可靠性。
(第27實施方式)
圖57係表示第27實施方式中之半導體裝置1之構成例之剖視圖。於圖56之形態中，於第3絕緣膜90內設置有複數個虛設構件80。第27實施方式之其他構成可與第26實施方式之對應之構成相同。藉由增加虛設構件80，能夠調整半導體裝置1之翹曲，進而能夠提高可靠性。又，亦可於複數個再配線層120內形成虛設構件80。第27實施方式亦可與其他實施方式組合。
(第28實施方式)
圖58係表示第28實施方式中之半導體裝置1之構成例之剖視圖。本實施方式為將半導體裝置1應用於所謂扇出型晶圓級CSP之例子。圖56表示 於RDL First中於第3絕緣膜90形成虛設構件80之例子。於RDL First方式中，於支持基板上形成剝離層，形成柱狀電極60。於將虛設構件80搭載於剝離層上之後，以覆蓋柱狀電極60、虛設構件80之方式形成第3絕緣膜90，利用機械研磨法、CMP等平坦化。於該情形時，直至使柱狀電極60露出為止對第3絕緣層90進行研磨，此時，虛設構件80作為擋止層發揮功能。於虛設構件80上進而存在再配線層120，於半導體晶片10之周圍存在第4絕緣膜150。半導體晶片10具有金屬凸塊100A，且覆晶安裝於再配線層120。於第3絕緣膜90形成虛設構件80，形成金屬凸塊100B。金屬凸塊100B電性連接於配線基板200。藉由於包含扇出型晶圓級CSP之第3絕緣膜90之再配線層120內設置虛設構件80，能夠進行半導體裝置1之翹曲之矯正，從而能夠提高可靠性。再者，於將再配線層自支持基板剝離之後，對第3絕緣膜90進行研磨，而使柱狀電極60露出。虛設構件80自上下兩者被研磨，故而發揮作為來自兩者之研磨之擋止層之作用。
(第29實施方式)
圖59係表示第29實施方式中之半導體裝置1之構成例之剖視圖。第29實施方式於半導體晶片10與再配線層120之間具備底部填充膠510之方面與第28實施方式不同。底部填充膠510被覆並保護半導體晶片10與再配線層120之間之金屬凸塊100A之周圍。藉此，提高半導體晶片10與再配線層120之連接部之可靠性。
(第30實施方式)
圖60A、圖60B、圖60D係表示第30實施方式中之研磨裝置之構成例 之圖。
圖60A所示之研磨裝置具備轉盤300、研磨墊310、旋轉軸320、馬達330、電流感測器340、信號轉換器350、及運算部360。
轉盤300能夠旋轉地設置，且於表面上搭載研磨墊310。
研磨墊310設置於轉盤300上，對半導體基板W進行研磨。
旋轉軸320固定於轉盤300，將來自馬達330之動力傳遞至轉盤300，使轉盤300旋轉。
馬達330接收來自未圖示之電源之電力，使旋轉軸320按照箭頭A旋轉。
電流感測器340測定由馬達330消耗之電流。
信號轉換器350轉換由電流感測器340測定出之馬達330之消耗電流值，並發送給運算部360。
運算部360例如為PC(Personal Computer，個人電腦)，根據馬達330之消耗電流進行半導體基板W之研磨處理之終點偵測。更詳細而言，馬達330之消耗電流根據半導體基板W與研磨墊310之間之摩擦而變化。半導體基板W與研磨墊310之間之摩擦根據半導體基板W之平坦化前後之接觸面積之變化或者正在研磨之膜種之變化而變化。能夠利用馬達330之消耗電力來偵測此種摩擦變化。此種研磨終點偵測方法亦稱為TCM(Torque Current Monitor，轉矩電流監測器)。
圖60B所示之研磨裝置與圖60A形態之不同點在於，進而具備渦電流感測器370。圖60B之研磨裝置之其他構成可與圖60A之研磨裝置之對應構成相同。再者，亦可省略圖60A之電流監測器340。
如圖60C所示，渦電流感測器370由線圈構成，檢測由半導體基板W 產生之感應電流(渦電流)。運算部360根據該渦電流引起之阻抗頻率或電壓等之變化而運算研磨處理之終點。圖60C係表示渦電流感測器370之概略性構成之概念圖。
此種研磨終點偵測方法亦稱為ECM(Eddy Current Monitor，渦電流監測器)。
圖60D所示之研磨裝置與圖60A形態之不同點在於，進而具備反射光感測器380。圖60D之研磨裝置之其他構成可與圖60A之研磨裝置之對應構成相同。再者，亦可省略圖60A之電流監測器340。
如圖60D所示，反射光感測器380將光照射至半導體基板W，檢測來自半導體基板W之反射光，求出反射率。運算部360根據反射率之變化而偵測研磨處理之終點。
此種研磨終點偵測方法亦稱為OTM(Optical Thickness Monitor，光學厚度監測器)。
圖60A中所說明之根據研磨阻力之變化進行之終點檢測方法與上述實施方式中所使用之CMP之檢測方法對應。
於使用圖60D中所說明之根據反射率之變化進行之光學式終點檢測方法之情形時，只要虛設構件80、81之反射率或透過率與第3絕緣膜90不同即可。一般而言，由於第3絕緣膜90多為暗色，故而虛設構件80、81之反射率亦可相對於測定波長更高。
雖然已經描述了某些實施例，但是該等實施例僅以實例方式呈現，且不意欲限制本發明之範圍。事實上，本文中所述之新穎方法和系統可以各種其他形式體現；再者，本文中所述之方法和系統之形式可進行各種省略、替代和變化而不會脫離本發明之精神。隨附申請專利範圍及其對等物 意欲涵蓋上述形式或修改，這將處於本發明之範圍和精神內。
相關申請案之引用
本申請案基於2020年07月7日提出申請之先行之日本專利申請案第2020-117274號之優先權而主張優先權利益，藉由引用將其全部內容併入本文中。
1:半導體裝置
10:半導體晶片
20:第1絕緣膜
30:電極墊
40:第2絕緣膜
50:障壁金屬
60:柱狀電極
70:樹脂層
80:虛設構件
90:第3絕緣膜
100:金屬凸塊
F10a:第1面
F10b:第2面

Claims (25)

  1. 一種半導體裝置，其包含： 半導體晶片，其具有第1面及與上述第1面為相反之側之第2面，且於上述第1面側設置有半導體元件； 柱狀電極，其於將自上述第2面向上述第1面之方向設為上方向時，設置於上述第1面之上方，且電性連接於上述半導體元件之任一個； 第1構件，其於上述第1面之上方，設置於上述柱狀電極之周邊；及 第1絕緣材料，其設置於上述柱狀電極及上述第1構件之周圍； 上述第1構件較上述柱狀電極及上述絕緣材料硬， 上述第1構件及上述柱狀電極係自上述絕緣材料之上方向側之表面露出。
  2. 如請求項1之半導體裝置，其中上述第1構件包含自上述第1絕緣材料露出之第3面、與上述半導體晶片之第1面對向之第4面、及處於上述第3面與上述第4面之間之側面， 上述側面係自相對於上述第1面垂直之方向傾斜，或具有階差。
  3. 如請求項1之半導體裝置，其中上述第1構件為積層體，該積層體係將自上述第1面觀察之面積互不相同之複數個第2構件積層而構成。
  4. 如請求項1之半導體裝置，其中上述第1構件使用矽、玻璃、氧化鋁、SiC、AlN、陶瓷或金屬中之任一種。
  5. 如請求項1之半導體裝置，其進而包含設置於上述柱狀電極上之金屬凸塊。
  6. 如請求項1之半導體裝置，其進而包含設置於上述柱狀電極上之第1配線層。
  7. 如請求項1之半導體裝置，其進而包含設置於上述半導體晶片之電極墊與上述柱狀電極之間之金屬膜， 自上述絕緣材料露出之上述柱狀電極之面積，大於上述柱狀電極對於上述半導體晶片之電極墊之接觸面積。
  8. 如請求項1之半導體裝置，其中自上述第1絕緣材料露出之上述柱狀電極之面積，小於上述柱狀電極對於上述半導體晶片之接觸面積。
  9. 如請求項1之半導體裝置，其中上述柱狀電極包含：第1柱狀電極，其自上述第1絕緣材料露出之面積，大於上述柱狀電極對於上述半導體晶片之接觸面積；及第2柱狀電極，其自上述絕緣材料露出之面積，小於上述柱狀電極對於上述半導體晶片之接觸面積。
  10. 如請求項5之半導體裝置，其中上述第1構件為導電體，且與上述半導體元件之任一個電性連接。
  11. 如請求項1之半導體裝置，其中上述絕緣材料將積層後之複數個上述半導體晶片埋入， 上述第1構件配置於上述半導體晶片之任一個上。
  12. 如請求項11之半導體裝置，其中上述複數個半導體晶片為複數個記憶體晶片及該記憶體晶片之控制器晶片， 上述第1構件及上述控制器晶片係設置於上述複數個記憶體晶片之積層體上。
  13. 如請求項1之半導體裝置，其中上述柱狀電極使用Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al等單體、其等之中2種以上之複合膜、或者其等之中2種以上之合金之任一種。
  14. 如請求項1之半導體裝置，其進而包含設置於上述半導體元件之上述第2面之支持部。
  15. 如請求項1之半導體裝置，其進而包含設置於上述半導體晶片之上述第1面上之第1配線層， 上述柱狀電極及上述第1構件係設置於上述配線層之上側。
  16. 如請求項1之半導體裝置，其進而包含：第2絕緣材料，其覆蓋上述半導體晶片；及 第1配線層，其設置於上述半導體晶片之第1面、及與該第1面為同一平面之上述第2絕緣材料之面上； 上述柱狀電極及上述第1構件係設置於上述配線層內。
  17. 一種半導體裝置之製造方法，其包含： 於半導體晶片之第1面之上方形成柱狀電極，該半導體晶片具有第1面及與該第1面為相反之側之第2面，且於該第1面上具有半導體元件； 於上述半導體晶片之上述第1面之上方，設置上表面位於較上述柱狀電極低之位置之第1構件； 於上述第1面上，形成埋入上述柱狀電極及上述第1構件之第1絕緣材料；及 對上述第1絕緣材料及上述柱狀電極進行研磨，直至較上述柱狀電極及上述第1絕緣材料硬之上述第1構件露出為止。
  18. 如請求項17之方法，其中上述第1構件包含自上述第1絕緣材料露出之第3面、與上述半導體晶片之第1面對應之第4面、及處於上述第3面與上述第4面之間之側面， 上述側面自相對於上述第1面垂直之方向傾斜，或具有階差， 基於上述第1構件之研磨面積之變化，停止上述第1絕緣材料及上述柱狀電極之研磨。
  19. 如請求項17之方法，其中上述第1構件係將表面積互不相同之複數個第2構件積層而形成。
  20. 如請求項17之方法，其進而包含於上述柱狀電極上形成金屬凸塊。
  21. 如請求項17之方法，其進而包含於上述柱狀電極上形成第1配線層。
  22. 如請求項17之方法，其中於上述半導體晶片之電極墊上形成金屬膜， 上述柱狀電極係利用鍍覆法形成於上述金屬膜上。
  23. 如請求項17之方法，其中上述柱狀電極係藉由將金屬線接合於上述半導體晶片之電極墊上，並向相對於上述第1面大致垂直之方向拉出而形成。
  24. 如請求項17之方法，其進而包含積層複數個上述半導體晶片， 上述柱狀電極形成於上述複數個半導體晶片各自之上述第1面上， 上述第1構件配置於上述複數個半導體晶片之任一個上， 上述第1絕緣材料係埋入上述半導體晶片之積層體、上述柱狀電極及上述第1構件。
  25. 如請求項17之方法，其中上述複數個半導體晶片為複數個記憶體晶片及該記憶體晶片之控制器晶片， 上述第1構件及上述控制器晶片係設置於上述複數個記憶體晶片之積層體之上。
TW110105709A 2020-07-07 2021-02-19 半導體裝置及半導體裝置之製造方法 TWI771913B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020117274A JP2022014750A (ja) 2020-07-07 2020-07-07 半導体装置およびその製造方法
JP2020-117274 2020-07-07

Publications (2)

Publication Number Publication Date
TW202203393A TW202203393A (zh) 2022-01-16
TWI771913B true TWI771913B (zh) 2022-07-21

Family

ID=79172991

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110105709A TWI771913B (zh) 2020-07-07 2021-02-19 半導體裝置及半導體裝置之製造方法

Country Status (4)

Country Link
US (1) US11929332B2 (zh)
JP (1) JP2022014750A (zh)
CN (1) CN113921479A (zh)
TW (1) TWI771913B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023129959A (ja) * 2022-03-07 2023-09-20 キオクシア株式会社 半導体装置
JP2023136139A (ja) * 2022-03-16 2023-09-29 キオクシア株式会社 半導体装置およびその製造方法
JP2023141317A (ja) * 2022-03-23 2023-10-05 キオクシア株式会社 半導体装置とその製造方法
CN116995056A (zh) * 2022-05-02 2023-11-03 旭化成株式会社 半导体装置及其制造方法

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200417016A (en) * 2002-11-21 2004-09-01 Rohm Co Ltd Semiconductor device production method and semiconductor device
TW200509269A (en) * 2003-05-21 2005-03-01 Casio Computer Co Ltd Semiconductor package and method for manufacturing the same
TW200531237A (en) * 2004-01-27 2005-09-16 Casio Computer Co Ltd Semiconductor device and method of fabricating the same
TW200620509A (en) * 2004-09-10 2006-06-16 Toshiba Kk Semiconductor device and method of manufacturing the same
US20090208737A1 (en) * 2008-01-18 2009-08-20 Sungkyunkwan University Foundation For Corporate Collaboration Lamella structured thin films with ultralow dielectric constants and high hardness and method for manufacturing the same
CN101946332A (zh) * 2008-02-15 2011-01-12 日本优尼山帝斯电子株式会社 半导体器件及其制造方法
TW201438240A (zh) * 2013-03-27 2014-10-01 Hitachi Ltd 半導體裝置及其製造方法、以及具有該半導體裝置的電路
US20140327150A1 (en) * 2012-08-03 2014-11-06 Deok-Young Jung Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
US20150287611A1 (en) * 2014-04-03 2015-10-08 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor devices and fabrication method thereof
US20190305107A1 (en) * 2018-03-29 2019-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with doped contact plug and method for forming the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
MY131962A (en) 2001-01-24 2007-09-28 Nichia Corp Light emitting diode, optical semiconductor device, epoxy resin composition suited for optical semiconductor device, and method for manufacturing the same
JP2011243724A (ja) 2010-05-18 2011-12-01 Elpida Memory Inc 半導体装置およびその製造方法
JP2012015446A (ja) 2010-07-05 2012-01-19 Elpida Memory Inc 半導体装置の製造方法
JP2012059730A (ja) 2010-09-03 2012-03-22 Elpida Memory Inc 半導体装置及びその製造方法
JP2019160495A (ja) * 2018-03-09 2019-09-19 株式会社Ｊｏｌｅｄ 有機ｅｌ表示パネルの製造方法および製造装置
KR102591627B1 (ko) * 2018-08-17 2023-10-20 삼성전자주식회사 이미지 센서
KR102510671B1 (ko) * 2018-09-21 2023-03-20 에스케이하이닉스 주식회사 램프신호 생성기 및 이를 포함하는 이미지 센서
KR20210117728A (ko) * 2020-03-20 2021-09-29 삼성전자주식회사 수직형 메모리 소자

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200417016A (en) * 2002-11-21 2004-09-01 Rohm Co Ltd Semiconductor device production method and semiconductor device
TW200509269A (en) * 2003-05-21 2005-03-01 Casio Computer Co Ltd Semiconductor package and method for manufacturing the same
TW200531237A (en) * 2004-01-27 2005-09-16 Casio Computer Co Ltd Semiconductor device and method of fabricating the same
TW200620509A (en) * 2004-09-10 2006-06-16 Toshiba Kk Semiconductor device and method of manufacturing the same
US20090208737A1 (en) * 2008-01-18 2009-08-20 Sungkyunkwan University Foundation For Corporate Collaboration Lamella structured thin films with ultralow dielectric constants and high hardness and method for manufacturing the same
CN101946332A (zh) * 2008-02-15 2011-01-12 日本优尼山帝斯电子株式会社 半导体器件及其制造方法
US20140327150A1 (en) * 2012-08-03 2014-11-06 Deok-Young Jung Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
TW201438240A (zh) * 2013-03-27 2014-10-01 Hitachi Ltd 半導體裝置及其製造方法、以及具有該半導體裝置的電路
US20150287611A1 (en) * 2014-04-03 2015-10-08 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor devices and fabrication method thereof
US20190305107A1 (en) * 2018-03-29 2019-10-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with doped contact plug and method for forming the same

Also Published As

Publication number Publication date
CN113921479A (zh) 2022-01-11
JP2022014750A (ja) 2022-01-20
US11929332B2 (en) 2024-03-12
US20220013477A1 (en) 2022-01-13
TW202203393A (zh) 2022-01-16

Similar Documents

Publication Publication Date Title
TWI771913B (zh) 半導體裝置及半導體裝置之製造方法
US10833039B2 (en) Multi-chip fan out package and methods of forming the same
CN108346646B (zh) 半导体装置及其制造方法
US20220320029A1 (en) Dummy Structure of Stacked and Bonded Semiconductor Device
TWI765520B (zh) 半導體封裝以及其製造方法
US10833052B2 (en) Microelectronic package utilizing embedded bridge through-silicon-via interconnect component and related methods
KR102170575B1 (ko) 휨 감소를 위한 인포 패키지 지지
US9048225B2 (en) Semiconductor device and method for manufacturing semiconductor device
US8703542B2 (en) Wafer-level packaging mechanisms
KR101690371B1 (ko) 몰딩 화합물 내에 리세스들을 가진 집적 팬아웃 패키지 구조
US9443783B2 (en) 3DIC stacking device and method of manufacture
KR100609334B1 (ko) 감광성 폴리머가 갭필된 적층 회로부재 및 그의 제조 방법
US7964446B2 (en) Semiconductor device and method of manufacturing the same
US20140057394A1 (en) Method for making a double-sided fanout semiconductor package with embedded surface mount devices, and product made
KR102459551B1 (ko) Cowos 구조물 및 이의 형성 방법
US20160148887A1 (en) Device Package with Reduced Thickness and Method for Forming Same
JP5588620B2 (ja) ウェーハ・レベル・パッケージ及びその形成方法
TW200952093A (en) Semiconductor package and method of making the same
US11848265B2 (en) Semiconductor package with improved interposer structure
TW201717293A (zh) 具有空腔之聚合物系半導體結構
TW201701429A (zh) 晶圓級封裝及其製作方法
TW202221866A (zh) 具有緩衝層的半導體裝置及處理半導體晶圓的方法
US11282759B2 (en) Chip package structure having warpage control and method of forming the same
CN221102065U (zh) 2.5维封装结构
CN112687634B (zh) 半导体封装及其制造方法