CN113921479A - 半导体装置及半导体装置的制造方法 - Google Patents

半导体装置及半导体装置的制造方法 Download PDF

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Publication number
CN113921479A
CN113921479A CN202110208824.8A CN202110208824A CN113921479A CN 113921479 A CN113921479 A CN 113921479A CN 202110208824 A CN202110208824 A CN 202110208824A CN 113921479 A CN113921479 A CN 113921479A
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semiconductor device
columnar electrode
semiconductor
electrode
semiconductor chip
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本间荘一
右田达夫
三浦正幸
前田竹识
加藤和弘
山本进
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Kioxia Corp
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Kioxia Corp
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Abstract

本案涉及一种半导体装置及半导体装置的制造方法。本实施方式的半导体装置具备半导体芯片，该半导体芯片具有第1面及与该第1面相反之侧的第2面，且在第1面上设置着半导体元件。柱状电极设置在第1面的上方，且电连接于半导体元件的任一个。第1部件在第1面的上方，设置在柱状电极的周边。绝缘材料被覆柱状电极及第1部件。第1部件比柱状电极及绝缘材料硬。第1部件及柱状电极从绝缘材料的表面露出。

Description

半导体装置及半导体装置的制造方法
相关申请案的引用
本申请案基于2020年07月7日提出申请的在先日本专利申请案第2020-117274号的优先权而主张优先权利益，通过引用将其全部内容并入本文中。
技术领域
本发明的实施方式涉及一种半导体装置及半导体装置的制造方法。
背景技术
业界开发出一种技术，将多个半导体芯片及控制器芯片作为1个半导体封装(CSP(Chip Scale Package，芯片规模封装))进行树脂密封。
然而，在对树脂进行研磨而调整半导体封装的厚度时，存在半导体封装的厚度不均的问题。如果半导体封装过薄，那么导致半导体封装翘曲。另外，一边测定树脂的厚度一边对树脂进行研磨会导致产量降低。
发明内容
一实施方式提供一种能够抑制产量降低、且抑制半导体封装的厚度不均或半导体封装的翘曲的半导体装置及半导体装置的制造方法。
实施方式的半导体装置具备一种半导体装置，包括：半导体芯片(10)，具有第1面及与所述第1面相反之侧的第2面，且在所述第1面侧设置着半导体元件；柱状电极(60)，在将从所述第2面朝向所述第1面的方向设为上方向时，设置在所述第1面的上方，且电连接于所述半导体元件的任一个；第1部件(80)，在所述第1面的上方，设置在所述柱状电极的周边；以及第1绝缘材料(90、122)，设置在所述柱状电极及所述第1部件的周围；所述第1部件比所述柱状电极及所述绝缘材料硬，所述第1部件及所述柱状电极从所述绝缘材料的上方向侧的表面露出。
根据所述构成，可提供一种能够抑制产量降低、且抑制半导体封装的厚度不均或半导体封装的翘曲的半导体装置及半导体装置的制造方法。
附图说明
图1是表示第1实施方式的半导体装置的构成的一例的剖视图。
图2是表示第1实施方式的半导体装置的制造方法的一例的剖视图。
图3是表示接在图2之后的半导体装置的制造方法的一例的剖视图。
图4是表示接在图3之后的半导体装置的制造方法的一例的剖视图。
图5是表示接在图4之后的半导体装置的制造方法的一例的剖视图。
图6是表示接在图5之后的半导体装置的制造方法的一例的剖视图。
图7是表示接在图6之后的半导体装置的制造方法的一例的剖视图。
图8是表示接在图7之后的半导体装置的制造方法的一例的剖视图。
图9是表示接在图8之后的半导体装置的制造方法的一例的剖视图。
图10是表示接在图9之后的半导体装置的制造方法的一例的剖视图。
图11是表示接在图10之后的半导体装置的制造方法的一例的剖视图。
图12是表示接在图11之后的半导体装置的制造方法的一例的剖视图。
图13是表示第2实施方式的半导体装置的制造方法及构成的一例的剖视图。
图14是表示第2实施方式的半导体装置的制造方法及构成的一例的剖视图。
图15是表示第3实施方式的半导体装置的制造方法及构成的一例的剖视图。
图16是表示第3实施方式的半导体装置的制造方法及构成的一例的剖视图。
图17是表示第4实施方式的半导体装置的制造方法及构成的一例的剖视图。
图18是表示第4实施方式的半导体装置的制造方法及构成的一例的剖视图。
图19是表示第5实施方式的半导体装置的制造方法及构成的一例的剖视图。
图20是表示第5实施方式的半导体装置的制造方法及构成的一例的剖视图。
图21是表示第6实施方式的半导体装置的构成的一例的剖视图。
图22是表示第7实施方式的半导体装置的制造方法的一例的剖视图。
图23是表示接在图22之后的半导体装置的制造方法的一例的剖视图。
图24是表示第7实施方式的半导体装置的构成例的剖视图。
图25是表示第8实施方式的半导体装置的构成的一例的剖视图。
图26是表示第9实施方式的半导体装置的构成的一例的剖视图。
图27是表示第10实施方式的半导体装置的构成的一例的剖视图。
图28是表示第11实施方式的半导体装置的构成的一例的剖视图。
图29是表示第11实施方式的半导体装置的制造方法的一例的剖视图。
图30是表示接在图29之后的半导体装置的制造方法的一例的剖视图。
图31是表示接在图31之后的半导体装置的制造方法的一例的剖视图。
图32是表示将第11实施方式的半导体装置安装在配线衬底上的状态的剖视图。
图33是表示第12实施方式的半导体装置的构成的一例的剖视图。
图34是表示第13实施方式的半导体装置的构成的一例的剖视图。
图35是表示变化例1的树脂密封工序的情况的图。
图36是表示变化例2的树脂密封工序的情况的图。
图37是表示第14实施方式的半导体装置的构成例的剖视图。
图38是表示第14实施方式的半导体装置的制造方法的一例的剖视图。
图39是表示接在图38之后的半导体装置的制造方法的一例的剖视图。
图40是表示接在图39之后的半导体装置的制造方法的一例的剖视图。
图41是表示第15实施方式的半导体装置的构成例的剖视图。
图42是表示第16实施方式的半导体装置的构成例的剖视图。
图43是表示第17实施方式的半导体装置的构成例的剖视图。
图44是表示第17实施方式的半导体装置的构成例的俯视图。
图45是表示第18实施方式的半导体装置的构成例的剖视图。
图46是表示第19实施方式的半导体装置的构成例的剖视图。
图47是表示第20实施方式的半导体装置的构成例的剖视图。
图48是表示第21实施方式的半导体装置的构成例的剖视图。
图49是表示第22实施方式的半导体装置的构成例的剖视图。
图50是表示第22实施方式的半导体装置的构成例的剖视图。
图51是表示第22实施方式的半导体装置的构成例的剖视图。
图52是表示第22实施方式的半导体装置的构成例的剖视图。
图53是表示第23实施方式的半导体装置的构成例的剖视图。
图54是表示第24实施方式的半导体装置的构成例的剖视图。
图55是表示第25实施方式的半导体装置的构成例的剖视图。
图56是表示第26实施方式的半导体装置的构成例的剖视图。
图57是表示第27实施方式的半导体装置的构成例的剖视图。
图58是表示第28实施方式的半导体装置的构成例的剖视图。
图59是表示第29实施方式的半导体装置的构成例的剖视图。
图60A是表示第30实施方式中的研磨装置的构成例的图。
图60B是表示第30实施方式中的研磨装置的构成例的图。
图60C是表示涡电流传感器的概略性构成的概念图。
图60D是表示第30实施方式中的研磨装置的构成例的图。
具体实施方式
现在参考附图说明实施例。本发明不限于这些实施例。在实施例中，“上方向”或“下方向”是指将与设置有半导体元件或半导体芯片的半导体衬底的表面垂直的方向假设为“上方向”时的相对方向。因此，术语“上方向”或“下方向”有时与基于重力加速度方向的上方向或下方向不同。在本说明书和附图中，与前述附图中描述的元件相同的元件用相同的附图标记表示，并适当地省略其详细说明。
本实施方式的半导体装置具备半导体芯片，该半导体芯片具有第1面及与该第1面相反之侧的第2面，且在第1面上设置着半导体元件。柱状电极设置在第1面的上方，且电连接于半导体元件的任一个。第1部件在第1面的上方，设置在柱状电极的周边。绝缘材料被覆柱状电极及第1部件。第1部件比柱状电极及绝缘材料硬。第1部件及柱状电极从绝缘材料的表面露出。以下，在各实施方式中所谓的“硬”，也可以指在所谓的布氏硬度、维氏硬度等试验中硬。
(第1实施方式)
图1是表示第1实施方式的半导体装置1的构成的一例的剖视图。半导体装置1具备半导体芯片10、第1绝缘膜20、电极垫30、第2绝缘膜40、势垒金属50、柱状电极60、树脂层70、作为第1部件的虚设部件80、作为绝缘材料的第3绝缘膜90、以及金属凸块100。半导体装置1例如也可以是NAND(Not And，与非)型闪速存储器、LSI(Large Scale Integration，大规模集成电路)等半导体封装。
半导体芯片10具有第1面F10a、及与第1面相反之侧的第2面F10b。晶体管或电容器等半导体元件(未图示)形成在半导体芯片10的第1面F10a上。半导体芯片10例如也可以是NAND型闪速存储器的存储器芯片或搭载着任意的LSI的半导体芯片。
第1绝缘膜20设置在半导体芯片10的第1面F10a上，被覆且保护所述半导体元件。第1绝缘膜20例如使用氧化硅膜、氮化硅膜等无机系绝缘材料。
电极垫30设置在半导体芯片10的第1面F10a上，且电连接于半导体元件的任一个。电极垫30例如使用Al、Cu、Au、Ni、Pd、W等单体、它们之中2种以上的复合膜、或者它们之中2种以上的合金等低电阻金属。第1绝缘膜20被局部地去除，以使电极垫30的一部分露出。
第2绝缘膜40设置在第1绝缘膜20上，且介置在第1绝缘膜20与第3绝缘膜90之间。第2绝缘膜40例如使用酚系、聚酰亚胺系、聚酰胺系、丙烯酸系、环氧系、PBO(p-phenylenebenzobisoxazole，p-苯撑-苯并二恶唑)系、硅酮系、苯并环丁烯系等树脂、或这些树脂的混合材料、复合材料等有机系绝缘材料。
作为金属膜的势垒金属50设置在柱状电极60与电极垫30或第2绝缘膜40之间。势垒金属50用作形成柱状电极60时的镀覆电极。势垒金属50例如使用Ti、TiN、Cr、CrN、Cu、Ni、Au、Pd、W等单体或它们之中2种以上的复合膜、或者它们之中2种以上的合金。
柱状电极60设置在半导体芯片10的第1面F10a的上方的势垒金属50上。柱状电极60从势垒金属50向相对于第1面F10a大致垂直的方向延伸。柱状电极60的下端经由势垒金属50及电极垫30而电连接于半导体芯片10的任一个半导体元件。另外，柱状电极60的上端连接于金属凸块100。柱状电极60例如使用Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al等单体、它们之中2种以上的复合膜、或者它们之中2种以上的合金等导电性金属。
柱状电极60由于是利用镀覆法或打线法等形成，所以形成在柱状电极60的形成工序中露出的势垒金属50的上方。此外，在打线法的情况下，也可以直接形成在电线30上。
树脂层70设置在虚设部件80与第2绝缘膜40之间，且将虚设部件80在第1面F10a上粘接在第2绝缘膜40。树脂层70例如使用包含酚系、聚酰亚胺系、聚酰胺系、丙烯酸系、环氧系、PBO(p-phenylenebenzobisoxazole)系、硅酮系、苯并环丁烯系等树脂、或这些树脂的混合材料、复合材料的DAF(Die Attach Film，晶片粘结薄膜)或DAP(Die Attach Paste，晶片粘结膏)。
作为第1部件的虚设部件80在第1面F10a的上方，设置在柱状电极60的周边。虚设部件80及柱状电极60形成在距第1面F10a大致相同高度水平，虚设部件80及柱状电极60的上表面从第3绝缘膜90的表面以大致相同的面露出。虚设部件80为了作为第3绝缘膜90的研磨工序中的研磨挡止层发挥功能，而由比柱状电极60及第3绝缘膜90的两者硬的材料构成。第3绝缘膜90例如使用环氧系、酚系、聚酰亚胺系、聚酰胺系、丙烯酸系、PBO系、硅酮系、苯并环丁烯系等树脂、这些树脂的混合材料、复合材料。虚设部件80例如使用硅、玻璃、氧化铝、SiC、AlN、陶瓷、金属等。
第3绝缘膜90在第1面F10a的上方，被覆且填埋柱状电极60及虚设部件80的周围。第3绝缘膜90的表面与柱状电极60及虚设部件80的表面为大致同一平面，且露出柱状电极60及虚设部件80的表面。
金属凸块100设置在柱状电极60上。金属凸块100例如使用焊料等导电性金属。
如上所述，本实施方式的半导体装置1中，虚设部件80设置在柱状电极60的周围，且与柱状电极60一起填埋在第3绝缘膜90内。虚设部件80由比柱状电极60及第3绝缘膜90硬的材料构成，且作为第3绝缘膜90的研磨工序中的挡止层发挥功能。由此，当虚设部件80从第3绝缘膜90露出时，能够阻止研磨处理。结果，第3绝缘膜90的厚度不会不均，半导体装置1的封装的厚度稳定。
另外，能够根据虚设部件80的厚度来控制第3绝缘膜90的厚度。因此，在研磨的中途，无须测定第3绝缘膜90的厚度，能够提高产量。
另外，由于虚设部件80由比柱状电极60及第3绝缘膜90硬的材料构成，所以半导体装置1被增强，不易翘曲。由此，有助于提高半导体装置1的可靠性。另外，通过改变半导体装置内的虚设部件80的体积，也能够调整翘曲，进而能够提高可靠性。
接下来，对本实施方式的半导体装置1的制造方法进行说明。
图2～图12是表示第1实施方式的半导体装置1的制造方法的一例的剖视图。此外，在图中，表示了半导体芯片，但该半导体芯片是切割前的晶片状态的一部分。
首先，在半导体晶片W的第1面F10a上形成半导体元件(未图示)。半导体晶片W例如可以是硅衬底等半导体衬底。接下来，在第1面F10a上，形成与半导体元件电连接的电极垫30。电极垫30例如使用Al、Cu、Au、Ni、Pd、W等单体、它们之中2种以上的复合膜、或者它们之中2种以上的合金等。接下来，以被覆半导体元件的方式，在第1面F10a上形成第1绝缘膜20。利用光刻技术及蚀刻技术对第1绝缘膜20进行加工，使电极垫30的一部分露出。第1绝缘膜20例如使用氧化硅膜、氮化硅膜等无机系绝缘材料。接下来，在第1绝缘膜20上形成第2绝缘膜40。也对第2绝缘膜40进行加工，以使电极垫30的一部分露出。第2绝缘膜40例如使用酚系、聚酰亚胺系、聚酰胺系、丙烯酸系、环氧系、PBO(p-phenylenebenzobisoxazole)系、硅酮系、苯并环丁烯系等树脂、或这些树脂的混合材料、复合材料等有机系绝缘材料。由此，获得图2所示的结构。
接下来，如图3所示，利用溅镀法、蒸镀法或无电解镀覆法，在电极垫30及第2绝缘膜40上形成势垒金属50。势垒金属50例如使用Ti、TiN、Cr、CrN、Cu、Ni、Au、Pd、W等单体、它们之中2种以上的复合膜、或者它们之中2种以上的合金。例如，势垒金属50使用利用溅镀法形成的0.1μm的厚度的Ti膜与0.3μm的厚度的Cu膜的积层膜。
接下来，如图4所示，在势垒金属50上涂布光阻剂PR。利用光刻技术，将光阻剂PR加工为柱状电极60的图案。例如，光阻剂PR的厚度约为40μm，在电极垫30上形成约100μm见方的开口。邻接的开口间的间距约为300μm。为了去除开口底部的残渣，也可以进行O2灰化处理。由此，处于柱状电极60的形成位置的势垒金属50确实地露出。
接下来，在露出的势垒金属50上，利用电镀法等堆积Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al等单体、它们之中2种以上的复合膜、或者它们之中2种以上的合金。由此，如图5所示，在柱状电极60的形成区域选择性地镀覆金属，而形成柱状电极60。例如，柱状电极60是通过将Cu以约35μm的厚度镀覆来形成。
接下来，如图6所示，将光阻剂PR剥离。在剥离之后，为了去除残渣，也可以进行O2灰化处理。
接下来，如图7所示，使用柱状电极60作为掩模，对势垒金属50进行蚀刻。例如，在势垒金属50为Cu的情况下，利用柠檬酸及过氧化氢的混合溶液进行湿式蚀刻即可。在势垒金属50为Ti的情况下，利用氢氟酸或过氧化氢水等进行蚀刻即可。
接下来，如图8所示，将芯片状的虚设部件80介隔树脂层70贴附在第1面F10a上。树脂层70例如使用包含酚系、聚酰亚胺系、聚酰胺系、丙烯酸系、环氧系、PBO(p-phenylenebenzobisoxazole)系、硅酮系、苯并环丁烯系等树脂的DAF(Die Attach Film)或DAP(Die Attach Paste)的单体、这些之中2种以上的混合材料、这些之中2种以上的积层材料。虚设部件80是比柱状电极60及图9所示的第3绝缘膜90硬的材料。虚设部件80例如使用硅、玻璃、氧化铝、SiC、AlN、陶瓷、金属等单体、这些之中2种以上的混合材料、或者这些之中2种以上的积层材料。虚设部件80的维氏硬度理想的是0.85GPa以上30GPa以下。如果小于0.85GPa，那么接近第3绝缘膜、柱状电极的维氏硬度，难以阻止研磨。相反，如果超过30GPa，那么材料价格高且特殊，不易使用。更理想的是可使维氏硬度为5GPa以上25GPa以下。虚设部件80以预先成为规定高度的方式设计。虚设部件80的上表面定位于比柱状电极60的上表面低的位置。由此，在研磨第3绝缘膜90时，虚设部件80在柱状电极60露出之后，可使研磨停止。例如，如果柱状电极60的厚度约为35μm，那么将树脂层70的厚度设为约5μm，将虚设部件80的厚度设为约25μm，将整体的厚度设为约30μm。此外，在使用金属作为虚设部件80的情况下，也可以利用镀覆法形成。例如，在形成柱状电极60之后，也可以利用镀覆法形成与柱状电极60不同的金属作为虚设部件80。在此情况下，也可以不使用贴附虚设部件80的树脂层70。
接下来，如图9所示，在第1面F10a上，利用模塑法等形成第3绝缘膜90。第3绝缘膜90的形成方法可以是涂布液状树脂的方法，或者也可以是使用片状膜的片材模塑法。第3绝缘膜90使用环氧系、酚系、聚酰亚胺系、聚酰胺系、丙烯酸系、PBO系、硅酮系、苯并环丁烯系等树脂、这些树脂的混合材料、复合材料。环氧树脂的例子并不特别限定，例如，可列举双酚A型、双酚F型、双酚AD型、双酚S型等双酚型环氧树脂、酚系酚醛清漆、甲酚酚醛清漆型等酚醛清漆型环氧树脂、间苯二酚型环氧树脂、三酚甲三缩水甘油醚等芳香族环氧树脂、萘型环氧树脂、茀型环氧树脂、二环戊二烯型环氧树脂、聚醚改性环氧树脂、二苯甲酮型环氧树脂、苯胺型环氧树脂、NBR改性环氧树脂、CTBN改性环氧树脂、及这些树脂的氢化物等。其中，从与Si的密接性良好的方面来看，优选萘型环氧树脂、二环戊二烯型环氧树脂。另外，从容易获得速硬化性的方面来看，也优选二苯甲酮型环氧树脂。这些环氧树脂可单独使用，也可以将2种以上一并使用。另外，也可以在第3绝缘膜90中包含二氧化硅等填料。第3绝缘膜90以填埋柱状电极60及虚设部件80的方式形成。在第3绝缘膜90是利用烘箱等的加热或UV(ultraviolet，紫外线)硬化类型树脂的情况下，通过利用紫外线等固化来硬化。
接下来，如图10所示，利用机械研磨法、CMP(Chemical Mechanical Polishing，化学机械抛光)法等，对第3绝缘膜90及柱状电极60进行研磨，而使虚设部件80露出。虚设部件80由于由比硬化后的第3绝缘膜90及柱状电极60硬的材料构成，所以在虚设部件80露出时，能够使第3绝缘膜90及柱状电极60的研磨停止。例如，在虚设部件80及它的下方的树脂层70的厚度约为30μm情况下，第3绝缘膜90的厚度也能够一致为约30μm。由于虚设部件80的上表面比柱状电极60的上表面低，所以虚设部件80在柱状电极60露出之后能够使研磨停止。
接下来，如图11所示，在柱状电极60上涂布助焊剂，形成金属凸块100。金属凸块100使用以Sn为主成分的焊料等金属。例如，使用Sn、Ag、Cu、Au、Pd、Bi、Zn的单体、它们之中的2种以上的复合膜、或合金。接下来，通过将金属凸块100回流焊，而将金属凸块100连接于柱状电极60。
接下来，利用刀片切割法或激光切割法等，将半导体晶片W切割，而单片化为半导体芯片10。由此，完成图11所示的半导体装置1。然后，如图12所示，在配线衬底200上搭载半导体装置1，将金属凸块100连接于配线衬底200的电极垫。也可以在配线衬底200上搭载其它半导体装置，并模块化。另外，也可以在半导体晶片W的状态下，搭载在配线衬底200上，然后，将半导体晶片W与配线衬底200一起切割。金属凸块100也可以形成在配线衬底200上。在该情况下，将柱状电极60的露出面与形成在配线衬底200的金属凸块100连接。
如以上所述，根据本实施方式，虚设部件80与柱状电极60一起设置在第1面F10a上。虚设部件80由比柱状电极60及第3绝缘膜90硬的材料构成，且作为第3绝缘膜90的研磨工序中的挡止层发挥功能。由此，第3绝缘膜90的厚度不会不均，而半导体装置1的封装的厚度稳定。
另外，能够根据虚设部件80的厚度来控制第3绝缘膜90的厚度。因此，在研磨的中途，无须测定第3绝缘膜90的厚度，能够提高产量。
另外，由于虚设部件80由比柱状电极60及第3绝缘膜90硬的材料构成，所以半导体装置1被增强，不易翘曲。由此，有助于提高半导体装置1的可靠性。
例如，对本实施方式的半导体装置1进行温度循环试验(Thermal Cycle Test)，调查它的可靠性。温度循环试验是将-55℃(30min)、25℃(5min)、125℃(30min)作为1个循环进行。结果，即便在3000个循环之后，半导体装置1也无问题。
(第2实施方式)
图13及图14是表示第2实施方式的半导体装置1的制造方法及构成的一例的剖视图。图13表示半导体装置1的制造中途的构成，且表示了与第1实施方式的图9对应的状态。图14表示了完成后的半导体装置1的构成。
在第2实施方式中，虚设部件80被分割成从第1面F10a的上方观察的面积互不相同的作为多个第2部件的部件80a～80c，成为将部件80a～80c积层而构成的积层体。通过使部件80a～80c的面积不同，虚设部件80的研磨面积变化。由于研磨阻力会基于虚设部件80的研磨面积的变化而变化，所以研磨装置(未图示)能够特定出正在研磨的部件80a～80c。研磨装置在虚设部件80的研磨面积(或者研磨阻力)成为规定值时停止研磨处理。只要预先设定与虚设部件80的研磨面积(或者研磨阻力)对应的部件80a～80c及树脂层70a～70c的厚度，便能够控制研磨中的虚设部件80的剩余膜厚(第3绝缘膜90的剩余膜厚)。
对第2实施方式的制造方法更详细地进行说明。
经过图2～图7所示的工序之后，部件80a利用树脂层70a粘接在第2绝缘膜40上，部件80b利用树脂层70b粘接在部件80a上，部件80c利用树脂层70c粘接在部件80b上。例如，将部件80a～80c的厚度分别设定为约10μm，将树脂层70a～70c的厚度分别设定为约5μm。在该情况下，虚设部件80的高度成为约45μm。另外，从第1面F10a的上方观察时，部件80a～80c中的部件80a的面积最大，并按照部件80b、80c的顺序变小。由此，如图13所示，构成为部件80a～80c的侧面阶梯状地具有阶差。部件80a～80c的材料可与第1实施方式的虚设部件80的材料相同。另外，树脂层70a～70c的材料可与第1实施方式的树脂层70的材料相同。
接下来，像参照图9所说明那样，第3绝缘膜90以填埋部件80a～80c及柱状电极60的方式形成。由此，获得图13所示的结构。
接下来，对第3绝缘膜90及柱状电极60进行研磨，使虚设部件80露出。此时，虚设部件80从部件80c起依次被研磨。因此，虚设部件80的研磨面积最初较小，但逐渐变大。由于研磨阻力会根据虚设部件80的研磨面积变化而变化，所以研磨装置能够检测出部件80a～80c的哪一个露出。由此，能够控制第3绝缘膜90的厚度。例如，当在部件80b露出的时间点停止研磨的情况下，部件80c及树脂层70c被研磨之后，在部件80b露出的时间点研磨装置停止研磨。由此，如图14所示，可控制为第3绝缘膜90的厚度与部件80a、80b及树脂层70a、70b的合计厚度(在所述例子的情况下，例如为30μm)大致相等。
接下来，在柱状电极60上涂布助焊剂，形成金属凸块100。接下来，将半导体晶片W切割，而单片化为半导体芯片10。由此，完成图14所示的半导体装置1。
研磨也可以在部件80a露出的时间点停止。另外，虚设部件80也可以是2层部件的积层体，或者也可以是4层以上部件的积层体。各部件80a～80c的厚度只要预先判明，那么也可以互不相同。
根据第2实施方式，虚设部件80在俯视时成为面积互不相同的多个部件80a～80c的积层体。另外，部件80a～80c及树脂层70a～70c的厚度预先设定。由此，容易控制第3绝缘膜90的膜厚。第2实施方式的其它构成可与第1实施方式相同。因此，第2实施方式也能够获得与第1实施方式相同的效果。
(第3实施方式)
图15及图16是表示第3实施方式的半导体装置1的制造方法及构成的一例的剖视图。图15表示半导体装置1的制造中途的构成，且表示了与第1实施方式的图9对应的状态。图16表示了完成后的半导体装置1的构成。
在第3实施方式中，虚设部件80在它的侧面F80c具有阶梯状的阶差ST。利用虚设部件80的侧面F80c的阶差ST，而从第1面F10a观察时的各阶差ST中的面积不同，由此，虚设部件80的研磨面积变化。研磨装置由于基于虚设部件80的研磨面积的变化而研磨阻力变化，所以能够特定出正在研磨的虚设部件80的阶差ST的高度。如果预先设定虚设部件80的各阶差ST的厚度(高度)，那么能够控制研磨中的虚设部件80的剩余膜厚(第3绝缘膜90的剩余膜厚)。
对第3实施方式的制造方法更详细地进行说明。
在经过图2～图7所示的工序之后，虚设部件80利用树脂层70a粘接在第2绝缘膜40上。虚设部件80具有上表面F80a、背面F80b、及侧面F80c。在虚设部件80的侧面F80c，形成着阶差ST。阶差ST也可以利用光刻技术及蚀刻技术形成。或者，阶差ST也可以利用加工技术、切割刀片形成。阶差ST既可以在将虚设部件80贴附在第2绝缘膜40上之后形成，也可以在将虚设部件80贴附在第2绝缘膜40上之前形成。例如，将各阶差ST的厚度分别设为约10μm，将阶差ST的段数设为5个。在该情况下，从虚设部件80的阶差ST的最下段到最上段为止的高度Hst成为约40μm。另外，在从第1面F10a的上方观察时，虚设部件80的研磨面积在虚设部件80的最上段中最小，越向下段前进越大。虚设部件80的材料可与第1实施方式的虚设部件80的材料相同。
接下来，像参照图9所说明那样，第3绝缘膜90以填埋虚设部件80及柱状电极60的方式形成。由此，获得图15所示的结构。
接下来，对第3绝缘膜90及柱状电极60进行研磨，而使虚设部件80露出。此时，虚设部件80从上段起向下段依次被研磨。因此，虚设部件80的研磨面积最初较小，但逐渐变大。由于根据虚设部件80的研磨面积变化而研磨阻力变化，所以研磨装置能够检测哪个高度的阶差部分露出。由此，能够控制第3绝缘膜90的厚度。例如，当在从虚设部件80的最上段起第4段的上表面露出的时间点停止研磨的情况下，在从虚设部件80的最上段起第3段被研磨之后，在第4段的上表面露出的时间点研磨装置停止研磨。由此，如图16所示，可控制为第3绝缘膜90的厚度与第4段以下的虚设部件80及树脂层70的合计厚度大致相等。此时，例如，Hst成为10μm。
接下来，在柱状电极60上涂布助焊剂，形成金属凸块100。接下来，将半导体晶片W切割，而单片化为半导体芯片10。由此，完成图16所示的半导体装置1。
使研磨停止的阶差并不特别限定。研磨也可以在从虚设部件80的最上段起第3段露出的时间点停止。阶差ST的段数也并不特别限定。另外，各阶差ST的高度只要预先判明，则也可以互不相同。
这样，根据第3实施方式，虚设部件80具备从第3绝缘膜90露出的第3面(研磨面)F80a＿1、与半导体芯片的第1面F10a对应的第4面F80b、以及处于第3面F80a＿1与第4面F80b之间的侧面F80c，侧面F80c阶梯状具有阶差ST。而且，阶差ST的高度(厚度)预先设定。由此，第3绝缘膜90的膜厚的控制变得容易。第3实施方式的其它构成可与第1实施方式相同。因此，第3实施方式也能够获得与第1实施方式相同的效果。
(第4实施方式)
图17及图18是表示第4实施方式的半导体装置1的制造方法及构成的一例的剖视图。图17表示半导体装置1的制造中途的构成，且表示了与第1实施方式的图9对应的状态。图18表示了完成后的半导体装置1的构成。
在第4实施方式中，虚设部件80在它的上表面F80a的中心部具有凹部，在该凹部的两侧具有阶梯状的阶差ST。从第1面F10a的上方观察时的各阶差ST中的虚设部件80的面积因据阶差ST而不同，由此，虚设部件80的研磨面积变化。研磨装置的研磨阻力会基于虚设部件80的研磨面积的变化而变化，所以能够特定出正在研磨的虚设部件80的阶差ST的高度。只要预先设定虚设部件80的各阶差ST的厚度(高度)，便能够那么与第3实施方式同样地，控制研磨中的虚设部件80的剩余膜厚(第3绝缘膜90的剩余膜厚)。
根据第4实施方式，阶差ST在上表面F80a的中心部设置在凹部的两侧。包含阶差ST的段数、高度、形成方法在内的第4实施方式的其它构成及制造方法可与第3实施方式相同。因此，第4实施方式能够获得与第3实施方式相同的效果。
(第5实施方式)
图19及图20是表示第5实施方式的半导体装置1的制造方法及构成的一例的剖视图。图19表示半导体装置1的制造中途的构成，且表示了与第1实施方式的图9对应的状态。图20表示了完成后的半导体装置1的构成。
在第5实施方式中，虚设部件80在它的侧面F80c具有倾斜。侧面F80c从相对于第1面F10a垂直的方向倾斜。利用虚设部件80的侧面F80c的倾斜，而从第1面F10a的上方观察时的面积根据虚设部件80的研磨面的高度位置而不同，由此，虚设部件80的研磨面积变化。研磨装置由于基于虚设部件80的研磨面积的变化而研磨阻力变化，所以能够特定出正在研磨的虚设部件80的研磨面的高度。如果预先设定虚设部件80的上表面F80a的面积及侧面F80c的倾斜，那么能够控制研磨中的虚设部件80的剩余膜厚(第3绝缘膜90的剩余膜厚)。
在第5实施方式中，由于虚设部件80的侧面F80c成为连续的倾斜面，所以能够更细地控制第3绝缘膜90的厚度。第5实施方式的其它构成及制造方法可与第3或第4实施方式相同。因此，第5实施方式能够获得与第3或第4实施方式相同的效果。
此外，虚设部件80例如可以是使三角锥、四角锤、多角锤、圆锥等任一个上部平坦的形状。虚设部件80例如能够通过将半导体晶片从相对于它的表面倾斜的方向切割来形成。
(第6实施方式)
图21是表示第6实施方式的半导体装置1的构成的一例的剖视图。在第6实施方式中，再配线层(RDL(Redistribution Layer))120设置在第3绝缘膜90上。再配线层120设置在第3绝缘膜90、柱状电极60及虚设部件80上，且具有配线层121与绝缘层122积层而成的多层配线结构。配线层121例如使用Ti、TiN、Cr、CrN、Cu、Ni、Au、Pd、W、Al、Ag等单体、它们之中2种以上的复合膜、或者它们之中2种以上的合金。绝缘层122例如使用酚系、聚酰亚胺系、聚酰胺系、丙烯酸系、环氧系、PBO系、硅酮系、苯并环丁烯系等树脂、它们之中2种以上的复合膜、或者它们之中2种以上的化合物。柱状电极60电连接于配线层121的一部分。金属凸块100设置在配线层121的电极垫上，且电连接于配线层121的一部分。由此，电极凸块100经由再配线层120而电连接于柱状电极60及半导体元件的任一个。通过使用再配线层120，能够提高柱状电极60的配置自由度。进而，与图12所示的结构同样地，第6实施方式的半导体装置1也可以搭载在配线衬底200上。
第6实施方式的其它构成可与第1实施方式的对应的构成相同。由此，第6实施方式能够获得与第1实施方式相同的效果。另外，第6实施方式也可以与第2～第5实施方式的任一个实施方式组合。
(第7实施方式)
图22～图24是表示第7实施方式的半导体装置1的制造方法及构成的一例的剖视图。图22及图23表示半导体装置1的制造中途的构成。图24表示了完成后的半导体装置1的构成。
在第6实施方式中，再配线层120设置在柱状电极60及虚设部件80上。相对于此，在第7实施方式中，再配线层120设置在柱状电极60及虚设部件80之下。
对第7实施方式的制造方法更详细地进行说明。
在经过图2～图7所示的工序之后，利用绝缘膜85被覆电极55及第2绝缘膜40。此外，在第7实施方式中，由于势垒金属50及柱状电极60形成在再配线层120上，所以图7的势垒金属50及柱状电极60在此处分别称为势垒金属45及电极55。另外，在该阶段中，不形成虚设部件80。绝缘膜85为使用酚系、聚酰亚胺系、聚酰胺系、丙烯酸系、环氧系、PBO(p-phenylenebenzobisoxazole)系、硅酮系、苯并环丁烯系等树脂、或这些树脂的混合材料、复合材料等的第3绝缘膜90。另外，势垒金属45及电极55的材料可分别与势垒金属50及柱状电极60的材料相同。
在利用绝缘膜85被覆电极55及第2绝缘膜40之后，通过曝光、显影等光刻，使电极55露出。由此，获得图22的结构。
接下来，如图23所示，在电极55及绝缘膜85上，形成再配线层120。
然后，像第1实施方式中所说明那样，将势垒金属50、柱状电极60形成在配线层121上，将虚设部件80利用树脂层70粘接在绝缘层122上。将柱状电极60及虚设部件80利用第3绝缘膜90填埋，对第3绝缘膜90进行研磨直至虚设部件80露出为止。将金属凸块100形成在柱状电极60上。由此，完成图24所示的半导体装置1。
这样，再配线层120也可以设置在柱状电极60及虚设部件80之下。金属凸块100及柱状电极60经由再配线层120而与半导体芯片10的半导体元件的任一个电连接。在该情况下，柱状电极60、虚设部件80及金属凸块100的布局配置的自由度变高。
第7实施方式的其它构成及制造方法可与第6实施方式的对应的构成及制造方法相同。由此，第7实施方式也能够获得第6实施方式的效果。另外，第7实施方式也可以与第2～第5实施方式的任一个实施方式组合。
(第8实施方式)
图25是表示第8实施方式的半导体装置1的构成的一例的剖视图。在第8实施方式中，柱状电极60使用金属线利用打线接合法来形成的方面与第1实施方式不同。以下，也将柱状电极60称为金属线60。在由金属线构成柱状电极60的情况下，金属线60利用打线接合法接合在电极垫30上。在该情况下，金属线60的直径(宽度)Φ3小于从第1绝缘膜20、40露出的电极垫30的开口径Φ1。另外，从第3绝缘膜90露出的金属线60的面积小于金属线60相对于半导体芯片10的接触面积(接合面积)。进而，金属线60由于能够利用打线接合法形成，所以与利用镀覆法形成的电极相比制造成本低廉。在柱状电极60使用金属线的情况下，获得这样的特征。金属线60的材料使用Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al等单体、它们之中2种以上的复合膜、或者它们之中2种以上的合金等低电阻金属。例如也可以是对Cu被覆Pd而成的材料。为了在形成第3绝缘膜90时不使金属线60倒塌，优选金属线60使用相对较硬的Cu、CuPd合金、对Cu被覆Pd而成的材料。
对第8实施方式的制造方法进行说明。
在经过图2所示的工序之后，使用打线接合机，将金属线60的一端接合在电极垫30。接下来，将金属线60向第1面F10a的上方向大致垂直方向拉出并切断。由此，金属线60形成为在相对于第1面F10a大致垂直的方向直立的柱状电极。然后，与第1实施方式同样地，形成虚设部件80、第3绝缘膜90及金属凸块100。也可以在金属线60露出之后，在形成大于露出面的电极垫之后，形成金属凸块100。由此，完成图25所示的半导体装置1。
在第8实施方式中，由于柱状电极60使用金属线利用打线接合法形成，所以能够比镀覆法低廉且简单地形成。第8实施方式的其它构成及制造方法可与第1实施方式的对应的构成及制造方法相同。因此，第8实施方式也能够获得与第1实施方式相同的效果。第8实施方式也可以与第1～第7实施方式的任一个实施方式组合。
(第9实施方式)
图26是表示第9实施方式的半导体装置1的构成的一例的剖视图。在第9实施方式中，柱状电极60包含利用镀覆法的柱状电极60a及利用打线接合法的柱状电极(金属线)60b这两者的方面与第1实施方式不同。也就是说，在柱状电极60中利用镀覆法的柱状电极60a与利用打线接合法的柱状电极60b混合存在。
从第3绝缘膜90露出的柱状电极60a的面积也可以大于柱状电极60a相对于半导体芯片10的接触面积。另一方面，从第3绝缘膜90露出的柱状电极60b的面积也可以小于柱状电极60b相对于半导体芯片10的接触面积。
也就是说，利用镀覆法的柱状电极60a的直径Φ2也可以大于从第1绝缘膜20、40露出的电极垫30的开口径Φ1。利用接合法的金属线60b的直径Φ3也可以小于从第1绝缘膜20、40露出的电极垫30的开口径Φ1。
第9实施方式的其它构成及制造方法可与第1实施方式的对应的构成及制造方法相同。因此，第9实施方式也能够获得与第1实施方式相同的效果。第9实施方式也可以与第1～第7实施方式的任一个实施方式组合。
(第10实施方式)
图27是表示第10实施方式的半导体装置1的构成的一例的剖视图。在第10实施方式中，虚设部件80为导电体，在虚设部件80之下设置着电极垫30及势垒金属50。虚设部件80接触于势垒金属50，且经由势垒金属50而电连接于电极垫30及半导体芯片10的半导体元件的任一个。
在第10实施方式中，虚设部件80兼备作为研磨挡止层的功能及作为电极的功能。虚设部件80也可以作为电源电极将电力供给至半导体芯片10。例如，也可以将虚设部件80使用焊料或导电膏等连接。或者，虚设部件80也可以作为接地电极对半导体芯片10供给接地电压。进而，虚设部件80也可以具有作为吸收半导体芯片10的热并释放的散热板的功能。
第10实施方式的其它构成及制造方法可与第1实施方式的对应的构成及制造方法相同。因此，第10实施方式也能够获得与第1实施方式相同的效果。第10实施方式也可以与第1～第9实施方式的任一个实施方式组合。
以下，对半导体芯片10的积层体的封装的实施方式进行说明。
(第11实施方式)
图28是表示第11实施方式的半导体装置1的构成的一例的剖视图。在第11实施方式中，积层着多个半导体芯片10，柱状电极60从各半导体芯片10向相对于半导体芯片10的表面大致垂直的方向延伸。在半导体芯片10的积层体上配置虚设部件80，虚设部件80的上表面处于比最上段的半导体芯片10的表面高的位置。因此，最上段的半导体芯片10的表面不从第3绝缘膜90露出，而由第3绝缘膜90被覆。
多个半导体芯片10例如也可以是NAND型闪速存储器的存储器芯片或搭载着任意的LSI的半导体芯片。多个半导体芯片10既可以为具有相同构成的半导体芯片，也可以是具有分别不同的构成的半导体芯片。例如，多个半导体芯片10之中最上段的半导体芯片10为控制存储器芯片的控制器芯片，其它半导体芯片10可以是存储器芯片。半导体芯片10利用粘接层12而相互粘接。在半导体芯片10中，表面F10a成为形成着半导体元件的元件形成面。表面F10a的相反侧的背面F10b利用粘接层12粘接在其它半导体芯片10。
粘接层12为了将多个半导体芯片10积层，而设置在半导体芯片10间。粘接层12例如使用包含酚系、聚酰亚胺系、聚酰胺系、丙烯酸系、环氧系、PBO(p-phenylenebenzobisoxazole)系、硅酮系、苯并环丁烯系等树脂、或这些树脂的混合材料、复合材料的DAF(Die Attach Film)或DAP(Die Attach Paste)。
柱状电极60向相对于半导体芯片10的表面F10a大致垂直的方向延伸，且连接于各半导体芯片10。柱状电极60的一端连接于半导体芯片10的电极垫P10，另一端连接于金属凸块100。例如，半导体芯片10阶梯状地错开积层，柱状电极60从设置在多个半导体芯片10端部的阶差部分的各电极垫P10延伸。由此，各半导体芯片10能够经由柱状电极60而连接于金属凸块100，且不经由其它半导体芯片10，与再配线层或外部装置直接交换信号。结果，能够使半导体芯片10与控制器等之间的通信数据量或通信速度增大。柱状电极60例如既可以为用于接合线的金属线，也可以是利用镀覆法形成的柱状电极。例如，也可以如下所述，最上段的半导体芯片10的柱状电极60是利用镀覆法形成的柱状电极，其下方的半导体芯片10的柱状电极60由用于接合线的金属线构成。柱状电极60例如使用Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al等单体、它们之中2种以上的复合膜、或者它们之中2种以上的合金等低电阻金属。
虚设部件80利用树脂层70贴附在多个半导体芯片10的积层体上，且配置在最上段的半导体芯片10的旁边。虚设部件80的上表面处于比最上段的半导体芯片10的表面高的位置，且作为第3绝缘膜90的研磨挡止层发挥功能。
第3绝缘膜90被覆并保护半导体芯片10及柱状电极60。第3绝缘膜90被覆最上段的半导体芯片10的表面使它不露出。
金属凸块100设置在柱状电极60上，用来与其它元件取得电连接。金属凸块100例如使用以Sn为主成分的焊料等低电阻金属。也可以在露出金属线60后，在形成大于露出面的电极垫之后，形成金属凸块100。
接下来，对第11实施方式的半导体装置1的制造方法进行说明。
图29～图31是表示第11实施方式的半导体装置1的制造方法的一例的剖视图。
首先，如图29所示，在支撑衬底5上积层多个半导体芯片10。此时，半导体芯片10利用粘接层12粘接在其它半导体芯片10上。
接下来，将虚设部件80利用树脂层70粘接在半导体芯片10的积层体上。此时，虚设部件80的上表面定位得比最上层的半导体芯片10的上表面高。
接下来，如图30所示，在半导体芯片10的电极垫P10上利用打线接合法将金属线接合，向相对于第1面F10a大致垂直的方向拉出而形成柱状电极60。此外，也可以改变几个金属线的柱状电极60的材料，来代替虚设部件80使用。
接下来，如图31所示，利用第3绝缘膜90被覆半导体芯片10的积层体、虚设部件80及柱状电极60。例如，第3绝缘膜90为模塑树脂，并将半导体芯片10的积层体、虚设部件80及柱状电极60利用该树脂密封。接下来，使第3绝缘膜90硬化。
接下来，使用机械研磨法、CMP法等，对第3绝缘膜90进行研磨直至虚设部件80露出为止。接下来，将支撑衬底5去除之后，在柱状电极60上形成金属凸块100。金属凸块100例如只要使用球搭载、镀覆法、印刷法即可。由此，完成图28所示的半导体装置1。另外，也可以在形成金属凸块100之后将支撑衬底5去除。
此外，如下所述，柱状电极60也可以利用镀覆法形成。在该情况下，在形成第3绝缘膜90之后，使用光刻技术及蚀刻技术，在第3绝缘膜90形成达到电极垫30的孔。进而，在该孔利用镀覆法填埋金属。这样，也可以形成柱状电极60。另外，也可以在半导体芯片10预先利用镀覆法等形成柱状电极60，搭载半导体芯片10。另外，也可以将支撑衬底5从半导体装置1去除，但也可以在半导体装置1作为散热板残留。
另外，半导体装置1也可以搭载在配线衬底200。图32是表示将第11实施方式的半导体装置1安装在配线衬底200上的状态的剖视图。半导体装置1将金属凸块100朝向配线衬底200安装，经由金属凸块100而与配线衬底200的配线的一部分电连接。由此，半导体装置1可与其它半导体装置一起模块化。金属凸块100也可以形成在配线衬底200上。在该情况下，将柱状电极60的露出面与形成在配线衬底200的金属凸块100连接。
(第12实施方式)
图33是表示第12实施方式的半导体装置1的构成的一例的剖视图。在第12实施方式中，虚设部件80为导电体，在虚设部件80上设置着金属凸块100。虚设部件80经由金属凸块100而电连接于配线衬底200的配线的一部分。虚设部件80兼备作为研磨挡止层的功能及作为电极的功能。虚设部件80也可以作为电源电极将电力供给至半导体芯片10。或者，虚设部件80也可以作为接地电极对半导体芯片10供给接地电压。进而，虚设部件80也具有作为吸收半导体芯片10的热并释放的散热板的功能。
进而，在半导体芯片10的积层体之中最下段的半导体芯片10(在图33中最上方所示的半导体芯片10)的背面F10b残置支撑衬底5。支撑衬底5接触于最下段的半导体芯片10的背面F10b，作为散热板发挥功能。另外，支撑衬底5也可以作为接地电极对半导体芯片10供给接地电压。支撑衬底5例如也可以是金属等导电体或包含导热性的材料的引线框架。
第12实施方式的其它构成及制造方法可与第11实施方式的对应的构成及制造方法相同。因此，第12实施方式也能够获得与第11实施方式相同的效果。
(第13实施方式)
图34是表示第13实施方式的半导体装置1的构成的一例的剖视图。在第13实施方式中，进而设置着虚设部件81的方面与第11实施方式不同。虚设部件81贯通第3绝缘膜90而设置在半导体芯片10的积层方向，且与半导体芯片10的积层体相邻而设置。虚设部件81由与虚设部件80相同的材料构成，且比第3绝缘膜90及柱状电极60硬。通过追加虚设部件81，能够进而抑制半导体装置1的封装的翘曲。
虚设部件81在形成第3绝缘膜90之前的图29或图30的工序中，以直立在支撑衬底5上的方式配置虚设部件81。虚设部件80、81的高度优选大致相等。然后，像第11实施方式中所说明那样，利用第3绝缘膜90填埋半导体芯片10，对第3绝缘膜90进行研磨。此时，虚设部件80、81成为研磨挡止层。第13实施方式的其它构成及制造方法可与第11实施方式的对应的构成及制造方法相同。第13实施方式也可以与第1～第12实施方式的任一个实施方式组合。
(变化例1)
在将熔融的树脂流入至模具而形成第3绝缘膜90的情况下，树脂优选从图31的箭头A1所示的方向流入。箭头A1的方向为从半导体芯片10的积层体观察柱状电极60存在的方向，利用半导体芯片10的积层体来缓和树脂的流动，抑制直接影响柱状电极60。由此，通过树脂的流动，能够抑制柱状电极60倒塌或弯曲。
图35是表示变化例1的树脂密封工序的情况的图。将熔融的树脂从插入口410向箭头A1方向导入，封入至模具400、401内。此时，密封的半导体芯片10的积层体以保护柱状电极60的方式位于比柱状电极60靠上游侧，抑制柱状电极60倒塌或弯曲。
(变化例2)
图36是表示变化例2的树脂密封工序的情况的图。在将熔融的树脂流入至模具400、401而形成第3绝缘膜90的情况下，在模具400、401的内面设置着脱模膜420。脱模膜420是为了将树脂密封的半导体芯片10从模具卸除而设置，且由树脂等构成。
在变化例2中，表示了利用压缩成形法的树脂密封的例子。在模具400、401内配置脱模膜420，在其中涂布树脂。然后，将形成着柱状电极60的半导体芯片10反转后放入至树脂内，进行压缩成形。柱状电极60物理地刺入至模具400、401内的脱模膜420。柱状电极60既可以压入至脱模膜420，或者也可以贯通。由此，在树脂密封工序中，能够将柱状电极60的两端固定，抑制柱状电极60因树脂的流动而倒塌或弯曲。
脱模膜420的拉伸强度例如优选1MPa～100MPa。如果脱模膜420的拉伸强度低于1MPa，那么脱模膜420难以固定柱状电极60。如果脱模膜420的拉伸强度高于100MPa，那么难以将柱状电极60刺入至脱模膜420。因此，通过使脱模膜420的拉伸强度为1MPa～100MPa，在树脂密封工序中，脱模膜420能够抑制柱状电极60的倒塌或弯曲。
(第14实施方式)
图37是表示第14实施方式的半导体装置1的构成例的剖视图。在第14实施方式中，柱状电极60包含利用接合线的柱状电极60a与利用镀覆法形成的柱状电极60b这两者。例如，在最上段的半导体芯片10b上，利用镀覆法形成柱状电极60b。在除此以外的半导体芯片10a上利用打线接合法形成柱状电极60a。半导体芯片10a例如为存储器芯片，半导体芯片10b例如为控制器芯片。
图38～图40是表示第14实施方式的半导体装置1的制造方法的一例的剖视图。柱状电极60a像参照图29～图31所说明那样形成。由此，获得图38所示的结构。然后，如图39所示，使用激光加工技术等，削掉第3绝缘膜90的柱状电极60b的形成位置。由此，在第3绝缘膜90形成孔H60b。孔H60b从第3绝缘膜90的上表面形成至半导体芯片10b的电极垫P10为止。
接下来，将势垒金属形成在半导体芯片10b的电极垫P10上之后，如图40所示，使用镀覆法，将柱状电极60b的金属材料填埋在孔H60b。由此，形成柱状电极60b。另外，也可以在半导体芯片10预先利用镀覆法等形成柱状电极60之后，搭载半导体芯片10。
然后，使用机械研磨法、CMP法，对第3绝缘膜90及柱状电极60a、60b进行研磨，直至虚设部件80露出为止。进而，通过将金属凸块100形成在柱状电极60a、60b上，完成图37所示的半导体装置1。
(第15实施方式)
图41是表示第15实施方式的半导体装置1的构成例的剖视图。在变化例3中，柱状电极60a、60b从第3绝缘膜90的表面向金属凸块100突出。通过将柱状电极60a、60b向金属凸块100刺入，而在将半导体装置1向配线衬底200倒装芯片连接时，半导体装置1相对于配线衬底200稳定地连接，有助于抑制不良。
柱状电极60a、60b的突出形状能够通过在对第3绝缘膜90进行研磨之后，进而利用等离子体等仅对第3绝缘膜90进行蚀刻而形成。虚设部件80也成为突出的形状。
第15实施方式的其它构成可与第14实施方式的对应的构成相同。第15实施方式也可以与第12～第13实施方式的任一个实施方式组合。
(第16实施方式)
图42是表示第16实施方式的半导体装置1的构成例的剖视图。第16实施方式的半导体装置1还具备虚设柱状电极60c、60d。虚设柱状电极60c的一端接合于支撑衬底5，另一端设置到第3绝缘膜90的表面为止。虚设柱状电极60d的一端接合于半导体芯片10的任一个，另一端设置到第3绝缘膜90的表面为止。在虚设柱状电极60c、60d的另一端设置着金属凸块100，且连接于配线衬底200。虚设柱状电极60c、60d在柱状电极60偏向半导体装置1一侧的情况下，设置在半导体装置1的另一侧。由此，半导体装置1与配线衬底200之间的金属凸块100的配置位置相对均匀，温度循环试验中的应力得到缓和。结果，有助于提高可靠性。此外，虚设柱状电极60c、60d既可以电连接于半导体芯片10及配线衬底200，或者也可以不连接于半导体芯片10及配线衬底200。
虚设柱状电极60c、60d的布局配置、数量以半导体装置1与配线衬底200之间的金属凸块100的配置位置相对均匀的方式设定。另外，虚设柱状电极60c、60d的直径、材质与柱状电极60a、60b的直径、材质可以相同，也可以不同。例如，也可以将虚设柱状电极60c、60d的材料改变为柱状电极60a、60b的材料，使它发挥虚设部件80的作用。第16实施方式的其它构成可与第15实施方式的对应构成相同。第16实施方式也可以与第12～第13实施方式的任一个实施方式组合。
(第17实施方式)
图43是表示第17实施方式的半导体装置1的构成例的剖视图。图44是表示第17实施方式的半导体装置1的构成例的俯视图。根据第17实施方式，多个虚设柱状电极60c设置在半导体装置1的两侧或角部。虚设柱状电极60c的构成可与第16实施方式的构成相同。由此，与第16实施方式同样地，半导体装置1与配线衬底200之间的金属凸块100的配置位置相对均匀化，温度循环试验中的应力得到缓和。结果，有助于提高可靠性。另外，虚设柱状电极60c在将半导体装置1向配线衬底200倒装芯片连接时，可成为对准标记。
虚设柱状电极60c的布局配置、数量并不限定于此，只要以半导体装置1与配线衬底200之间的金属凸块100的配置位置相对均匀化的方式设定即可。另外，多个虚设柱状电极60c的直径、材质既可以相互相同，也可以不同。第17实施方式的其它构成可与第14实施方式的对应的构成相同。第17实施方式也可以与第12～第13实施方式的任一个实施方式组合。
(第18实施方式)
图45是表示第18实施方式的半导体装置1的构成例的剖视图。根据第18实施方式，在第3绝缘膜90的表面设置着凹部130，在凹部130内设置着金属凸块100。通过将金属凸块100形成在凹部130内，即便金属凸块100因回流焊等熔融，也能够使金属凸块100滞留在凹部130内。因此，金属凸块100能够将柱状电极60与配线衬底200之间确实地连接。第18实施方式的其它构成可与第14实施方式的对应的构成相同。另外，凹部130只要在经过图31的工序之后，对第3绝缘膜90进行研磨，使用光刻技术及蚀刻技术或激光加工技术，将柱状电极60的周围的第3绝缘膜90去除即可。第18实施方式也可以与第12～第17实施方式的任一个实施方式组合。
(第19实施方式)
图46是表示第19实施方式的半导体装置1的构成例的剖视图。根据第19实施方式，柱状电极60在第3绝缘膜90内，从相对于第1面F10a垂直的方向倾斜地设置。柱状电极60随着从相对于半导体芯片10的连接部接近第3绝缘膜90的表面，而从半导体装置1的中心部向外侧扩展，柱状电极60间的间隔也扩展。由此，扩大配线衬底200中的配线间隔，配线衬底200的配线的设计的自由度变高。第19实施方式的其它构成可与第14实施方式的对应的构成相同。第19实施方式也可以与第12～第18实施方式的任一个实施方式组合。
(第20实施方式)
图47是表示第20实施方式的半导体装置1的构成例的剖视图。根据第20实施方式，柱状电极60在第3绝缘膜90内从相对于第1面F10a垂直的方向倾斜地设置的方面与第19实施方式相同。然而，在第20实施方式中，柱状电极60随着从相对于半导体芯片10的连接部接近第3绝缘膜90的表面，从半导体装置1的中心部朝向内侧变窄，柱状电极60间的间隔也变窄。由此，例如，作为控制器的半导体芯片10b与作为存储器芯片的其它半导体芯片10a之间的配线距离变短，半导体装置1的电特性得到改善。第20实施方式的其它构成可与第14实施方式的对应的构成相同。第20实施方式也可以与第12～第18实施方式的任一个实施方式组合。
(第21实施方式)
图48是表示第21实施方式的半导体装置1的构成例的剖视图。根据第21实施方式，柱状电极60在第3绝缘膜90内从相对于第1面F10a垂直的方向倾斜且弯曲地设置的方面与第19实施方式不同。柱状电极60的弯曲优选以在导入第3绝缘膜90时柱状电极60不受影响的方式，弯曲为能够增强柱状电极60的形状。例如，柱状电极60也可以向与图31的A1方向大致平行的方向回折而成形为Z型。由此，柱状电极60成为弹簧状，能够相对于第3绝缘膜90的流动获得机械性的耐性。第21实施方式的其它构成可与第19实施方式的对应的构成相同。第21实施方式也可以与第12～第18实施方式的任一个实施方式组合。
(第22实施方式)
图49～图52是表示第22实施方式的半导体装置1的构成例的剖视图。根据图49及图50的第22实施方式，半导体装置1在配线衬底200上，由底部填充胶510及绝缘材料500被覆。底部填充胶510填充至半导体装置1与配线衬底200之间，被覆且保护金属凸块100的周围。由此，半导体装置1与配线衬底200的连接部的可靠性提高。底部填充胶510例如使用树脂。绝缘材料500以被覆半导体装置1及底部填充胶510的整体的方式设置。绝缘材料500保护半导体装置1及底部填充胶510。绝缘材料500例如与第3绝缘膜90同样地使用树脂。由此，半导体装置1的可靠性进而提高。第22实施方式的其它构成可与第14实施方式的对应的构成相同。
另外，绝缘材料500也可以像图49那样，设置至支撑衬底5之上为止，被覆支撑衬底5，但也可以像图50那样，以使支撑衬底5的上表面露出的方式设置。该情况下，能够提高支撑衬底5的散热性。
绝缘材料500及底部填充胶510也可以仅设置一者。例如，也可以像图51及图52那样，省略底部填充胶510，绝缘材料500被覆半导体装置1。在该情况下，代替底部填充胶而将绝缘材料500填埋在半导体装置1与配线衬底200之间，被覆并保护金属凸块100。第22实施方式也可以与所述实施方式的任一个实施方式组合。
图28至图52中表示了使用线作为柱状电极60的例子。当然，也可以像通常的使用打线接合法的产品那样，将芯片间直接连接的线与使用线的柱状电极60混合存在。另外，也可以将芯片间直接连接的线与使用线的柱状电极60、应用镀覆法等的柱状电极60混合存在。
(第23实施方式)
图53是表示第23实施方式中的半导体装置1的构成例的剖视图。第23实施方式在将多个虚设部件80配置在一个半导体芯片10内的方面与第1实施方式不同。第23实施方式的其它构成可与第1实施方式的对应的构成相同。通过配置多个虚设部件80，而多个虚设部件80更加能够发挥作为挡止层的作用，并且也能够调整半导体装置1的翘曲。结果，能够提高可靠性。
(第24实施方式)
图54是表示第24实施方式中的半导体装置1的构成例的剖视图。第24实施方式在还具备配置在再配线层120内的虚设部件80的方面与第6实施方式不同。第24实施方式的其它构成可与第6实施方式的对应的构成相同。通过除了虚设部件80以外将虚设部件80配置在再配线层120内，能够调整半导体装置1的翘曲。结果，能够提高可靠性。也可以将多个虚设部件80配置在再配线层120内的多个配线层间。由此，进而能够调整半导体装置1的翘曲。
(第25实施方式)
图55是表示第25实施方式中的半导体装置1的构成例的剖视图。第25实施方式在半导体装置1的柱状电极60上具备再配线层120的方面与第11实施方式不同。再配线层120在对第3绝缘膜90进行研磨之后，形成在第3绝缘膜90及柱状电极60上。金属凸块100形成在再配线层120上。通过设置再配线层120，即便在柱状电极60间的间距狭窄的情况下，也能够扩大金属凸块100间的间距。进而，再配线层120能够将半导体芯片10间经由再配线层120内的配线而电连接。也可以在再配线层120内形成虚设部件80。另外，也可以设置多个再配线层120，在多个再配线层120内形成虚设部件80。
(第26实施方式)
图56是表示第26实施方式中的半导体装置1的构成例的剖视图。本实施方式为将半导体装置1应用于所谓扇出型晶片级CSP(Chip Size Package，芯片尺寸封装)的例子。扇出型晶片级CSP的工艺大致分为RDL Last与RDL First。RDL Last为在将半导体芯片利用第4绝缘膜(绝缘材料)150覆盖之后形成再配线层120的方式，RDL First为在将半导体芯片利用第4绝缘膜150覆盖的状态之前形成再配线层120的方式。第4绝缘膜150使用环氧系、酚系、聚酰亚胺系、聚酰胺系、丙烯酸系、PBO系、硅酮系、苯并环丁烯系等树脂、这些树脂的混合材料、复合材料。作为环氧树脂的例子并不特别限定，例如，可列举双酚A型、双酚F型、双酚AD型、双酚S型等双酚型环氧树脂、酚系酚醛清漆、甲酚酚醛清漆型等酚醛清漆型环氧树脂、间苯二酚型环氧树脂、三酚甲三缩水甘油醚等芳香族环氧树脂、萘型环氧树脂、茀型环氧树脂、二环戊二烯型环氧树脂、聚醚改性环氧树脂、二苯甲酮型环氧树脂、苯胺型环氧树脂、NBR改性环氧树脂、CTBN改性环氧树脂、及这些树脂的氢化物等。其中，从与Si的密接性良好的方面来看，优选萘型环氧树脂、二环戊二烯型环氧树脂。另外，从容易获得速硬化性的方面来看，优选二苯甲酮型环氧树脂。这些环氧树脂既可以单独使用，也可以将2种以上一并使用。另外，也可以在第3绝缘膜90中包含二氧化硅等填料。
图56表示在RDL Last中在再配线层120形成虚设部件80的例子。在RDL Last方式中，在支撑衬底上形成剥离层，然后搭载半导体芯片10，利用第4绝缘膜150覆盖半导体芯片10。然后将支撑衬底剥离，将再配线层120形成在半导体芯片10的元件面。在形成柱状电极60之后，形成第3绝缘膜90，将第3绝缘膜90利用机械研磨法、CMP等平坦化。在该情况下，直至使柱状电极60露出为止对第3绝缘膜90进行研磨，此时，虚设部件80作为挡止层发挥功能。在半导体芯片10的周围存在第4绝缘膜150，在半导体芯片10的元件面形成再配线层120。再配线层120设置在半导体芯片10的第1面F10a、及与该第1面F10a为同一平面的第4绝缘膜150上。在再配线层120内形成虚设部件80，在再配线层120上形成金属凸块100。金属凸块100电连接于配线衬底200。通过在包含扇出型晶片级CSP的第3绝缘膜的再配线层120内设置虚设部件80，能够进行半导体装置1的翘曲的矫正，从而能够提高可靠性。
(第27实施方式)
图57是表示第27实施方式中的半导体装置1的构成例的剖视图。在图56的形态中，在第3绝缘膜90内设置着多个虚设部件80。第27实施方式的其它构成可与第26实施方式的对应的构成相同。通过增加虚设部件80，能够调整半导体装置1的翘曲，进而能够提高可靠性。另外，也可以在多个再配线层120内形成虚设部件80。第27实施方式也可以与其它实施方式组合。
(第28实施方式)
图58是表示第28实施方式中的半导体装置1的构成例的剖视图。本实施方式为将半导体装置1应用于所谓扇出型晶片级CSP的例子。图56表示在RDL First中在第3绝缘膜90形成虚设部件80的例子。在RDL First方式中，在支撑衬底上形成剥离层，形成柱状电极60。在将虚设部件80搭载在剥离层上之后，以覆盖柱状电极60、虚设部件80的方式形成第3绝缘膜90，利用机械研磨法、CMP等平坦化。在该情况下，直至使柱状电极60露出为止对第3绝缘层90进行研磨，此时，虚设部件80作为挡止层发挥功能。在虚设部件80上进而存在再配线层120，在半导体芯片10的周围存在第4绝缘膜150。半导体芯片10具有金属凸块100A，且倒装芯片安装在再配线层120。在第3绝缘膜90形成虚设部件80，形成金属凸块100B。金属凸块100B电连接于配线衬底200。通过在包含扇出型晶片级CSP的第3绝缘膜90的再配线层120内设置虚设部件80，能够进行半导体装置1的翘曲的矫正，从而能够提高可靠性。此外，在将再配线层从支撑衬底剥离之后，对第3绝缘膜90进行研磨，而使柱状电极60露出。虚设部件80从上下两者被研磨，所以发挥作为来自两者的研磨的挡止层的作用。
(第29实施方式)
图59是表示第29实施方式中的半导体装置1的构成例的剖视图。第29实施方式在半导体芯片10与再配线层120之间具备底部填充胶510的方面与第28实施方式不同。底部填充胶510被覆并保护半导体芯片10与再配线层120之间的金属凸块100A的周围。由此，提高半导体芯片10与再配线层120的连接部的可靠性。
(第30实施方式)
图60A、图60B、图60D是表示第30实施方式中的研磨装置的构成例的图。
图60A所示的研磨装置具备转盘300、研磨垫310、旋转轴320、马达330、电流传感器340、信号转换器350、及运算部360。
转盘300能够旋转地设置，且在表面上搭载研磨垫310。
研磨垫310设置在转盘300上，对半导体衬底W进行研磨。
旋转轴320固定在转盘300，将来自马达330的动力传递至转盘300，使转盘300旋转。
马达330接收来自未图示的电源的电力，使旋转轴320按照箭头A旋转。
电流传感器340测定由马达330消耗的电流。
信号转换器350转换由电流传感器340测定出的马达330的消耗电流值，并发送给运算部360。
运算部360例如为PC(Personal Computer，个人计算机)，根据马达330的消耗电流进行半导体衬底W的研磨处理的终点侦测。更详细来说，马达330的消耗电流根据半导体衬底W与研磨垫310之间的摩擦而变化。半导体衬底W与研磨垫310之间的摩擦根据半导体衬底W的平坦化前后的接触面积的变化或者正在研磨的膜种的变化而变化。能够利用马达330的消耗电力来侦测这种摩擦变化。这种研磨终点侦测方法也称为TCM(Torque CurrentMonitor，转矩电流监测器)。
图60B所示的研磨装置与图60A形态的不同点在于，还具备涡电流传感器370。图60B的研磨装置的其它构成可与图60A的研磨装置的对应构成相同。此外，也可以省略图60A的电流监测器340。
如图60C所示，涡电流传感器370由线圈构成，检测由半导体衬底W产生的感应电流(涡电流)。运算部360根据该涡电流引起的阻抗频率或电压等的变化而运算研磨处理的终点。图60C是表示涡电流传感器370的概略性构成的概念图。
这种研磨终点侦测方法也称为ECM(Eddy Current Monitor，涡电流监测器)。
图60D所示的研磨装置与图60A形态的不同点在于，还具备反射光传感器370。图60D的研磨装置的其它构成可与图60A的研磨装置的对应构成相同。此外，也可以省略图60A的电流监测器340。
如图60D所示，反射光传感器380将光照射至半导体衬底W，检测来自半导体衬底W的反射光，求出反射率。运算部360根据反射率的变化而侦测研磨处理的终点。
这种研磨终点侦测方法也称为OTM(Optical Thickness Monitor，光学厚度监测器)。
图60A中所说明的根据研磨阻力的变化进行的终点检测方法与所述实施方式中所使用的CMP的检测方法对应。
在使用图60D中所说明的根据反射率的变化进行的光学式终点检测方法的情况下，只要虚设部件80、81的反射率或透过率与第3绝缘膜90不同即可。一般来说，由于第3绝缘膜90多为暗色，所以虚设部件80、81的反射率也可以相对于测定波长更高。
虽然已经描述了某些实施例，但是这些实施例仅以实例方式呈现，且不意欲限制本发明的范围。事实上，本文中所述的新颖方法和系统可以各种其它形式体现；此外，本文中所述的方法和系统的形式可进行各种省略、替代和变化而不会脱离本发明的精神。随附权利要求及其对等物意欲涵盖所述形式或修改，这将处于本发明的范围和精神内。

Claims (25)

1.一种半导体装置，具备：
半导体芯片，具有第1面及与所述第1面相反之侧的第2面，且在所述第1面侧设置着半导体元件；
柱状电极，在将从所述第2面朝向所述第1面的方向设为上方向时，设置在所述第1面的上方，且电连接于所述半导体元件的任一个；
第1部件，在所述第1面的上方，设置在所述柱状电极的周边；以及
第1绝缘材料，设置在所述柱状电极及所述第1部件的周围；
所述第1部件比所述柱状电极及所述绝缘材料硬，
所述第1部件及所述柱状电极从所述绝缘材料的上方向侧的表面露出。
2.根据权利要求1所述的半导体装置，其中所述第1部件具备从所述第1绝缘材料露出的第3面、与所述半导体芯片的第1面对向的第4面、以及处于所述第3面与所述第4面之间的侧面，
所述侧面从相对于所述第1面垂直的方向倾斜，或者具有阶差。
3.根据权利要求1所述的半导体装置，其中所述第1部件为积层体，该积层体是将从所述第1面观察的面积互不相同的多个第2部件积层而构成。
4.根据权利要求1所述的半导体装置，其中所述第1部件使用硅、玻璃、氧化铝、SiC、AlN、陶瓷或金属中的任一种。
5.根据权利要求1所述的半导体装置，还具备设置在所述柱状电极上的金属凸块。
6.根据权利要求1所述的半导体装置，还具备设置在所述柱状电极上的第1配线层。
7.根据权利要求1所述的半导体装置，还具备设置在所述半导体芯片的电极垫与所述柱状电极之间的金属膜，
从所述绝缘材料露出的所述柱状电极的面积大于所述柱状电极相对于所述半导体芯片的电极垫的接触面积。
8.根据权利要求1所述的半导体装置，其中从所述第1绝缘材料露出的所述柱状电极的面积小于所述柱状电极相对于所述半导体芯片的接触面积。
9.根据权利要求1所述的半导体装置，其中所述柱状电极包含：第1柱状电极，从所述第1绝缘材料露出的面积大于所述柱状电极相对于所述半导体芯片的接触面积；以及第2柱状电极，从所述绝缘材料露出的面积小于所述柱状电极相对于所述半导体芯片的接触面积。
10.根据权利要求5所述的半导体装置，其中所述第1部件为导电体，且与所述半导体元件的任一个电连接。
11.根据权利要求1所述的半导体装置，其中所述绝缘材料填埋所积层的多个所述半导体芯片，
所述第1部件配置在所述半导体芯片的任一个上。
12.根据权利要求11所述的半导体装置，其中所述多个半导体芯片为多个存储器芯片及该存储器芯片的控制器芯片，
所述第1部件及所述控制器芯片设置在所述多个存储器芯片的积层体上。
13.根据权利要求1所述的半导体装置，其中所述柱状电极使用Cu、Ni、W、Au、Ag、Pd、Sn、Bi、Zn、Cr、Al等单体、它们之中2种以上的复合膜、或者它们之中2种以上的合金的任一种。
14.根据权利要求1所述的半导体装置，还具备设置在所述半导体元件的所述第2面的支撑部。
15.根据权利要求1所述的半导体装置，还具备设置在所述半导体芯片的所述第1面上的第1配线层，
所述柱状电极及所述第1部件设置在所述配线层的上侧。
16.根据权利要求1所述的半导体装置，还具备：第2绝缘材料，覆盖所述半导体芯片；以及
第1配线层，设置在所述半导体芯片的第1面及与该第1面为同一平面的所述第2绝缘材料的面上；
所述柱状电极及所述第1部件设置在所述配线层内。
17.一种半导体装置的制造方法，具备：
在半导体芯片的第1面的上方形成柱状电极，该半导体芯片具有第1面及与该第1面相反之侧的第2面，且在该第1面上具有半导体元件；
在所述半导体芯片的所述第1面的上方，设置上表面处于比所述柱状电极低的位置的第1部件；
在所述第1面上，形成填埋所述柱状电极及所述第1部件的第1绝缘材料；以及
对所述第1绝缘材料及所述柱状电极进行研磨，直至比所述柱状电极及所述第1绝缘材料硬的所述第1部件露出为止。
18.根据权利要求17所述的方法，其中所述第1部件具备从所述第1绝缘材料露出的第3面、与所述半导体芯片的第1面对应的第4面、以及处于所述第3面与所述第4面之间的侧面，
所述侧面从相对于所述第1面垂直的方向倾斜，或者具有阶差，
基于所述第1部件的研磨面积的变化，停止所述第1绝缘材料及所述柱状电极的研磨。
19.根据权利要求17所述的方法，其中所述第1部件是将表面积互不相同的多个第2部件积层而形成。
20.根据权利要求17所述的方法，还具备在所述柱状电极上形成金属凸块。
21.根据权利要求17所述的方法，还具备在所述柱状电极上形成第1配线层。
22.根据权利要求17所述的方法，其中在所述半导体芯片的电极垫上形成金属膜，
所述柱状电极利用镀覆法形成在所述金属膜上。
23.根据权利要求17所述的方法，其中所述柱状电极是通过将金属线接合在所述半导体芯片的电极垫上并向相对于所述第1面大致垂直的方向拉出而形成。
24.根据权利要求17所述的方法，还具备积层多个所述半导体芯片，
所述柱状电极形成在所述多个半导体芯片各自的所述第1面上，
所述第1部件配置在所述多个半导体芯片的任一个上，
所述第1绝缘材料填埋所述半导体芯片的积层体、所述柱状电极及所述第1部件。
25.根据权利要求17所述的方法，其中所述多个半导体芯片为多个存储器芯片及该存储器芯片的控制器芯片，
所述第1部件及所述控制器芯片设置在所述多个存储器芯片的积层体之上。
CN202110208824.8A 2020-07-07 2021-02-24 半导体装置及半导体装置的制造方法 Pending CN113921479A (zh)

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