JP4933233B2 - ウエーハの加工方法 - Google Patents
ウエーハの加工方法 Download PDFInfo
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- JP4933233B2 JP4933233B2 JP2006324921A JP2006324921A JP4933233B2 JP 4933233 B2 JP4933233 B2 JP 4933233B2 JP 2006324921 A JP2006324921 A JP 2006324921A JP 2006324921 A JP2006324921 A JP 2006324921A JP 4933233 B2 JP4933233 B2 JP 4933233B2
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- 238000003672 processing method Methods 0.000 title claims description 13
- 238000005520 cutting process Methods 0.000 claims description 68
- 239000000463 material Substances 0.000 claims description 56
- 239000010410 layer Substances 0.000 claims description 26
- 239000011229 interlayer Substances 0.000 claims description 22
- 238000000576 coating method Methods 0.000 claims description 13
- 239000011248 coating agent Substances 0.000 claims description 11
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 92
- 238000000034 method Methods 0.000 description 19
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- 239000004642 Polyimide Substances 0.000 description 4
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- 230000005068 transpiration Effects 0.000 description 2
- 101100008046 Caenorhabditis elegans cut-2 gene Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910009372 YVO4 Inorganic materials 0.000 description 1
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- 238000010438 heat treatment Methods 0.000 description 1
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- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
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- 238000004528 spin coating Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Dicing (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
[1]半導体ウエーハ
図1の符合1は、一実施形態で切削加工が施される円盤状の半導体ウエーハ(以下ウエーハと略称)の一例を示している。このウエーハ1はシリコンウエーハ等であって、厚さは例えば800μm程度である。ウエーハ1の表面には格子状の切断予定ライン2によって複数の矩形状の半導体チップ(デバイス)3が区画されている。これら半導体チップ3の表面には、ICやLSI等の図示せぬ電子回路が形成されている。
上記ウエーハ1は、切断予定ライン2に沿って切断、分割され、複数の半導体チップ3に個片化されるが、個片化される前に、本発明に係る次の加工が施される。
図2(a)に示す加工前のウエーハ1の表面に、アンダーフィル材9を被覆して全てのバンプ4をアンダーフィル材9中に埋没させる。図1(a),(c)および図2(b)はウエーハ1の表面にアンダーフィル材9が被覆された状態を示している。アンダーフィル材9はエポキシやポリイミド等の絶縁性樹脂からなるもので、溶液を塗布して固化したり、あるいはフィルム状のものを貼着したりする方法でウエーハ1の表面に設けられる。
図2(c)に示すように、ウエーハ1の表面側から切断予定ライン2に沿ってレーザ光Lを照射して、少なくとも切断予定ライン2上のアンダーフィル材9および層間絶縁膜層5を除去する。レーザヘッド10から照射されるレーザ光Lは、例えば次のような特性のものが用いられる。
・YVO4レーザ、YAGレーザ等の固体レーザ
・波長:355nm
・発振方法:パルス発振
・パルス幅:10〜100ns
・集光スポット径:φ5〜20μm
・繰り返し周波数:50〜100kHz
・平均出力:1〜10W
・加工送り速度:50〜400mm/秒
図2(d)に示すように、ウエーハ1を真空チャック式のチャックテーブル30上に載置し、このチャックテーブル30に真空作用で吸着、保持させる。チャックテーブル30は、円盤状のベース30aの表面に多数のピン30bが立設されたピンチャック式であり、例えばSUS430等のステンレスでできている。ウエーハ1は、裏面が多数のピン30bの先端に接触し、表面側が上方に向けられて、ピン30bの先端で形成される水平な保持面に吸着、保持される。
切削加工装置20は直方体状の基台21を有しており、ワークであるウエーハ1は、基台21上の所定位置にセットされるカセット22に、所定枚数が積層して収容される。カセット22からは、1枚のウエーハ1が搬送ロボット23によって取り出され、さらに、切削される表面側を上に向けた状態で位置決めテーブル24上に載置され、一定の位置に決められる。
以上の動作が繰り返されて多数のウエーハの表面が切削加工される。
2…切断予定ライン
3…半導体チップ(デバイス)
4…(突起状電極)
5…層間絶縁膜層
7…デブリ
9…アンダーフィル材
20…切削加工装置
L…レーザ光
Claims (2)
- 表面に形成された複数のデバイスが切断予定ラインによって区画されており、それらデバイスの表面には層間絶縁膜層および突起状電極が形成されているウエーハを、切断予定ラインに沿って切断するためのウエーハの加工方法であって、
前記層間絶縁膜層の表面にアンダーフィル材を被覆する被覆工程と、
前記ウエーハの表面側から前記切断予定ラインに沿ってレーザ光を照射して、少なくとも切断予定ライン上の前記層間絶縁膜層および前記アンダーフィル材を除去するレーザ光照射工程と、
前記アンダーフィル材の表層を切削して前記電極を表出させるとともに、前記レーザ光照射によって該アンダーフィル材上に付着したデブリを除去する切削工程と
を備えることを特徴とするウエーハの加工方法。 - 前記アンダーフィル材がフィルム状であることを特徴とする請求項1に記載のウエーハの加工方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2006324921A JP4933233B2 (ja) | 2006-11-30 | 2006-11-30 | ウエーハの加工方法 |
US11/998,045 US7662666B2 (en) | 2006-11-30 | 2007-11-28 | Method of processing wafer |
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JP2006324921A JP4933233B2 (ja) | 2006-11-30 | 2006-11-30 | ウエーハの加工方法 |
Publications (2)
Publication Number | Publication Date |
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JP2008140940A JP2008140940A (ja) | 2008-06-19 |
JP4933233B2 true JP4933233B2 (ja) | 2012-05-16 |
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JP (1) | JP4933233B2 (ja) |
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JP2011192781A (ja) * | 2010-03-15 | 2011-09-29 | Disco Corp | パッケージ基板の加工方法 |
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JP5666335B2 (ja) | 2011-02-15 | 2015-02-12 | 日東電工株式会社 | 保護層形成用フィルム |
JP5950561B2 (ja) * | 2011-12-13 | 2016-07-13 | 株式会社ディスコ | 発光素子パッケージ基板の加工方法 |
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JP6361348B2 (ja) * | 2014-07-18 | 2018-07-25 | 株式会社デンソー | 半導体装置およびその製造方法 |
JP2015092594A (ja) * | 2014-12-10 | 2015-05-14 | 日東電工株式会社 | 保護層形成用フィルム |
TWI566290B (zh) * | 2015-05-22 | 2017-01-11 | Circular splitting method | |
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JP2017054888A (ja) * | 2015-09-08 | 2017-03-16 | 株式会社ディスコ | ウエーハの加工方法 |
JP2019080024A (ja) * | 2017-10-27 | 2019-05-23 | 株式会社ディスコ | 被加工物の加工方法 |
JP7430515B2 (ja) * | 2019-11-06 | 2024-02-13 | 株式会社ディスコ | ウエーハの処理方法 |
JP7477325B2 (ja) | 2020-03-06 | 2024-05-01 | 株式会社ディスコ | 加工方法 |
JP7430111B2 (ja) | 2020-05-08 | 2024-02-09 | 株式会社ディスコ | 加工方法 |
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US7057133B2 (en) * | 2004-04-14 | 2006-06-06 | Electro Scientific Industries, Inc. | Methods of drilling through-holes in homogenous and non-homogenous substrates |
JP4130668B2 (ja) * | 2004-08-05 | 2008-08-06 | 富士通株式会社 | 基体の加工方法 |
JP4630692B2 (ja) * | 2005-03-07 | 2011-02-09 | 株式会社ディスコ | レーザー加工方法 |
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