JP2007250599A - デバイスパッケージの製造方法 - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000011347 resin Substances 0.000 claims abstract description 79
- 229920005989 resin Polymers 0.000 claims abstract description 79
- 238000005520 cutting process Methods 0.000 claims description 20
- 238000000227 grinding Methods 0.000 claims description 16
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 238000010030 laminating Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 61
- 238000000034 method Methods 0.000 abstract description 21
- 238000000465 moulding Methods 0.000 abstract description 11
- 238000005192 partition Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000005484 gravity Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003522 acrylic cement Substances 0.000 description 1
- 239000002313 adhesive film Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000005461 lubrication Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920000098 polyolefin Polymers 0.000 description 1
- 229920000915 polyvinyl chloride Polymers 0.000 description 1
- 239000004800 polyvinyl chloride Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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Abstract
【解決手段】ウエーハ1の裏面のデバイス領域4に対応する領域を薄化して凹部1aを形成し、この凹部1a内の各半導体チップ3の裏面に対応する箇所に半導体チップ21〜23を積層して実装し、凹部1a内にモールド用の樹脂Mを充填して固化させ、半導体チップ21〜23が樹脂M内に封入された樹脂モールドウエーハ9を得る。次いで、この樹脂モールドウエーハ9を分割予定ライン2に沿って切断し、複数の半導体パッケージ3Aに個片化する。
【選択図】図9
Description
[1]半導体ウエーハ
図1の符号1は、製造する半導体パッケージの素材である円盤状の半導体ウエーハ(以下ウエーハと略称)を示している。このウエーハ1はシリコンウエーハ等であって、厚さは例えば600μm程度のものである。ウエーハ1の表面には、格子状の分割予定ライン2によって複数の矩形状の半導体チップ(デバイス)3が区画されている。これら半導体チップ3の表面には、ICやLSI等の図示せぬ電子回路が形成されている。複数の半導体チップ3は、ウエーハ1と同心の概ね円形状のデバイス領域4に形成されており、このデバイス領域4の周囲に、半導体チップ3が形成されない環状の外周余剰領域5が存在している。
以下に、図1に示すウエーハ1から複数の半導体パッケージを製造する方法を、工程順に説明していく。
(1)裏面凹部形成工程
まず、図1に示すようにウエーハ1の表面に、電子回路を保護する目的で保護テープ6を貼り付ける。保護テープ6としては、例えば、厚さ70〜200μm程度のポリオレフィン等の基材の片面に厚さ5〜20μm程度のアクリル系等の粘着剤を塗布したテープなどが好適に用いられる。
次に、ウエーハ1の裏面の半導体チップ3に対応する箇所に、複数の半導体チップを積層して実装するが、その前に、図5に示すように、半導体チップ3ごとに、ウエーハ1を貫通して半導体チップ3内の電極部に導通する複数の貫通電極7を形成するとともに、図6に示すように貫通電極7に通じる球状のバンプ(外部接続端子)8を裏面に付着させる。貫通電極7は、保護テープ6を剥離させた後に、半導体チップ3ごとにウエーハ1の厚さ方向に貫通して両端が表面および裏面に露出するように形成される。この貫通電極7は、ウエーハ1にプラズマエッチングやレーザ照射等によって貫通孔を形成し、その貫通孔の内面を絶縁処理した後に銅などの金属を埋め込むことによって形成される。また、バンプ8は溶融金属を裏面側の貫通電極7の露出面に接触させるなどの方法で設けられる。貫通電極7とバンプ8の形成順は任意であり、また、少なくともバンプ8は凹部1aの形成工程の前に予め形成しておくこともできる。
次に、図9に示すように、各半導体チップ3に2層あるいは3層の状態で半導体チップが積層されたウエーハ1の裏面の凹部1a内に、エポキシ等のモールド用の樹脂Mを流し込んで充満させ、スキージ等によって樹脂Mの余剰分をすり切りにより排除して環状壁部1bと面一に仕上げる。そして、樹脂Mに応じた加熱温度/時間で加熱し、樹脂Mを固化させる。これによって、ウエーハ1の凹部1a内の積層チップ(図9(b)では複数の積層チップを一括して符号26で示している)が樹脂M内に封入された樹脂モールドウエーハ9を得る。凹部1aに樹脂Mを充填する際には、大気雰囲気の下で凹部1aを上方に向け、重力によって樹脂Mを凹部1a内に流し込めばよい。
次いで、樹脂モールドウエーハ9を、ウエーハ1の表面に形成されている分割予定ライン2に沿って切断、分割し、図8に示すような、半導体チップ3に複数の半導体チップ(図8では21〜23の3つ)が積層されて樹脂モールドされた個片化した半導体パッケージ(デバイスパッケージ)3Aを複数得る。樹脂モールドウエーハ9は、図10に示すダイシングテープ31に貼着して支持した状態として、図11に示すダイシング装置40によって好適に切断、分割することができる。
1a…凹部
1b…環状壁部
3…半導体チップ(デバイス)
3A…半導体パッケージ(デバイスパッケージ)
4…デバイス領域
5…外周余剰領域
9…樹脂モールドウエーハ
10…研削装置
21〜23…半導体チップ(デバイスチップ)
40…ダイシング装置
M…樹脂
Claims (2)
- 分割予定ラインによって複数のデバイスが区画されたデバイス領域と、このデバイス領域を囲繞する外周余剰領域とが表面に形成されたウエーハの裏面の、前記デバイス領域に対応する領域を薄化して、該裏面側に凹部を形成する裏面凹部形成工程と、
前記ウエーハの前記裏面における前記各デバイスに対応する箇所に、デバイスチップをそれぞれ積層するデバイスチップ積層工程と、
前記各デバイスと、これらデバイスに対応して積層された前記各デバイスチップとをそれぞれ電気的に接続する接続工程と、
前記ウエーハの前記凹部にモールド用の樹脂を充填して固化させ、前記デバイスチップが該樹脂内に封入された樹脂モールドウエーハを得る樹脂封入工程と、
前記樹脂モールドウエーハを、前記分割予定ラインに沿って切断し、前記デバイスに前記デバイスチップが積層されて樹脂モールドされた複数のデバイスパッケージを個片化させる個片化工程と
を備えることを特徴とするデバイスパッケージの製造方法。 - 前記ウエーハが、前記裏面凹部形成工程よりも前の段階で、前記凹部が形成された後の前記デバイス領域の厚さに至らない範囲で前記裏面全面が研削されることにより薄化処理されていることを特徴とする請求項1に記載のデバイスパッケージの製造方法。
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Application Number | Priority Date | Filing Date | Title |
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JP2006068458A JP2007250599A (ja) | 2006-03-14 | 2006-03-14 | デバイスパッケージの製造方法 |
US11/715,999 US7608481B2 (en) | 2006-03-14 | 2007-03-09 | Method for producing semiconductor package |
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JP2006068458A JP2007250599A (ja) | 2006-03-14 | 2006-03-14 | デバイスパッケージの製造方法 |
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Cited By (3)
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JP2009224622A (ja) * | 2008-03-17 | 2009-10-01 | Shindengen Electric Mfg Co Ltd | 半導体チップの製造方法、半導体ウエハおよび半導体チップ |
KR101061180B1 (ko) * | 2009-06-29 | 2011-09-01 | 주식회사 하이닉스반도체 | 반도체 패키지 |
JP2013004836A (ja) * | 2011-06-20 | 2013-01-07 | Disco Abrasive Syst Ltd | 半導体ウエーハの加工方法 |
Families Citing this family (5)
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JP5221279B2 (ja) * | 2008-10-22 | 2013-06-26 | 株式会社ディスコ | 積層デバイスの製造方法 |
US8895440B2 (en) * | 2010-08-06 | 2014-11-25 | Stats Chippac, Ltd. | Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV |
US9111946B2 (en) * | 2012-12-20 | 2015-08-18 | Invensas Corporation | Method of thinning a wafer to provide a raised peripheral edge |
US9698070B2 (en) * | 2013-04-11 | 2017-07-04 | Infineon Technologies Ag | Arrangement having a plurality of chips and a chip carrier, and a processing arrangement |
KR102327142B1 (ko) | 2015-06-11 | 2021-11-16 | 삼성전자주식회사 | 웨이퍼 레벨 패키지 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0555454A (ja) * | 1991-08-22 | 1993-03-05 | Honda Motor Co Ltd | 半導体装置と、その製造方法 |
JPH1050718A (ja) * | 1996-08-07 | 1998-02-20 | Hitachi Ltd | 半導体装置の製造方法 |
JP2003282817A (ja) * | 2002-03-27 | 2003-10-03 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2005123425A (ja) * | 2003-10-17 | 2005-05-12 | Toshiba Corp | 半導体基板の製造方法、半導体基板及び半導体装置の製造方法 |
JP2007173487A (ja) * | 2005-12-21 | 2007-07-05 | Disco Abrasive Syst Ltd | ウエーハの加工方法および装置 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI254387B (en) * | 2004-09-10 | 2006-05-01 | Advanced Semiconductor Eng | Wafer stacking package method |
JP2007019379A (ja) | 2005-07-11 | 2007-01-25 | Disco Abrasive Syst Ltd | ウェーハの加工方法 |
-
2006
- 2006-03-14 JP JP2006068458A patent/JP2007250599A/ja active Pending
-
2007
- 2007-03-09 US US11/715,999 patent/US7608481B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0555454A (ja) * | 1991-08-22 | 1993-03-05 | Honda Motor Co Ltd | 半導体装置と、その製造方法 |
JPH1050718A (ja) * | 1996-08-07 | 1998-02-20 | Hitachi Ltd | 半導体装置の製造方法 |
JP2003282817A (ja) * | 2002-03-27 | 2003-10-03 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP2005123425A (ja) * | 2003-10-17 | 2005-05-12 | Toshiba Corp | 半導体基板の製造方法、半導体基板及び半導体装置の製造方法 |
JP2007173487A (ja) * | 2005-12-21 | 2007-07-05 | Disco Abrasive Syst Ltd | ウエーハの加工方法および装置 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009224622A (ja) * | 2008-03-17 | 2009-10-01 | Shindengen Electric Mfg Co Ltd | 半導体チップの製造方法、半導体ウエハおよび半導体チップ |
KR101061180B1 (ko) * | 2009-06-29 | 2011-09-01 | 주식회사 하이닉스반도체 | 반도체 패키지 |
JP2013004836A (ja) * | 2011-06-20 | 2013-01-07 | Disco Abrasive Syst Ltd | 半導体ウエーハの加工方法 |
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