TW202240843A - 具有一或多個至少部分嵌入於重佈層之晶粒之半導體裝置總成及系統及其製造方法 - Google Patents

具有一或多個至少部分嵌入於重佈層之晶粒之半導體裝置總成及系統及其製造方法 Download PDF

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TW202240843A
TW202240843A TW110149070A TW110149070A TW202240843A TW 202240843 A TW202240843 A TW 202240843A TW 110149070 A TW110149070 A TW 110149070A TW 110149070 A TW110149070 A TW 110149070A TW 202240843 A TW202240843 A TW 202240843A
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die
rdl
semiconductor device
device assembly
dies
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TW110149070A
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白宗植
楊博智
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美商美光科技公司
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Abstract

本發明提供一種半導體裝置總成。該總成包括一重佈層(RDL)，該RDL包括一第一側上之複數個外部觸點及與該第一側相對之一第二側上之複數個內部觸點。該總成進一步包括至少部分地嵌入於該RDL中且具有在該RDL之該第一側與該第二側之間的一主動表面之一第一晶粒。該總成進一步包括安置在控制器晶粒及該RDL上之一或多個第二晶粒，其中該一或多個第二晶粒電耦合至該等內部觸點。該總成進一步包括至少部分地囊封該一或多個第二晶粒之一囊封體。

Description

具有一或多個至少部分嵌入於重佈層之晶粒之半導體裝置總成及系統及其製造方法
本發明大體上係關於半導體裝置，且更具體言之，係關於具有至少部分地嵌入於重佈層(RDL)中之一或多個晶粒之半導體裝置總成及系統及其製造方法。
包括記憶體晶片、微處理器晶片及成像器晶片之已封裝半導體晶粒通常包括安裝在基板上且圍封在保護性覆蓋物中或用導熱蓋封蓋之一或多個半導體晶粒。在許多應用中，期望半導體裝置總成儘可能地薄。因此，需要更薄的半導體裝置總成設計及其製造方法。
半導體裝置總成併入在封裝高度備受關注之多種產品(例如，行動電話、平板電腦、膝上型電腦等等)中。當總成中之各種裝置之大小迥異時，設計較薄總成可能尤其具有挑戰性。舉例而言，記憶體控制器晶粒可比安置於其上之記憶體晶粒小得多，以致使需要間隔件來支撐較小晶粒上之更大晶粒之周邊，此會增加總成設計之厚度、成本及複雜性。
為了解決此等挑戰，本發明技術之實施例提供具有晶粒嵌入於其中且一或多個額外晶粒設置於其上之重佈層(RDL)之半導體裝置總成。嵌入式晶粒及一或多個額外晶粒可藉由形成在RDL中之一或多個通孔及跡線彼此電耦合及/或電耦合至總成之外部觸點。藉由將晶粒(例如，控制器晶粒)嵌入於RDL中，可極大地減小總成厚度，且可更容易地執行製造(例如，在嵌板、晶圓或條帶層級處，且不需要間隔件或厚的有機基板)。
就此而言，圖1A至圖1I繪示根據本發明技術之各種實施例之半導體裝置總成100在各個製造階段的簡化示意性橫截面圖。如參考圖1A可看出，晶粒(例如，記憶體控制器晶粒) 120安置在臨時載體晶圓103上。晶粒120具有主動表面120b及背表面120a，且在本實施例中，背表面120a (例如，使用臨時黏合劑)附接至臨時載體晶圓103。轉向圖1B，介電材料(例如，感光聚醯亞胺(PSPI)) 111之層形成在載體晶圓103上且圍繞晶粒120。隨後圖案化介電材料111 (如圖1C中所展示)，且將導電材料鍍敷至經圖案化介電材料111中(如圖1D中所展示)以形成多種導電特徵，例如內部觸點112、通孔113及跡線114。此等導電特徵可將電連接(例如，電力、接地及信號)提供至嵌入式晶粒120、內部觸點112及/或外部觸點(下文更詳細地說明)。
重複安置及圖案化介電材料且鍍敷導電特徵之此過程直至RDL 110完成，如圖1E中所展示，其中高度界定在其上設置有複數個外部觸點之第一側110a與其上設置有複數個內部觸點之第二側110b之間。根據本發明技術之一個態樣，RDL 110之高度可小於100 µm，或小於75 µm，或甚至小於50 µm，此取決於嵌入式晶粒120之厚度及每一反覆形成之導電特徵層之厚度。
在RDL 110完成的情況下，第二載體晶圓104 (例如，使用臨時黏合劑)附接至RDL 110a之第一側，如圖1F中所展示，且翻轉總成100以使得可去除第一臨時載體晶圓103，從而曝露嵌入式晶粒120之背側120a及RDL 110a之第一側，如圖1G中所展示。
轉向圖1H，一或多個晶粒(例如，記憶體晶粒，例如DRAM及/或NAND晶粒) 130a至130d可安置在RDL 110及嵌入式晶粒120上(例如，使用晶粒附接膜或類似黏合劑)，且可藉由在晶粒中之每一者上之接觸襯墊131與RDL 110之第一側110a上之內部觸點112之間形成線接合件132而電連接至RDL 110，如圖1H中所展示。囊封材料140可隨後形成在一或多個晶粒130a至130d及線接合件132周圍以對其提供結構完整性及環境密封。隨後可去除第二載體晶圓104，且可在RDL 110之第二側110b上之對應複數個外部觸點上形成複數個焊球115。
根據本發明技術之一個態樣，可在晶圓、嵌板或條帶層級下執行前述步驟中之一些或全部以促進大量製造。在此階段，或視情況更早，總成100可自形成其之晶圓、嵌板或條帶單體化(例如，藉由鋸切、電漿切割、雷射等)，將其與其他同時形成之總成分離。成品總成100享有優於習知總成之數個優點，因為嵌入式晶粒120減小總體封裝厚度，且避免需要間隔件來支撐在其上之一或多個較大晶粒(例如，具有較大規劃區域之晶粒)。此外，前述過程不需要昂貴的底部填充材料，且享有比其他製造方法更低的熱預算(例如，歸因於RDL 110中之導電特徵之鍍敷)。
儘管在前述實例中，已說明且描述具有部分地嵌入於RDL內之晶粒(例如，具有晶粒之與RDL之表面齊平地曝露之一個表面)之半導體裝置總成，但在本發明技術之另一實施例中，一或多個晶粒可完全嵌入於RDL內(例如，由RDL包圍所有側)，如下文更詳細地闡述。
就此而言，圖2A至圖2I繪示根據本發明技術之各種實施例之半導體裝置總成200在各個製造階段的簡化示意性橫截面圖。如參考圖2A可見，介電材料(例如，感光聚醯亞胺(PSPI)) 211之層形成在載體晶圓204上，且隨後(視情況，反覆地)圖案化且鍍敷以形成RDL之部分，如圖2B中所展示。隨後，晶粒(例如，記憶體控制器晶粒) 220安置在部分製造之RDL上，如圖2C中所展示。晶粒220具有主動表面220b及背表面220a，且在本實施例中，背表面220a面向下安置在部分製造之RDL上(例如，背側面向將為總成200之外部觸點)。轉向圖2D，另一介電材料(例如，感光聚醯亞胺(PSPI)) 211之層形成在繼續其製造之部分製造之RDL上，且圍繞晶粒220。再次圖案化介電材料211 (如圖2E中所展示)，且將導電材料再次鍍敷至經圖案化介電材料211中(如圖2F中所展示)以形成多種導電特徵，例如通孔213及跡線214。此等導電特徵可將電連接(例如，電力、接地及信號)提供至嵌入式晶粒220、RDL之內部觸點(下文更詳細地描述)及/或RDL之外部觸點(下文更詳細地說明)。
安置及圖案化介電材料且鍍敷導電特徵之此過程可重複直至RDL 210完成，如圖2G中所展示，其中高度界定在其上設置有複數個內部觸點212之第一側210a與其上設置有複數個外部觸點之第二側210b之間。根據本發明技術之一個態樣，RDL 210之高度可小於100 µm，或小於75 µm，或甚至小於50 µm，此取決於嵌入式晶粒220之厚度及每一反覆形成之導電特徵層之厚度。
在RDL 210完成的情況下，一或多個晶粒(例如，記憶體晶粒，例如DRAM及/或NAND晶粒) 230a至230d可安置在RDL 210上 (例如，使用晶粒附接膜或類似黏合劑)，且可藉由在晶粒中之每一者上之接觸襯墊231與RDL 210之第一側210a上之內部觸點212之間形成線接合件232而電連接至RDL 210，如圖2H中所展示。囊封材料240可隨後形成在一或多個晶粒230a至230d及線接合件232周圍以對其提供結構完整性及環境密封。隨後可去除載體晶圓204，且可在RDL 210之第二側210b上之對應複數個外部觸點上形成複數個焊球215。
根據本發明技術之一個態樣，可在晶圓、嵌板或條帶層級處執行前述步驟中之一些或全部以促進大量製造。在此階段，或視情況在更早階段，總成200可自形成其之晶圓、嵌板或條帶單體化(例如，藉由鋸切、電漿切割、雷射等)，將其與其他同時形成之總成分離。成品總成200享有優於習知總成之數個優點，因為嵌入式晶粒220減小總體封裝厚度，且避免需要間隔件來支撐在其上之一或多個較大晶粒(例如，具有較大規劃區域之晶粒)。此外，前述過程不需要昂貴的底部填充材料，且享有比其他製造方法更低的熱預算(例如，歸因於RDL 210中之導電特徵之鍍敷)。
儘管在前述實例中，半導體裝置總成已描述且說明為包括以疊瓦式堆疊配置且藉由線接合件連接至RDL之複數個記憶體晶粒，但在本發明技術之其他實施例中，晶粒之其他配置可類似地得益於併入有具有嵌入式晶粒之RDL之設計。舉例而言，除以疊瓦式堆疊配置且藉由線接合件連接之晶粒之外或代替以疊瓦式堆疊配置且藉由線接合件連接之晶粒，晶粒可以豎直堆疊設置且與其他連接方法連接，例如TSVS、焊料互連、銅-銅連接、混合接合等。在一些實施例中，半導體裝置總成可僅包括在RDL上之單一晶粒，而非複數個晶粒，在該RDL中嵌入另一晶粒(例如，經由直接晶片附接(DCA)而附接)。熟習此項技術者將瞭解，實例之前述清單並非窮盡性的，而是許多其他半導體裝置總成可類似地組態有RDL，在該RDL中至少部分地嵌入一或多個晶粒，已作必要的修正。
儘管在前述實例中，半導體裝置總成已描述且說明為包括具有單一嵌入式晶粒之RDL，但在本發明技術之其他實施例中，多個晶粒可以類似於上文所描述之方式的方式嵌入於半導體裝置總成之RDL內。在一些實施例中，可組合部分地嵌入及完全地嵌入晶粒之前述方法以在RDL內提供不同高度處之嵌入式晶粒。替代地，由於介電安置、圖案化及鍍敷導電特徵之反覆性質，多個晶粒可嵌入重疊或豎直對準之位置。
此外，儘管上文所描述之實例中之嵌入式晶粒已識別為控制器晶粒(例如，用於受管理NAND (mNAND)裝置)，且堆疊之一或多個晶粒已識別為記憶體晶粒(例如，NAND或DRAM，或其組合)，但熟習此項技術者將容易瞭解，前述總成拓樸可適用於其他晶粒類型。舉例而言，除記憶體晶粒之外或代替記憶體晶粒，其他種類之半導體裝置可設置在半導體裝置總成中，例如邏輯晶粒、特殊應用積體電路(ASIC)晶粒、場可程式化閘陣列(FPGA)晶粒等。代替嵌入式控制器晶粒，其他晶粒類型可嵌入於RDL中(例如，記憶體晶粒、其他邏輯晶粒、ASIC晶粒、FPGA晶粒等)。
圖3為繪示製造半導體裝置總成之方法的流程圖。方法包括在第一載體晶圓上安置第一晶粒(框310)；在第一晶粒周圍及上形成重佈層(RDL) (框320)；及將第二載體晶圓附接至RDL之第一側(框330)。方法進一步包括去除第一載體晶圓以曝露第一晶粒及RDL之第二側(框340)；將一或多個第二晶粒附接至RDL之第二側(框350)；及囊封一或多個第二晶粒(框360)。方法進一步包括自嵌板、晶圓或條帶將半導體裝置封裝單體化(框370)及將對應複數個焊球附接至複數個外部觸點(框380)。
圖4為繪示製造半導體裝置總成之方法的流程圖。方法包括在載體晶圓上安置第一晶粒(框410)；在第一晶粒周圍及上形成重佈層(RDL) (框420)；及將一或多個第二晶粒附接至RDL之第二側(框430)。方法進一步包括囊封一或多個第二晶粒(框440)；自嵌板、晶圓或條帶將半導體裝置封裝單體化(框450)；及將對應複數個焊球附接至複數個外部觸點(框460)。
上文參考圖1A至圖4所描述之晶粒支撐結構及/或半導體裝置總成中之任一者可併入至無數較大及/或更複雜的系統中之任一者中，該等系統之代表性實例為圖5中示意性地展示之系統500。系統500可包括半導體裝置總成510、電源520、驅動器530、處理器540及/或其他子系統或組件550。半導體裝置總成510可包括大體上類似於上文所描述之半導體裝置總成之特徵的特徵。所得系統500可執行廣泛多種功能中之任一者，例如記憶體儲存、資料處理及/或其他合適功能。因此，代表性系統500可包括但不限於手持式裝置(例如，行動電話、平板電腦、數位閱讀器及數位音訊播放器)、電腦、車輛及其他機器及電器。系統500之組件可容納在單一單元中或分佈在多個互連單元上(例如，藉由通信網路)。系統500之組件亦可包括遠端裝置及廣泛多種電腦可讀媒體中之任一者。
本文中所論述之包括記憶體裝置之裝置可形成在例如矽、鍺、矽鍺合金、砷化鎵、氮化鎵等半導體基板或晶粒上。在一些情況下，基板為半導體晶圓。在其他情況下，基板可為絕緣體上矽(SOI)基板，例如玻璃上矽(SOG)或藍寶石上矽(SOP)，或另一基板上之半導體材料之磊晶層。可藉由使用包括但不限於磷、硼或砷之各種化學物種之摻雜來控制基板或基板之子區之導電性。可在基板之初始形成或生長期間，藉由離子植入或藉由任何其他摻雜方法來執行摻雜。
本文中所描述之功能可以硬體、由處理器執行之軟體、韌體或其任何組合來實施。其他實例及實施方案在本發明及所附申請專利範圍之範疇內。實施功能之特徵也可在實體上位於各個位置處，包括經分佈以使得功能之各部分在不同實體位置處實施。
如本文(包括在申請專利範圍中)所使用，如在項目清單(例如，以例如「中之至少一者」或「中之一或多者」等片語結尾之項目清單)中所使用之「或」指示包括性清單，使得例如A、B或C中之至少一者之清單意謂A或B或C或AB或AC或BC或ABC (即，A及B及C)。此外，如本文所使用，片語「基於」不應被理解為係指一組封閉條件。舉例而言，在不脫離本發明之範疇的情況下，描述為「基於條件A」之例示性步驟可基於條件A及條件B兩者。換言之，如本文所使用，片語「基於」應同樣地解釋為片語「至少部分地基於」。
如本文所使用，術語「豎直」、「橫向」、「上部」、「下部」、「之上」及「之下」可鑒於圖中所展示之定向而係指半導體裝置中之特徵之相對方向或位置。舉例而言，「上部」或「最上部」可係指比另一特徵更接近頁面之頂部定位之特徵。然而，此等術語應廣泛地理解為包括具有其他定向之半導體裝置，該等定向係例如倒置或傾斜定向，其中頂部/底部、上方/下方、之上/之下、向上/向下及左側/右側可取決於定向而互換。
應注意，上文描述之方法描述了可能的實施方案，且操作及步驟可重新配置或以其他方式加以修改，且其他實施方案係可能的。此外，可組合來自該等方法中之兩者或更多者之實施例。
自前述內容將瞭解，本文中已出於說明之目的而描述本發明之特定實施例，但可在不偏離本發明之範疇的情況下進行各種修改。相反，在前述描述中，論述了許多特定細節以提供對本發明技術之實施例之透徹及啟發性描述。然而，熟習相關技術者將認識到，可在無特定細節中之一或多者的情況下實踐本發明。在其他情況下，未展示或未詳細地描述通常與記憶體系統及裝置相關聯之眾所周知的結構或操作，以避免混淆技術之其他態樣。一般而言，應理解，除了本文中所揭示之彼等特定實施例之外的各種其他裝置、系統及方法可在本發明技術之範疇內。
100:半導體裝置總成 103:第一臨時載體晶圓 104:第二載體晶圓 110:重佈層(RDL) 110a:第一側 110b:第二側 111:介電材料 112:內部觸點 113:通孔 114:跡線 115:焊球 120:晶粒 120a:背表面 120b:主動表面 130a:晶粒 130b:晶粒 130c:晶粒 130d:晶粒 131:接觸襯墊 132:線接合件 140:囊封材料 200:半導體裝置總成 204:載體晶圓 210:重佈層(RDL) 210a:第一側 210b:第二側 211:介電材料 212:內部觸點 213:通孔 214:跡線 215:焊球 220:晶粒 220a:背表面 220b:主動表面 230a:晶粒 230b:晶粒 230c:晶粒 230d:晶粒 231:接觸襯墊 232:線接合件 240:囊封材料 310:框 320:框 330:框 340:框 350:框 360:框 370:框 380:框 410:框 420:框 430:框 440:框 450:框 460:框 500:系統 510:半導體裝置總成 520:電源 530:驅動器 540:處理器 550:其他子系統或組件
圖1A至圖1I繪示根據本發明技術之各種實施例之半導體裝置總成在各個製造階段的簡化示意性橫截面圖。
圖2A至圖2I繪示根據本發明技術之各種實施例之半導體裝置總成在各個製造階段的簡化示意性橫截面圖。
圖3為繪示根據本發明技術之實施例的製造半導體裝置總成之方法的流程圖。
圖4為繪示根據本發明技術之實施例的製造半導體裝置總成之方法的流程圖。
圖5為展示包括根據本發明技術之實施例而組態之半導體裝置總成之系統的示意圖。
100:半導體裝置總成
110:重佈層(RDL)
110a:第一側
110b:第二側
111:介電材料
112:內部觸點
113:通孔
114:跡線
115:焊球
120:晶粒
120a:背表面
120b:主動表面
130a:晶粒
130b:晶粒
130c:晶粒
130d:晶粒
131:接觸襯墊
132:線接合件
140:囊封材料

Claims (20)

  1. 一種半導體裝置總成，其包含： 一重佈層(RDL)，其包括一第一側上之複數個外部觸點及與該第一側相對之一第二側上之複數個內部觸點； 一第一晶粒，其至少部分地嵌入於該RDL中且具有在該RDL之該第一側與該第二側之間的一主動表面； 一或多個第二晶粒，其安置在該第一晶粒及該RDL上，該一或多個第二晶粒電耦合至該等內部觸點；以及 一囊封體，其至少部分地囊封該一或多個第二晶粒。
  2. 如請求項1之半導體裝置總成，其中該第一晶粒具有與該RDL之該第二側齊平之一背表面。
  3. 如請求項1之半導體裝置總成，其中該第一晶粒具有嵌入於該RDL內該第一側與該第二側之間的一背表面。
  4. 如請求項1之半導體裝置總成，其中該第一晶粒之該主動表面背對該複數個外部觸點。
  5. 如請求項1之半導體裝置總成，其中該第一晶粒之該主動表面藉由安置在該RDL中之一或多個跡線及/或通孔電耦合至該複數個外部觸點中之一或多者、該複數個內部觸點中之一或多者或其一組合。
  6. 如請求項1之半導體裝置總成，其中該RDL包括一感光聚醯亞胺(PSPI)材料。
  7. 如請求項1之半導體裝置總成，其中該一或多個第二晶粒包括黏附至該RDL之該第二側之一最低晶粒。
  8. 如請求項7之半導體裝置總成，其中該最低晶粒進一步黏附至該第一晶粒之一背表面。
  9. 如請求項1之半導體裝置總成，其中該一或多個第二晶粒各自具有背對該RDL之該第二側之一主動表面，其中該一或多個第二晶粒中之每一者之該主動表面包括藉由一或多個線接合件電耦合至該複數個內部觸點中之一或多者之一或多個襯墊。
  10. 如請求項1之半導體裝置總成，其中該一或多個第二晶粒包括至少一個DRAM晶粒及至少一個NAND晶粒。
  11. 如請求項1之半導體裝置總成，其進一步包含形成在該複數個外部封裝觸點上之對應複數個焊球。
  12. 如請求項1之半導體裝置總成，其中該複數個內部觸點包括與該第一晶粒豎直對準之一或多個內部觸點。
  13. 一種形成一半導體裝置總成之方法，該方法包含： 在一載體晶圓上安置一第一晶粒； 在該第一晶粒周圍及上形成一重佈層(RDL)，該RDL包括一第一側上之複數個外部觸點及與該第一側相對之一第二側上之複數個內部觸點； 將一或多個第二晶粒附接至該RDL之該第二側；以及 囊封該一或多個第二晶粒。
  14. 如請求項13之方法，其中該第一晶粒之一主動表面藉由安置在該RDL中之一或多個跡線及/或通孔電耦合至該複數個外部觸點中之一或多者、該複數個內部觸點中之一或多者或其一組合。
  15. 如請求項13之方法，其中該第一晶粒被安置成其一背表面與第一載體晶圓接觸。
  16. 如請求項13之方法，其中該載體晶圓為一第一載體晶圓，且該方法進一步包含： 將一第二載體晶圓附接至該RDL之該第一側；以及 去除該第一載體晶圓以曝露該第一晶粒及該RDL之該第二側。
  17. 如請求項13之方法，其中該第一晶粒被安置成其一背表面嵌入於該RDL內該第一側與該第二側之間。
  18. 如請求項13之方法，其中形成該RDL包含反覆地(i)安置及圖案化一感光聚醯亞胺(PSPI)材料，及(ii)形成對應於該經圖案化PSPI之複數個導電跡線及/或通孔。
  19. 如請求項13之方法，其進一步包含自包含複數個其他同時形成之半導體裝置總成之一嵌板、晶圓或條帶將該半導體裝置總成單體化。
  20. 如請求項13之方法，其進一步包含將對應複數個焊球附接至該複數個外部觸點。
TW110149070A 2020-12-30 2021-12-28 具有一或多個至少部分嵌入於重佈層之晶粒之半導體裝置總成及系統及其製造方法 TW202240843A (zh)

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