JP2020508569A - ダイ基板拡張部を有する積み重ねられた半導体ダイアセンブリ - Google Patents
ダイ基板拡張部を有する積み重ねられた半導体ダイアセンブリ Download PDFInfo
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- JP2020508569A JP2020508569A JP2019544691A JP2019544691A JP2020508569A JP 2020508569 A JP2020508569 A JP 2020508569A JP 2019544691 A JP2019544691 A JP 2019544691A JP 2019544691 A JP2019544691 A JP 2019544691A JP 2020508569 A JP2020508569 A JP 2020508569A
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Abstract
Description
の付加的なダイがその上に積み重ねられ得るダイ基板又は同様の支持構造を共に形成する成型材料とを含む。用語“半導体デバイス”は、一般的に、半導体材料を含む固体状態デバイスを指す。半導体デバイスは、例えば、半導体基板、ウエハ、又はウエハ若しくは基板からシンギュレーションされたダイを含み得る。開示全体を通じて、半導体デバイスは、一般的に、半導体ダイの文脈で説明されるが、半導体デバイスは半導体ダイに限定されない。
方の第1のダイ110の第1のフットプリント又は第1の外周P1を画定する。ダイ基板122の第1の成型材料140が平面図形を少なくとも部分的に画定すると共に、第2のダイ基板122は、第2のダイ120の第2のフットプリント又は第2の外周P2を画定する。第1のダイ基板111の第1の外縁113の領域がパッケージ基板102の一部を第1の距離d1だけ張り出すように、及び第2のダイ基板122の第2の外縁123の領域が第1の外縁113を越えて第2の距離d2に広がるように、第1の外周P1及び第2の外周P2は、相互に重なる。図1Bに説明する実施形態では、第2の距離d2に広がる第2の外縁123の領域は、第1の成型材料140の一部と、第2のダイ120の半導体基板130の一部と含む。
。パッケージ基板102は更に、第2の外周P2の両対辺に位置付けられ、且つ第1の基板パッド108aのアレイに概して垂直な方向に整列された第2の基板パッド108bを含む。第2の基板パッド108bは、第2のワイヤボンドコネクタ107b(例えば、ワイヤボンド)によって、第2のダイ120の半導体基板130の上面124上の対応するボンドパッド109bに結合される。ボンドパッド109aは、第1の成型材料140と概して位置合わせされ、このことは、ワイヤボンディングの信頼性を増加させること、及びチップの亀裂を防止することを助け得る。
、アセンブリ100は、3つ以上のメモリダイ(例えば、4つのダイ、8つのダイ等)又は唯1つのメモリダイを含み得る。更に、様々な実施形態では、アセンブリ100のダイは異なるサイズを有し得る。例えば、幾つかの実施形態では、第1のダイ110の第1の外周P1全体は、第2のダイ120の第2の外周P2全体の外側であり得る。
は、上で説明したように、ワイヤボンディング後にダイ110及び120を入れるためにダイスタック及びパッケージ基板102に渡って流れ得る。
を画定する。第1のダイ基板111の第1の外縁113の領域がパッケージ基板102の一部を第1の距離d1だけ張り出すように、及び第2のダイ基板122の第2の外縁123の領域が第1の外縁113を越えて第2の距離d2に広がるように、第1の外周P1及び第2の外周P2は、相互に重なる。図1Bに説明する実施形態では、第2の距離d2に広がる第2の外縁123の領域は、第1の成型材料140の一部と、第2のダイ120の半導体基板130の一部と含む。
Claims (24)
- パッケージ基板と、
前記パッケージ基板に取り付けられたダイのスタックであって、前記ダイのスタックは、
第1のダイ基板を有する第1のダイと、
前記第1のダイ基板に取り付けられた第2のダイ基板を有する第2のダイであって、前記第2のダイは、(1)周辺部分を有する半導体基板と(2)前記周辺部分から広がる第1の成型材料とを含み、前記周辺部分及び前記第1の成型材料は前記第2のダイ基板を画定する、前記第2のダイと
を含む、前記ダイのスタックと、
前記ダイのスタックを封止する第2の成型材料と
を含む、半導体ダイアセンブリ。 - 前記第2のダイは前記パッケージ基板と前記第1のダイとの間にあり、前記第1のダイ基板は、前記第2のダイの前記半導体基板に取り付けられた第1の部分と、前記第2のダイの前記第1の成型材料に取り付けられた第2の部分とを含む、請求項1に記載の半導体ダイアセンブリ。
- 前記第1のダイ基板は外周を有し、前記第2のダイの前記第1の成型材料及び前記半導体基板の両方は前記外周を越えて広がる、請求項2に記載の半導体ダイアセンブリ。
- 前記第1の成型材料は、前記第2のダイの前記半導体基板を完全に取り囲む、請求項1に記載の半導体ダイアセンブリ。
- 前記第2のダイの前記第1の成型材料及び前記半導体基板は同一平面にある、請求項1に記載の半導体ダイアセンブリ。
- 前記第1のダイ基板は、前記第2のダイの前記第1の成型材料の一部の上方に広がる外縁を含み、
前記パッケージ基板は、前記パッケージ基板の周辺に基板パッドを含み、
前記第1のダイは、前記第1のダイの周辺にボンドパッドを含み、
前記第1のボンドパッドの各々は、前記第2のダイの前記第1の成型材料と概して位置合わせされ、前記基板パッド及び対応するボンドパッドは、ワイヤボンドを介して電気的に接続される、
請求項1に記載の半導体ダイアセンブリ。 - 前記第1のダイは、前記パッケージ基板と前記第2のダイとの間にあり、前記第2のダイの前記第1の成型材料は、前記第1のダイを越えて広がり、前記パッケージ基板を張り出す、請求項1に記載の半導体ダイアセンブリ。
- 前記パッケージ基板と前記第2のダイ基板との間のダイアタッチフィルムを更に含み、前記ダイアタッチフィルムは、前記第2のダイの前記第1の成型材料及び前記半導体基板の両方に取り付けられる、請求項1に記載の半導体ダイアセンブリ。
- 前記第2のダイの前記第1の成型材料は、エポキシ樹脂及び熱硬化性材料の内の少なくとも1つを含む、請求項1に記載の半導体ダイアセンブリ。
- 前記第1及び前記第2のダイの内の少なくとも1つはメモリダイである、請求項1に記載の半導体ダイアセンブリ。
- パッケージ基板と、
前記パッケージ基板に搭載された第1のダイであって、前記第1のダイは第1のダイ基板を含む、前記第1のダイと、
前記第1のダイに搭載された第2のダイであって、前記第2のダイは、前記第1のダイ基板に取り付けられた第2のダイ基板を含む、前記第2のダイと
を含み、
前記第1及び前記第2のダイ基板の内の少なくとも1つは、半導体基板と、前記半導体基板の外周に結合されたダイ基板拡張部とを含み、前記ダイ基板拡張部は成型材料を含み、前記成型材料は平面図形を少なくとも部分的に画定する、
半導体デバイス。 - 前記成型材料は第1の成型材料であり、前記半導体デバイスは、前記第1及び前記第2のダイを封止する第2の成型材料を更に含む、請求項11に記載の半導体デバイス。
- 前記第1のダイを前記第2のダイに取り付けるダイアタッチフィルムを更に含み、前記半導体基板は、前記ダイアタッチフィルムに取り付けられた第1の面を含み、前記成型材料は、前記ダイアタッチフィルムに取り付けられた第2の面を含む、請求項11に記載の半導体デバイス。
- 前記ダイアタッチフィルムは第1のダイアタッチフィルムであり、前記第1のダイは、前記半導体基板と前記基板拡張部とを含み、前記半導体デバイスは、前記第1のダイの前記半導体基板及び前記基板拡張部の両方に前記パッケージ基板を取り付ける第2のダイアタッチフィルムを更に含む、請求項13に記載の半導体デバイス。
- 半導体デバイスを製造する方法であって、
半導体基板の一部の上方に成型材料を成型することであって、前記成型材料は、前記半導体基板の前記一部から外側に広がり、第1のダイの平面図形を画定する、前記成型することと、
ダイスタックを形成するために、前記第1のダイに第2のダイを取り付けることであって、前記第2のダイを取り付けることは、前記第2のダイを前記半導体基板及び前記成型材料に取り付けることを含む、前記取り付けることと、
前記ダイスタックをパッケージ基板に搭載することと
を含む、
方法。 - 前記搭載することは、前記第1のダイの前記半導体基板及び前記成型材料の両方に前記パッケージ基板を取り付けることを含む、請求項15に記載の方法。
- 前記搭載することは、前記第2のダイを前記パッケージ基板に取り付けることを含む、請求項15に記載の方法。
- 前記成型材料は第1の成型材料であり、前記方法は、パッケージケースを形成するために、前記第1の成型材料の上方に第2の成型材料を成型することを更に含む、請求項18に記載の方法。
- 前記成型することは、
前記第1のダイの前記半導体基板を一時的積載部に取り付けることと、
前記半導体基板及び前記一時的積載部の上方に前記成型材料を成型することと、
前記半導体基板の第1の面と前記成型材料の第2の面とを露出するために、前記成型材
料を薄くすることであって、前記第1の面は前記第2の面に隣接する、前記薄くすることと
を含む、請求項15に記載の方法。 - 前記パッケージ基板を前記第1及び前記第2の面に取り付けることを更に含む、請求項19に記載の方法。
- 前記第2のダイを前記第1及び前記第2の面に取り付けることを更に含む、請求項19に記載の方法。
- 前記成型することの後に前記パッケージ基板及び前記ダイスタックの上方に封止材料を流すことを更に含む、請求項19に記載の方法。
- 前記第1及び前記第2のダイの内の少なくとも1つはメモリダイである、請求項15に記載の方法。
- 前記第1のダイの前記半導体基板はコントローラ回路を含む、請求項23に記載の方法。
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KR102305390B1 (ko) | 2021-09-28 |
WO2018156512A1 (en) | 2018-08-30 |
JP6998963B2 (ja) | 2022-01-18 |
JP2022010117A (ja) | 2022-01-14 |
US10553566B2 (en) | 2020-02-04 |
US20190043840A1 (en) | 2019-02-07 |
EP3586362A4 (en) | 2020-09-09 |
US11335667B2 (en) | 2022-05-17 |
EP3586362A1 (en) | 2020-01-01 |
CN110178217B (zh) | 2023-05-30 |
KR20190104236A (ko) | 2019-09-06 |
US10147705B2 (en) | 2018-12-04 |
US20200321316A1 (en) | 2020-10-08 |
JP7253601B2 (ja) | 2023-04-06 |
CN110178217A (zh) | 2019-08-27 |
TWI680541B (zh) | 2019-12-21 |
TW201842631A (zh) | 2018-12-01 |
US20180240782A1 (en) | 2018-08-23 |
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