TW201314757A - 於塗佈後研磨前之切塊 - Google Patents

於塗佈後研磨前之切塊 Download PDF

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TW201314757A
TW201314757A TW101126862A TW101126862A TW201314757A TW 201314757 A TW201314757 A TW 201314757A TW 101126862 A TW101126862 A TW 101126862A TW 101126862 A TW101126862 A TW 101126862A TW 201314757 A TW201314757 A TW 201314757A
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wafer
dicing
underfill
semiconductor
bumps
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Gina Hoang
Youn-Sang Kim
Rosette Guino
Qiaohong Huang
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Henkel Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本發明係將半導體晶圓單體化成個別半導體晶粒之方法，該半導體晶圓之頂部表面具有金屬預先連接凸塊且具有佈置於該等金屬預先連接凸塊上及附近之底部填充劑之塗層。該方法包含(A)提供半導體晶圓，其頂部表面具有金屬預先連接凸塊之陣列及佈置於該等金屬預先連接凸塊上及附近之底部填充劑之塗層；(B)穿過該等金屬預先連接凸塊之間之該底部填充劑切塊且切入該半導體晶圓之頂部表面中至最終期望晶圓厚度，從而產生切塊線；及(C)自該晶圓之背側移除晶圓材料至少至該等切塊線之深度，由此使所得晶粒自該晶圓單體化。

Description

於塗佈後研磨前之切塊
本發明係關於製造施加有底部填充劑囊封劑之半導體晶圓的方法。
電設備及電子設備之微型化及輕量化已導致需要更薄半導體裝置及更薄半導體封裝。
產生更薄半導體晶粒之方式係自半導體晶圓之背側移除過量材料，自該半導體晶圓切塊個別晶粒。過量晶圓之移除通常發生在研磨過程中，通常稱作背側研磨。在晶圓薄化之前將晶圓切塊成個別半導體電路時，該過程稱作「研磨之前切塊」或DBG。
產生更小且更有效半導體封裝之方式係採用具有金屬凸塊之陣列的封裝，該等金屬凸塊附接至封裝之活性面。金屬凸塊經佈置以與基板上之銲墊對齊。在使金屬凸塊重熔至熔體時，凸塊與銲墊連接，從而形成電連接及機械連接二者。
沿晶圓材料、金屬凸塊及基板存在熱失配，從而引起金屬互連受到重複熱循環之應力。此可潛在地導致失效。為抵消此問題，將囊封材料(稱作底部填充劑)佈置於圍繞並支撐金屬凸塊且介於晶圓與基板之間之空隙中。
半導體封裝製造之目前趨勢偏好完成盡可能多之晶圓級過程步驟，從而使得可同時而非單獨處理多個積體電路，如晶粒單體化之後所進行。在將晶圓切塊成個別半導體晶 粒之前將底部填充劑囊封劑施加於金屬凸塊之陣列及晶圓電路上係實施之晶圓級操作中之一者。
在典型過程中，具有金屬預先連接凸塊之半導體晶圓在金屬凸塊上經底部填充劑材料塗佈。將支撐膠帶(稱作背面研磨膠帶)層壓於晶圓頂部側上之底部填充劑材料上。藉由研磨或其他方式自晶圓背側移除晶圓材料。自晶圓頂部側上之底部填充劑移除背面研磨膠帶。在如下切塊期間將切塊膠帶施加至晶圓之背側以支撐晶圓。切塊可藉由雷射進行(此成本高)，或其可藉由切塊刀片以機械方式進行。由於薄化晶圓尤其易碎，故儘管使用切塊刀片較便宜，但其可對晶圓、電路及底部填充劑造成損害。
因此，業內需要將半導體晶圓單體化成個別半導體晶粒之方法，其中可預先施加底部填充劑，但其中機械切塊操作不會損壞具有凸塊之晶圓及底部填充劑。
本發明係將半導體晶圓單體化成個別半導體晶粒之方法，該半導體晶圓之頂部表面具有金屬預先連接凸塊且具有佈置於該等金屬預先連接凸塊上及附近之底部填充劑之塗層。
該方法包含(A)提供半導體晶圓，其頂部表面具有金屬預先連接凸塊之陣列及佈置於該等金屬預先連接凸塊上及附近之底部填充劑之塗層；(B)穿過該等金屬預先連接凸塊之間之該底部填充劑切塊且切入該半導體晶圓之頂部表面中至最終期望晶圓厚度，從而產生切塊線；及(C)自該 晶圓之背側移除晶圓材料至該等切塊線之深度，由此使所得晶粒自該晶圓單體化。
半導體晶圓係自半導體材料(通常矽、砷化鎵或類似化合物半導體材料)製得。晶圓之頂部側上之主動電路及金屬凸塊係根據工業文獻中大量記載之半導體及金屬製造方法製得。
切塊膠帶通常用於在切塊操作期間支撐晶圓。切塊膠帶可自多個來源購得且可呈載體上之熱敏性、壓敏性或UV敏感性黏著劑形式。載體通常係聚烯烴或聚醯亞胺之撓性基板。在分別施加熱、拉伸應力或UV時，黏性降低。通常，釋放襯墊覆蓋黏著層且可在即將使用切塊膠帶之前容易地移除。在DBG過程中，對晶圓之背側施加切塊膠帶且在晶圓頂部側上之電路之間切割切塊溝槽至滿足或符合可進行背側研磨之程度的深度。
在晶圓薄化過程期間，使用背面研磨膠帶保護並支撐金屬凸塊及晶圓之頂部表面。背面研磨膠帶可自多個來源購得且呈一種由載體上之熱敏性、壓敏性或UV敏感性黏著劑組成之形式。載體通常係聚烯烴或聚醯亞胺之撓性基板。在分別施加熱、拉伸應力或UV時，黏性降低。通常，釋放襯墊覆蓋黏著層且可在即將使用背面研磨膠帶之前容易地移除。可藉由機械研磨或蝕刻實施背面研磨操作。移除晶圓背側上之材料直至達到或超過切塊溝槽為止，此使晶粒單體化。
底部填充囊封劑通常係以膏糊或膜形式施加。藉由噴霧、旋塗、模板印刷或工業中所用之任何方法施加膏糊。呈膜形式之底部填充劑通常較佳，此乃因其較不髒亂且更易於以均勻厚度施加。已知適用作可呈膜形式之底部填充劑化學物質的黏著劑及囊封劑，如同製造膜本身之方法一樣。可調節底部填充劑材料之厚度以使可在層壓後完全或僅部分覆蓋金屬凸塊。在任一情形下，供應底部填充劑材料以使其完全填充半導體與期望基板之間之間隔。
在一個實施例中，將底部填充劑材料提供於載體上並用釋放襯墊加以保護。因此，呈一種型式之底部填充劑材料係以三層形式提供，其中順序為第一層係載體(例如撓性聚烯烴或聚醯亞胺膠帶)，第二層係底部填充劑材料，且第三層係釋放襯墊。在即將使用之前，移除釋放襯墊並通常在仍附接至載體時施加底部填充劑。在將底部填充劑施加至晶圓之後，移除載體。
參照圖進一步闡述本發明。圖1展示切塊一個表面上具有主動電路12及金屬凸塊13之陣列之矽晶圓11的先前技術方法。首先用底部填充劑材料14囊封主動電路及金屬凸塊。將背面研磨膠帶15層壓至底部填充劑14以支撐晶圓並保護底部填充劑，其後藉由研磨刀片16或由從業人員選擇之任何其他適當方法減少晶圓背側之厚度。
在背面研磨後，將切塊膠帶18施加至晶圓背側以在切塊期間及在進行切塊之後支撐晶圓並使晶粒保持在適當位置。自晶圓移除背面研磨膠帶15並使用切塊刀片19切割切 塊溝(亦稱作切塊線)，在主動電路附近之間隔中穿過底部填充劑並切入晶圓中，以將電路單體化成個別晶粒。元件17代表切塊線且最終代表在切塊及單體化後個別半導體之間之間隔。在背面研磨期間薄化晶圓時，其變得非常易碎且主動電路在切塊操作期間可因切割刀片之機械應力而受損。為對此進行補償，降低切割速度。對主動電路之損害及切割速度之減少使製造產量降低並使成本增加。
在底部填充劑囊封之後及在研磨之前進行切塊之本發明方法繪示於圖2中。提供具有主動電路12及金屬凸塊13之陣列之矽晶圓11；且主動電路及金屬凸塊經底部填充劑材料14囊封。晶圓安裝於切塊膠帶18上，其中晶圓背側接觸切塊膠帶。切塊刀片19在主動電路附近之間隔中切割穿過底部填充劑並切入晶圓，從而產生切塊線17。在單體化後，元件17代表個別半導體之間之間隔。將切塊線切割至晶圓中至晶圓之最終厚度期望之深度或超過該深度。將背面研磨膠帶15層壓至晶圓頂部側上之底部填充劑並自晶圓背側移除切塊膠帶18。隨後藉由(例如)用研磨刀片19研磨或由從業人員選擇之任何其他適當方法減少晶圓背側之厚度。取厚度減少至少至切塊線之深度，且可進一步取至期望之最終晶圓厚度。藉由自晶圓背側移除厚度至少至切塊線之深度，將晶圓單體化成個別晶粒。
11‧‧‧矽晶圓
12‧‧‧主動電路
13‧‧‧金屬凸塊
14‧‧‧底部填充劑材料
15‧‧‧背面研磨膠帶
16‧‧‧研磨刀片
17‧‧‧切塊線
18‧‧‧切塊膠帶
19‧‧‧切塊刀片
圖1係將具有預先施加之底部填充劑材料之晶圓單體化的先前技術方法的示意圖。
圖2係將具有預先施加之底部填充劑材料之晶圓單體化的本發明方法的示意圖。
11‧‧‧矽晶圓
12‧‧‧主動電路
13‧‧‧金屬凸塊
14‧‧‧底部填充劑材料
15‧‧‧背面研磨膠帶
16‧‧‧研磨刀片
17‧‧‧切塊線
18‧‧‧切塊膠帶
19‧‧‧切塊刀片

Claims (1)

  1. 一種將半導體晶圓單體化成個別半導體晶粒之方法，該半導體晶圓之頂部表面具有金屬預先連接凸塊且具有佈置於該等金屬預先連接凸塊上及附近之底部填充劑之塗層，該方法包含：(A)提供半導體晶圓，其頂部表面具有金屬預先連接凸塊之陣列及佈置於該等金屬預先連接凸塊上及附近之底部填充劑之塗層；(B)穿過該等金屬預先連接凸塊之間之該底部填充劑切塊且切入該半導體晶圓之該頂部表面中至最終期望晶圓厚度，從而產生切塊線；及(C)自該晶圓背側移除晶圓材料至少至該等切塊線之深度，藉此使所得晶粒自該晶圓單體化。
TW101126862A 2011-07-29 2012-07-25 於塗佈後研磨前之切塊 TW201314757A (zh)

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WO2013019499A2 (en) 2013-02-07
CN103999203A (zh) 2014-08-20
KR20140044879A (ko) 2014-04-15
KR101504461B1 (ko) 2015-03-24
US20140057411A1 (en) 2014-02-27
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EP2737522A2 (en) 2014-06-04

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