TWI502724B - 形成積體電路結構的方法與積體電路結構 - Google Patents

形成積體電路結構的方法與積體電路結構 Download PDF

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TWI502724B
TWI502724B TW099122431A TW99122431A TWI502724B TW I502724 B TWI502724 B TW I502724B TW 099122431 A TW099122431 A TW 099122431A TW 99122431 A TW99122431 A TW 99122431A TW I502724 B TWI502724 B TW I502724B
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wafer
integrated circuit
circuit structure
trenches
die
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TW201110310A (en
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Hsin Hui Lee
William Cheng
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Taiwan Semiconductor Mfg Co Ltd
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Description

形成積體電路結構的方法與積體電路結構
本發明大致關於半導體裝置的製造，且特別關於晶圓級晶片模壓封裝(wafer level chip molded packaging)的結構與方法。
於半導體工業中，為響應減少半導體封裝之厚度、增加晶片速度及高密度製造的目標，進行減少半導體晶圓厚度的努力。於堆疊之晶圓製造中，具有積體電路形成於其中之兩個或多個半導體晶圓互相連接。在相對於含有圖案形成化電路系統之表面的表面上，藉由所謂半導體晶圓之背面研磨來執行厚度減少。由於經薄化之晶圓傾向具有不足的強度且較易變形，例如彎曲及/或扭曲，所以在使用一切割製程將晶圓分成個別之晶片封裝體前，通常執行一封住步驟，於其中將晶圓之一表面封在一成形化合物(molding compound)(例如，熱固化環氧樹脂(thermocuring epoxy resin))中。之後將這些個別之晶片封裝體固定於一基板上，例如一印刷電路板(printed circuit board,PBC)。
然而，並無法進行一般堆疊晶圓製程而無其缺陷。有時，在晶圓遭受溫度循環測試(temperature cycle test)之處，例如成形化合物會變成自其所貼附之晶圓鬆開或脫層(delamination)。成形脫層(molding delamination)對於製造製程有害且易減低整體製程產率並會降低所生產之晶片封裝體的品質與可靠程度。此外，已發生自晶圓成形脫層之處，於隨後之切割製程與相關處理期間，晶圓之晶片的邊緣更易受到破裂、形成缺口及/或腐蝕性環境影響。由於這些理由及根據閱讀以下之詳細敘述會開始變得明顯的其他理由，需要一晶圓級晶片製造的改善方法，其避免一般晶圓結合製程的缺點。
本發明提供一種形成積體電路結構的方法，包括：提供一晶圓，其具有一晶片側與一非晶片側，該晶片側包括複數個半導體晶片；提供複數個晶粒，各個該晶粒結合至該複數個半導體晶片之一；形成一或多個溝槽於該晶圓之該晶片側上；將該晶圓之該晶片側與該複數個晶粒封住，且實質上以一保護材料填入該一或多個溝槽；以及切割該晶圓以將該晶圓分成個別的半導體封裝體。
本發明又提供一種形成積體電路結構的方法，包括：提供一晶圓，其具有一晶片側與一非晶片側，該晶片側包括複數個半導體晶片；提供複數個晶粒，各個該晶粒結合至該複數個半導體晶片之一；將一高能束聚焦於該晶圓之該晶片側上以形成一或多個溝槽；將該晶圓之該晶片側與該複數個晶粒封住，並以一保護材料填入該一或多個溝槽；烘烤該保護材料以固化該保護材料；以及切割該晶圓以將該晶圓分成個別的半導體封裝體。
本發明還提供一種積體電路結構，包括：一半導體晶片，其具有一晶粒側與一非晶粒側，該晶粒側具有一或多個溝槽形成於其中；至少一個晶粒，結合至該半導體晶片的該晶粒側；以及一保護材料封住該至少一晶粒且實質上填入該一或多個溝槽。
為了讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖示，作詳細說明如下：
第1圖為一積體電路結構10之一實施例於其製造階段期間的一剖面圖。晶粒20結合於晶圓22之上。晶粒20可包括記憶體晶片(memory chip)、射頻(radio frequency,RF)晶片、邏輯晶片(logic chip)或其他晶片。晶粒20各具有一正表面30與一背表面40。各個晶粒20包括半導體基板50，其中晶粒20的背表面40也為分別之半導體基板50的背表面。
晶圓22包括複數個半導體晶片70。晶圓22包括半導體晶圓，例如矽、砷化鎵、水晶晶圓(rock crystal wafer)、藍寶石(sapphire)、玻璃等。晶片70可包括記憶體晶片、射頻晶片、邏輯晶片或其他晶片。在本發明之一實施例中，各個晶粒20結合至晶片70之一。或者，一晶片70可具有大於一個晶粒20結合於其上。在一些實施例中，晶粒20與晶片70為面對面(face-to-face)結合，其中結合方法包括一般使用之方法，例如氧化物至氧化物(oxide-to-oxide)結合、氧化物至矽(oxide-to-silicon) 結合、銅至銅(copper-to-copper)結合、附著結合(adhesive bonding)等。在一實施例中，各個晶粒20藉由焊料凸塊(solder bump)35結合至複數個晶片之一。在一些實施例中，可使用底膠材料(underfill material)25以填入介於複數個晶粒20之一與複數個晶片70之一間的一缺口，底膠材料實質上封住焊料凸塊35。結合至一相同之晶片70的晶粒20可各具有相同或不同的電路設計或尺寸。
晶圓22可具有一正表面80與一背表面90，其中接合墊(未顯示)及/或其他內連線結構(未顯示)為接近正表面80，而背表面90為一半導體基板背表面。積體電路(未顯示)包括主動與被動裝置，例如電晶體、電阻器、電容器等，且形在於晶圓22的正表面80。在本發明一實施例中，半導體晶片70包括一或多個穿透矽通孔(through-silicon via,TSV)(未顯示)，其自正表面80往下延伸進入晶圓22，其中穿透矽通孔連接至一或多個晶粒20。
然後參見第2圖，於晶圓22之正表面80上形成一或多個溝(geoove)或溝槽(trench)60。溝槽60可藉由一般雷射切割(laser scribing)技術或其他適合裁切方法來形成，其中一高能束(high energy beam)，如雷射光束，可被使用來例如穿過或切除晶圓22之正表面80的一部份。溝槽60代表一體積，其藉由溝槽之底部的寬度乘以側壁的高度乘以於晶圓22之正表面80中所製成之溝槽的長度所定義。溝槽60之體積代表藉由一雷射切割機器或其他適合裁切工具自晶圓表面所移除之矽的量。
要被使用於一切割製程中之適合的雷射裝備可為任何那些市售可得之雷射。例如，可適合地使用具有能量等級介於1與2 watts之間的一連續Nd/YAG雷射。熟悉此技藝人士瞭解可適合地調整雷射的能量以僅移除所需之矽層的深度、寬度及/或長度。熟悉此技藝人士也瞭解深度應夠深以允許一之後要被沈積之成形化合物(later-to-be deposited molding compound)被形成於溝槽60中以可充分附著或固定至下方晶圓22以使在溫度循環測試(temperature cycle test)或切割步驟期間，例如成形化合物不會自晶圓變形或脫層(delaminate)。於相同意義下，在由於溝槽60形成而在於矽層中建立應力之處，深度應不那麼深。在本發明一實施例中，形成溝槽60至介於約100至約150,000之間的一深度。在另一實施例中，形成溝槽60至介於約1,000至約50,000之間的一深度。
如第2圖中所示，形成一或多個溝槽60於晶圓22之正表面上介於複數個晶粒20之任兩個之間。然後參見第3圖，將一成形化合物或保護材料100塗覆於晶圓22之正表面80上、於複數個晶粒20上，及實質上於溝槽60中。保護材料100係由一可固化材料，例如一聚合物材料、樹脂材料、聚亞醯胺、氧化矽、環氧樹脂、苯並環丁烯(Benzocyclobutene,BCB)、SILKTM (Dow Chemical)或其組合所形成。為了避免晶圓22或要被研磨之本體(body)在一研磨製程中扭曲，例如，在保護材料100固化後，保護材料100較佳具有充分地高剛度(stiffness)與撓曲剛性(flexural rigidity)。可於晶圓22上形成保護材料100至厚度大於晶粒20的高度以封住晶粒20。保護材料20之厚度並無特別限制，只要其可確保一後製程(later process)，例如晶圓22或要被研磨之本體之研磨，所需的厚度一致。然而，為了在基板之研磨後，獲得所需之厚度一致，保護材料100之厚度較佳為一致。
使用製程，如射出成形(injection molding)、壓縮成形(compression molding)、鋼板印刷(stencil printing)、旋塗(spin-on coating)或未來發展之成形製程(molding process)可將保護材料100提供至積體電路結構10。在保護材料100的塗覆之後與一後來的晶圓薄化或切割製程之前，執行一固化或烘烤步驟以固化保護材料100。在本發明一實施例中，於一加熱腔室中在自約100℃至約200℃的溫度下，以自約30分鐘至約8小時的時間，烘烤保護材料100。在固化保護材料100後，晶圓22的非晶片側可接受一進一步之薄化製程來研磨非晶片側以減少晶圓的厚度。
回到溝槽60形成的討論上，第6圖顯示根據本發明一實施例，一積體電路結構10的剖面圖，其中溝槽60形成於晶粒20之周圍(但在晶粒切割線區內)且實質上被以成形材料100填入。第5圖顯示相同之積體電路結構，但為一上視圖，其中成形材料100形成於溝槽60中。為了清楚說明，未顯示成形材料100形成於晶粒20、底膠材料25或晶圓22之部分之上。第5圖顯示根據發明一實施例，溝槽60為一環繞晶粒20之連續溝槽。然而，在一些實施例中，溝槽60可為一非連續溝槽，換句話說，溝槽60可包括一或多個獨立且分離之溝槽，其實質上連續沿著晶粒20的周圍。
第8圖顯示根據本發明一實施例，積體電路結構10的剖面圖，其中溝槽60形成在晶粒20的周圍但較接近晶粒20，且實質上被以成形化合物100填入。第7圖顯示積體電路結構的上視圖，其中顯示成形化合物100形成於溝槽60中。再者，為了清楚之目的，於第7圖中未顯示成形化合物100形成於晶粒20、底膠材料25或晶圓22之部分之上。第7圖顯示根據本發明一實施例，溝槽60為形成於晶粒20之周圍的一連續溝槽。然而，在一些實施例中，溝槽60可為一非連續溝槽，其意指，溝槽60可包括一些個別分離之溝槽，其實質上連續沿著晶粒20的周圍。在一些實施例中，溝槽60形成於晶圓22中實質上連續沿著晶圓之一或多個晶粒切割線。
雖然顯示於第5至8圖中之溝槽60具有矩形的形狀，然而可以瞭解的是，根據依照所實施之製造製程的設計選擇，溝槽60可包括任何形狀。例如，溝槽60可具有一圓形、卵形、矩形、三角形、正方形、五邊形、六邊形、七邊形、八邊形、星形、十字形或橢圓形的形狀。第10與9圖顯示根據一實施例，包括一矩形、圓形(各種尺寸)與十字形之形狀的溝槽。
然後參見第4圖，一般在晶圓已接受一晶圓等級測試程序後，接著將晶圓22倒置且固定至切割膠帶(dicing tape)110或一晶粒模(die frame)，其為之後以一般方式沿著切割線93被切割以將經封住的晶圓分成用於固定於一基板，例如印刷電路板(printed circuit board,PCB)上之個別的半導體封裝體。
第11圖顯示一形成積體電路結構之方法200的一實施例。經由提供一晶圓，其具有一晶片側與一非晶片側，晶片側包括複數個半導體晶片，方法200開始於步驟202。於步驟204，提供複數個晶粒，各個晶粒結合至複數個半導體晶片之一。於步驟206，一或多個溝槽形成於晶圓之晶片側上。於步驟208，將晶圓之晶片側與複數個晶粒以一保護材料封住，保護材料實質上填入一或多個溝槽。於步驟210，切割晶圓以將其分成用於固定於一基板(例如，印刷電路板)上之個別的半導體封裝體。
可將根據本發明實施例之形成晶圓級晶片模壓封裝(wafer level chip molded package)的方法實施於廣大範圍之封裝應用。由於具有成形化合物嵌入於下方晶圓中，增強了介於成形化合物與晶圓之間的附著。此避免了可起因於溫度循環測試的可能脫層，而在溫度循環測試中，例如熱膨脹係數(coefficient of thermal Expansion,CTE)變成一議題。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧積體電路結構
20‧‧‧晶粒
22‧‧‧晶圓
25‧‧‧底膠材料(underfill material)
30‧‧‧晶粒20之正表面
35‧‧‧焊料凸塊
40‧‧‧晶粒20之背表面
50‧‧‧半導體基板
60‧‧‧溝或溝槽
70‧‧‧晶片
80‧‧‧晶圓22之正表面
90‧‧‧晶圓22之背表面
93‧‧‧切割線
100‧‧‧成形化合物或保護材料
110‧‧‧切割膠帶(dicing tape)
200‧‧‧形成一積體電路結構之方法
202、204、206、208、210‧‧‧步驟
第1至10圖顯示一積體電路結構之一實施例於其各種製造階段期間的剖面圖。
第11圖顯示形成積體電路結構之方法之一實施例的一流程圖。
10．．．積體電路結構
20．．．晶粒
22．．．晶圓
25．．．底膠材料(underfill material)
30．．．晶粒20之正表面
35．．．焊料凸塊
40．．．晶粒20之背表面
50．．．半導體基板
60．．．溝或溝槽
70．．．晶片
80．．．晶圓22之正表面
90．．．晶圓22之背表面
100．．．成形化合物或保護材料

Claims (14)

  1. 一種形成積體電路結構的方法，包括：接收一晶圓，其具有一晶片側與一非晶片側，該晶片側包括複數個半導體晶片；提供複數個晶粒，各個該晶粒自該晶片側藉由焊料凸塊結合至該複數個半導體晶片之一；形成一或多個溝槽於該晶圓該晶片側之該晶圓內；在各個該晶粒結合至該複數個半導體晶片之一之後，將該晶圓之該晶片側與該複數個晶粒封住，且以一保護材料填入該一或多個溝槽；以及切割該晶圓以將該晶圓分成個別的半導體封裝體。
  2. 如申請專利範圍第1項所述之形成積體電路結構的方法，其中形成一底膠材料以填入介於該複數個晶粒之一與該複數個晶片之一間的一缺口，該底膠材料封住該焊料凸塊。
  3. 如申請專利範圍第1項所述之形成積體電路結構的方法，其中形成一或多個溝槽於該晶圓該晶片側之該晶圓內介於該複數個晶粒之任兩個之間。
  4. 如申請專利範圍第3項所述之形成積體電路結構的方法，其中該一或多個溝槽係藉由一高能束(high energy beam)形成。
  5. 如申請專利範圍第1項所述之形成積體電路結構的方法，其中該一或多個溝槽係使用一雷射切割技術形成。
  6. 如申請專利範圍第1項所述之形成積體電路結構 的方法，其中該一或多個溝槽連續沿著該晶粒之一的一周圍被形成於該晶圓中。
  7. 如申請專利範圍第6項所述之形成積體電路結構的方法，其中該一或多個溝槽被形成於該晶圓之一晶粒切割線區內。
  8. 如申請專利範圍第1項所述之形成積體電路結構的方法，其中該一或多個溝槽連續沿著該晶粒之一晶粒切割線被形成於該晶圓中。
  9. 如申請專利範圍第1項所述之形成積體電路結構的方法，更包括在該切割該晶圓的步驟前烘烤該保護材料以固化該保護材料。
  10. 一種形成積體電路結構的方法，包括：接收一晶圓，其具有一晶片側與一非晶片側，該晶片側包括複數個半導體晶片；提供複數個晶粒，各個該晶粒自該晶片側藉由焊料凸塊結合至該複數個半導體晶片之一；將一高能束聚焦於該晶圓之該晶片側上以形成一或多個溝槽；在各個該晶粒結合至該複數個半導體晶片之一之後，將該晶圓之該晶片側與該複數個晶粒封住，並以一保護材料填入該一或多個溝槽；烘烤該保護材料以固化該保護材料；以及切割該晶圓以將該晶圓分成個別的半導體封裝體。
  11. 一種積體電路結構，包括：一半導體晶片，其具有一晶粒側與一非晶粒側，該 晶粒側具有一或多個溝槽形成於其中；至少一個晶粒，藉由焊料凸塊結合至該半導體晶片的該晶粒側；以及一保護材料封住該至少一晶粒且填入該一或多個溝槽。
  12. 如申請專利範圍第11項所述之積體電路結構，其中該一或多個溝槽被形成至介於約100Å至約150,000Å之間的一深度。
  13. 如申請專利範圍第11項所述之積體電路結構，其中該一或多個溝槽連續沿著該晶粒的一周圍被形成於該半導體晶片中。
  14. 如申請專利範圍第13項所述之積體電路結構，其中該一或多個溝槽被形成於該半導體晶片之一切割線區內。
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US8647963B2 (en) 2014-02-11

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