TWI478282B - 半導體元件的形成方法 - Google Patents

半導體元件的形成方法 Download PDF

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TWI478282B
TWI478282B TW098118502A TW98118502A TWI478282B TW I478282 B TWI478282 B TW I478282B TW 098118502 A TW098118502 A TW 098118502A TW 98118502 A TW98118502 A TW 98118502A TW I478282 B TWI478282 B TW I478282B
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wafer
forming
semiconductor
semiconductor device
thinned
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TW201023298A (en
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Ku Feng Yang
Weng Jin Wu
Wen Chih Chiou
Chen Hua Yu
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Taiwan Semiconductor Mfg Co Ltd
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Description

半導體元件的形成方法
本發明實施例係有關於連結半導體晶粒之系統及方法，且特別是有關於使用穿矽導通孔(through-silicon via)連結半導體晶粒之系統及方法。
通常，可使用穿矽導通孔(through-silicon via，TSVs)來連結兩半導體晶粒(semiconductor dies)，一般需要自其上形成有半導體晶粒之晶圓的背面以某些型式移除材料。在一種形成TSVs的方法中，晶圓之具有主動元件的一側被部分移除以形成一或多個孔洞，孔洞至少部分穿進矽晶圓。在於孔洞中填入導電材料後，使用例如是機械研磨(mechanical grinding)或蝕刻之製程自晶圓之背面移除晶圓以露出導電材料，形成了自晶圓之背面穿越至正面之接點(contact)。
然而，因為例如是低介電常數(low-k)介電材料或超低介電常數(extremely low-k)介電材料正開始變得更加廣為使用，這些形成TSVs之方法面臨問題。這些低介電常數材料非常的易脆，且難以承受來自各種製程步驟之應力。當晶圓以機械研磨或蝕刻薄化時，此問題變得更為放大，因為介電材料可能變得無法承受進一步的處理及製程，可能會造成損壞，更甚者使元件完全破壞。
因此，業界亟需形成TSVs的新方法，其可減少或避免薄化晶圓在隨後的處理或製程期間受到傷害。
本發明一實施例提供一種半導體元件的形成方法，包括提供晶圓，具有第一側面及相反之第二側面，晶圓包括至少一導電插塞，穿過晶圓之至少一部分；保護晶圓之位於第二側面上之邊緣；將晶圓之第二側面薄化以露出至少一導電插塞而不將第二側面之邊緣薄化；以及將晶圓之薄化後部分與未薄化之邊緣分離。
本發明另一實施例提供一種半導體元件的形成方法，包括提供基底，包括第一側面及相反之第二側面，晶圓之第二側面包括第一部分及圍繞第一部分之第二部分；於晶圓之第一部分中形成至少一導電插塞；保護晶圓之第二部分；將晶圓之第一部分薄化以露出至少一導電插塞而不將晶圓之第二部分薄化，薄化步驟形成晶圓之薄化第一部分及無薄化第二部分；以及將晶圓之薄化第一部分自晶圓之無薄化第二部分分離。
本發明又一實施例提供一種半導體元件的形成方法，包括提供半導體晶圓，具有內部晶粒區、圍繞內部晶粒區之切割線、及緊鄰切割線之外部區，半導體晶圓包括第一側面及相反之第二側面；自第一側面形成部分穿過半導體晶圓之複數個導電插塞；以及將半導體晶圓之第二側面上之內部晶粒區薄化以露出導電插塞而不將外部區薄化。
本發明將於數個實施例中描述，主要是針對在半導體晶圓中使用穿矽導通孔(TSVs)來堆疊晶粒。然而，本發明實施例亦可應用在其他薄晶圓的處理製程中。
請參照第1圖，其顯示晶圓100之剖面圖，其具有正面115及背面117。晶圓100較佳具有複數個第一半導體晶粒102(以虛線示出其輪廓)，其形成在晶圓100之晶粒區119中、鄰接晶圓100之晶粒區119之切割線(scribe line)120、以及緊接晶圓100之切割線120之邊緣(edge)121。然而，為了清楚敘述本發明實施例，第1、2A、3A、及4-5圖中，僅顯示單一的第一半導體晶粒102。可了解的是，雖然僅顯示單一的第一半導體晶粒102，在本發明實施例之精神內，任何數目之第一半導體晶粒102可形成在晶圓100上。
第一半導體晶粒102較佳包括基底101、主動元件104、金屬化層(metallization layers)103、接墊(contact pads)105、下凸塊金屬層(UBM)107、接觸凸塊(contact bump)108、以及穿矽導通孔(TSVs)109，或亦可稱為導電插塞(conductive plug)。基底101可包括塊材矽(bulk silicon)、摻雜或無摻雜基底、或絕緣層上覆矽(SOI)之主動層基底。一般，基底包括半導體材料層，例如矽、鍺、矽鍺、SOI、絕緣層上覆矽鍺、或前述之組合。亦可使用其他基底，包括多層基底(multi-layered substrate)、梯度基底(gradient substrates)、或晶向混合基底(hybrid orientation substrates)。
顯示於第1圖中之主動元件104為一單一電晶體。然而，此技藝人士當可明瞭，可使用各種被動元件(例如，電容、電阻、電感、及其相似物)以產生所需之結構及設計所需之功能。可使用任何適合方法於基底101中或表面上形成主動元件104。
穿矽導通孔109之形成較佳藉著塗佈及顯影適合的光阻(未顯示)及接著蝕刻基底101以產生TSV開口(將在後續製程中被填充)。在此階段形成之穿矽導通孔109之開口較佳延伸進入基底101，並至少超過形成於基底101中或上之主動元件104，且所延伸之深度較佳至少大於所將完成第一半導體元件102之高度。因此，當延伸深度取決於第一半導體晶粒102之整體設計，延伸在基底101之表面下的深度較佳介於約1μm至約700μm之間，較佳深度為約50μm。所形成穿矽導通孔109之開口較佳具有介於約1μm至約100μm之直徑，較佳直徑為約6μm。
一旦形成了穿矽導通孔109之開口，較佳以緩衝層111及導電材料113填充穿矽導通孔109之開口。緩衝層111較佳包括導電材料，例如氮化鈦，雖然亦可使用其他材料，例如氮化鉭、鈦、介電材料、或其相似物。緩衝層111之形成較佳使用CVD製程，例如PECVD。然而，亦可使用其他製程，例如濺鍍或MOCVD。較佳形成緩衝層111以控制穿矽導通孔109之開口下的輪廓形狀。
導電材料113較佳包括銅，雖然亦可使用其他適合材料，例如鋁、合金、摻雜多晶矽、前述之組合、或其相似物。導電材料113之形成較佳藉著沉積晶種層及接著電鍍銅至晶種層上以填充並滿出矽導通孔109之開口。一旦矽導通孔109之開口被填滿，較佳透過研磨製程將矽導通孔109之開口外多餘的緩衝層111及導電材料113移除，例如透過化學機械研磨(CMP)法，雖然亦可使用任何其他適合的移除製程。
金屬化層103較佳形成於基底101及主動元件104上，且設計為連接各種主動元件104以形成功能性電路(functional circuitry)。金屬化層103較佳由數層介電層及導電材料層交錯堆疊而成，且可以任何適合製程形成，例如沉積、鑲嵌(damascene)、雙鑲嵌(dual damascene)等。較佳有至少4層的金屬化層，其由至少一層間介電層(ILD)而與基底101隔開，然金屬化層103之準確數目係取決於第一半導體晶粒102之設計。
較佳形成接墊105以將金屬化層103連接至外部的輸入/輸出連接(exterior input/output connections)，例如凸塊下金屬層107。接墊105較佳由鋁形成，雖然亦可使用其他材料，例如鋁合金、鋁銅(aluminum copper)、銅、前述之組合、或其相似物。再者，可以各種方法形成接墊105，取決於所選用之材質。例如，若使用鋁，接墊105之形成較佳藉著於金屬化層103上形成鋁層，並接著使用適合的技術(如微影及化學蝕刻)將鋁層圖案化為接墊105。或者，若使用銅，接墊105之形成較佳先形成介電層106、形成進入介電層106之開口、沉積緩衝層及晶種層(未顯示)、於開口中填滿銅、及接著使用研磨製程(例如CMP)移除開口外多餘的銅以形成接墊105。任何適合形成接墊105之方法皆可採用，且這些製程皆在本發明實施例之精神之內。
凸塊下金屬層107較佳逐層順應性地形成在接墊上。每一材料層之形成較佳以CVD製程進行，例如採用PECVD，雖然亦可使用其他製程，例如濺鍍、蒸鍍、或電鍍等製程，取決於所需之材質。凸塊下金屬層107中之每一材料層較佳具有約10μm至約100μm之間的厚度，較佳厚度為約45μm。一旦形成了所需之材料層，透過適合的微影遮罩及蝕刻製程以將部分不需要的材料層移除，並留下圖案化之凸塊下金屬層107。
接觸凸塊108之材質較佳例如包括錫或其他適合材料，如銀或銅。在一實施中，接觸凸塊108為銲錫凸塊(tin solder bump)，接觸凸塊108之形成可藉著先透過任何適合的製程，例如蒸鍍、電鍍、印刷(printing)、焊料轉移(solder transfer)、植球(ball placement)等以形成錫層，其較佳厚度為約100μm。一旦於結構上形成了錫層，較佳進行迴銲(reflow)以將焊料塑形為所需的凸塊形狀。
晶圓之切割線120較佳圍繞複數個半導體晶粒102。切割線120較佳藉著不放置功能性結構(例如主動元件104)至欲用作切割線120之區域而形成。其他結構例如測試接墊(test pads)或用以平坦化之虛置金屬可放置在切割線120中，一旦半導體晶粒102自晶圓100切下，這些結構對於半導體晶粒102執行功能不是必需的。切割線120較佳具有約20μm至約180μm之寬度，較佳寬度為約80μm。
然而，此技藝人士可明瞭，以上之敘述僅為舉例說明，不應用以將本發明限制至此特定實施例。第一半導體晶粒102之啟始結構可有數種變化。例如，亦可使用一結構，其穿矽導通孔109除了延伸穿過基底101外，還進一步穿過一或數層金屬層化層103。任何這些實施例及任何其他適合的實施例皆完全在本發明之精神之內。
第2A圖顯示晶圓100之背面117的薄化。在此實施例中，較佳將晶圓100放置進夾盤(chuck)201之底部部分203，其中晶圓100之正面115朝下。夾盤201之頂部部分205較佳連接至夾盤201之底部部分203，其中夾盤201之頂部部分205覆蓋且保護晶圓100之邊緣121，其中邊緣121緊鄰切割線120，而露出切割線120及晶粒區119。較佳使用一或多個密封結構(seals)系列以確保夾盤201與晶圓100之間的密封，並確保無污染物可到達晶圓100之邊緣121及背面117。
然而，此技藝人士當可明瞭夾盤201僅為用以保護晶圓100之正面115且保護晶圓100之背面117中較佳不被移除之部分的單一適合方法舉例。亦可使用任何其他適合方法，例如形成一或多個光阻層或使用黏著膠帶保護需保護的區域。所有這些方法皆完全在本發明實施例之精神中。
一旦晶圓100之背面117的邊緣121被保護，較佳將晶圓100之未被保護的晶粒區119薄化，以便露出穿矽導通孔109，並將夾盤201之圖案轉移至晶圓100之邊緣121上。此薄化製程較佳以兩段濕式蝕刻進行，即一塊材移除蝕刻(bulk removal etch)及一完成蝕刻(finishing etch)。塊材移除蝕刻較佳使用硝酸(HNO3 )、硫酸(H2 SO4 )、氫氟酸(HF)、及磷酸(H3 PO4 )之混合物(即商用Spin-Etch D)以將晶圓100之塊材移除，使降至穿矽導通孔109。若晶圓具有700μm之厚度，薄化製程較佳移除約600μm至約670μm之間，較佳的移除厚度為約650μm。
一旦進行了塊材移除，較佳對晶圓100進行過蝕刻(overetch)以將部分的緩衝層111移除，並使穿矽導通孔109延伸凸出餘留的晶圓100。過蝕刻所使用之蝕刻劑較佳包括例如氫氧化四甲基銨(teramethylammonium hydroixde，TMAH)，其於晶圓之材質(例如矽)與穿矽導通孔109之材質(例如銅)之間具有非常高的蝕刻選擇性。過蝕刻較佳移除晶圓之材質以使穿矽導通孔109延伸凸出晶圓100約10μm至約0.5μm之間，較佳的凸出距離為約1μm。
第2B圖顯示晶圓100之背面117被薄化且夾盤201被移除之後的晶圓100背面117平面圖。如圖所示，夾盤201較佳形成一邊緣121，邊緣121盡可能地自較外圍之邊緣延伸而不妨礙最外圍之切割線120或晶粒區119中之複數個半導體晶粒102(以虛線表示)。因此，邊緣121之內邊界(inner boundary)較佳順應(conform to)晶粒區119之形狀。
第3A圖顯示將第二半導體晶粒300接合至第一半導體晶粒102。第二半導體晶粒300較佳包含類似於晶圓100之結構，例如第二基底301、第二系列之主動元件303、第二系列之金屬化層305、及第二系列之接觸凸塊307，其位於第二半導體晶粒300之第一側上，且這些結構較佳相似於如上所述第1圖所示之結構。然而，第二半導體晶粒300不限於此實施例所述，亦可使用任何欲連結至第一半導體晶粒102之適合元件。
第二半導體晶粒300較佳放置在由晶圓100之薄化後背面117與邊緣121所形成之凹陷(cavity)中。此外，第二半導體晶粒300與晶圓100較佳彼此對準，使第二接墊307與穿矽導通孔109對齊。一旦對齊，較佳接著將第二接墊307與穿矽導通孔109接合在一起，可藉著使第二接墊307與穿矽導通孔109接觸，並進行迴焊製程使第二接墊307之材質經迴焊而與穿矽導通孔109接合。然而，亦可使用任何適合的接合方法，例如銅-銅接合(copper-copper bonding)以將第二半導體晶粒300接合至第一半導體晶粒102。
較佳將底膠材料(underfill material)309注入或形成於第一半導體晶粒102與第二半導體晶粒300之間的空間中。底膠材料309可例如包括液態環氧物(liquid epoxy)，其可分配(dispensed)在第一半導體晶粒102與第二半導體晶粒300之間的空間中，並接著被硬化(cured to harden)。底膠材料309用以避免裂縫(crack)形成在接觸凸塊307中，其中裂縫通常由熱應力造成。
或者，可於第一半導體晶粒102與第二半導體晶粒300之間形成可變形凝膠(deformable gel)或矽橡膠(silicon rubber)以有助於避免接觸凸塊307中產生裂縫。此凝膠或矽橡膠之形成可以於第一半導體晶粒102與第二半導體晶粒300之間注入(injecting)或者是放置(placing)凝膠或矽橡膠。可變形凝膠或矽橡膠可於後續製程期間提供更佳的應力緩衝(stress relief)。
第3B圖顯示貼合第二半導體晶粒300後之晶圓100背面117的平面圖。如所示，在形成於晶圓100上之複數個第一半導體晶粒102其中之一單一第一半導體晶粒102中，較佳貼合有多重第二半導體晶粒300。再者，晶圓100之邊緣121較佳自晶圓100之較外圍邊緣盡可能地向晶粒區119方向延伸，因而較佳順應於晶粒區119之形狀。
第4圖顯示選擇性增加填充材料(filler material)401以進一步保護所接合之第一半導體晶粒102與第二半導體晶粒300。較佳放置填充材料401使填充於邊緣121與第二半導體晶粒300之間，並較佳覆蓋第二半導體晶粒300。填充材料401較佳包括模封化合物(molding compound)，然亦可為環氧物(epoxy)、聚亞醯胺(polyimide)、或其相似物，且較佳在使用熱硬化製程(thermal cure process)硬化之前注入或放入。然而，亦可使用任何其他可用以保護第一半導體晶粒102及第二半導體晶粒300之材料或製程。
第5圖顯示一旦第二半導體晶粒300已接合至第一半導體晶粒102且已選擇性放置填充材料401(或不放置填充材料401)，較佳將個別接合之第一半導體晶粒102自晶圓100切下。切割(singulation)製程之進行較佳使用鋸片(saw blade)沿著個別第一半導體晶粒102之間的區域切開晶圓100，因而將每一個別第一半導體晶粒102自晶圓100分離。此外，切割製程自晶圓100之邊緣121分離每一個別第一半導體晶粒102，因此切割後所留下之第一半導體晶粒102不具有晶圓100之邊緣121。
藉著留下厚度大於薄化晶圓100之剩餘部分之邊緣121，晶圓100可較佳地承受來自進一步製程、處理、及運送所造成的應力。再者，藉著將邊緣121盡可能延伸至晶粒區119，晶圓100的更多部分維持較厚，因而更進一步增進晶圓承受應力的能力。因此，形成於晶圓100上之第一半導體晶粒102僅有少部分的損壞，造成整體良率的提升。
雖然本發明實施例及其優點已詳細敘述如上，應了解的是各種改變、置換、或修飾皆可在不脫離所申請專利範圍所界定之發明的精神下實施。例如，保護邊緣免於被移除之各種不同方法皆完全在本發明實施例之精神之內。又例如，用作底膠及填充材料之材質在本發明實施例之精神之內可有很大的變異。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．晶圓
101、301．．．基底
102、300．．．晶粒
103、305．．．金屬化層
104、303．．．主動元件
105、307．．．接墊
106．．．介電層
107．．．下凸塊金屬層
108、307．．．接觸凸塊
109．．．穿矽導通孔
115．．．正面
111．．．緩衝層
113．．．導電材料
117．．．背面
119．．．晶粒區
120．．．切割線
121．．．邊緣
201．．．夾盤
203．．．底部部分
205．．．頂部部分
309．．．底膠材料
401．．．填充材料
第1圖顯示本發明一實施例中之晶圓，其中形成有穿過部分晶圓之穿矽導通孔。
第2A-2B圖分別顯示依本發明一實施例薄化晶圓之一部分的剖面圖及平面圖。
第3A-3B圖分別顯示依本發明一實施例將第二晶粒接合至晶圓的剖面圖及平面圖。
第4圖顯示依本發明一實施例將填充材料放置於第二晶粒上。
第5圖顯示依本發明一實施例將已接合之第一晶粒與第二晶粒自晶圓之邊緣分離。
100．．．晶圓
101．．．基底
102．．．晶粒
103．．．金屬化層
104．．．主動元件
105．．．接墊
106．．．介電層
107．．．下凸塊金屬層
108．．．接觸凸塊
109．．．穿矽導通孔
115．．．正面
111．．．緩衝層
113．．．導電材料
117．．．背面
119．．．晶粒區
120．．．切割線
121．．．邊緣
201．．．夾盤
203．．．底部部分
205．．．頂部部分

Claims (21)

  1. 一種半導體元件的形成方法，包括：提供一晶圓，具有一第一側面及相反之一第二側面，該晶圓包括至少一導電插塞，穿過該晶圓之至少一部分；以一夾盤覆蓋該晶圓之位於該第二側面上之一邊緣，其中由該夾盤所覆蓋之該邊緣的一內邊界順應該晶圓之晶粒區的外圍輪廓；將該晶圓之該第二側面薄化以露出該至少一導電插塞而不將該第二側面之邊緣薄化；以及將該晶圓之薄化後部分與未薄化之該邊緣分離。
  2. 如申請專利範圍第1項所述之半導體元件的形成方法，其中該邊緣之該內邊界圍繞出一十二邊形。
  3. 如申請專利範圍第1項所述之半導體元件的形成方法，更包括將一半導體晶粒接合至該晶圓之薄化後部分。
  4. 如申請專利範圍第3項所述之半導體元件的形成方法，更包括將一底膠材料放置於該半導體晶粒與該晶圓之薄化後部分之間。
  5. 如申請專利範圍第3項所述之半導體元件的形成方法，其中將該半導體晶粒接合至該晶圓之薄化後部分的步驟包括將該半導體晶粒放置進入由該晶圓之該邊緣與該晶圓之薄化後部分所形成之一凹陷中。
  6. 如申請專利範圍第5項所述之半導體元件的形成方法，更包括以一填充材料封裝該半導體晶粒。
  7. 如申請專利範圍第1項所述之半導體元件的形成方法，其中以一夾盤覆蓋該晶圓之該邊緣的步驟包括將該晶圓放置入一夾盤。
  8. 一種半導體元件的形成方法，包括：提供一晶圓，包括一第一側面及相反之一第二側面及一側壁，該晶圓之該第二側面包括一第一部分及圍繞該第一部分之一第二部分；於該晶圓之該第一部分中形成至少一導電插塞；於該晶圓之該第二部分及該側壁上設置一夾盤，其中該第二部分之一內邊界順應該晶圓之一區域的外圍輪廓，該區域包括複數個半導體晶粒；將該晶圓之該第一部分薄化以露出該至少一導電插塞而不將該晶圓之該第二部分薄化，該薄化步驟形成該晶圓之一薄化第一部分及一無薄化第二部分；以及將該晶圓之該薄化第一部分自該晶圓之該無薄化第二部分分離。
  9. 如申請專利範圍第8項所述之半導體元件的形成方法，更包括將一半導體晶粒接合至該晶圓之該薄化第一部分。
  10. 如申請專利範圍第9項所述之半導體元件的形成方法，更包括將一底膠材料放置於該半導體晶粒與該晶圓之該薄化第一部分之間。
  11. 如申請專利範圍第9項所述之半導體元件的形成方法，其中將該半導體晶粒接合至該晶圓之該薄化第一部分的步驟包括將該半導體晶粒放置進入由該晶圓之該 無薄化第二部分與該晶圓之該薄化第一部分所形成之一凹陷中。
  12. 如申請專利範圍第9項所述之半導體元件的形成方法，更包括將一填充材料放置於該半導體晶粒與該晶圓之該無薄化第二部分之間。
  13. 如申請專利範圍第8項所述之半導體元件的形成方法，其中該晶圓之該第一部分的薄化步驟包括一濕式蝕刻。
  14. 如申請專利範圍第8項所述之半導體元件的形成方法，其中該晶圓之該無薄化第二部分之該內邊界圍繞出一十二邊形。
  15. 一種半導體元件的形成方法，包括：提供一半導體晶圓，具有一內部晶粒區、圍繞該內部晶粒區之一切割線、及緊鄰該切割線之一外部區，該半導體晶圓包括一第一側面及相反之一第二側面；自該第一側面形成部分穿過該半導體晶圓之複數個導電插塞；於該半導體晶圓之該外部區之一較低表面及相反之一較高表面上覆蓋一夾盤，其中由該夾盤所覆蓋之該外部區的一內邊界順應該內部晶粒區之外圍輪廓；以及將該半導體晶圓之該第二側面上之該內部晶粒區薄化以露出該些導電插塞而不將該外部區薄化。
  16. 如申請專利範圍第15項所述之半導體元件的形成方法，更包括將一半導體晶粒接合至該晶圓之該內部晶粒區。
  17. 如申請專利範圍第16項所述之半導體元件的形成方法，更包括將一底膠材料放置於該半導體晶粒與該晶圓之該內部晶粒區之間。
  18. 如申請專利範圍第16項所述之半導體元件的形成方法，其中該半導體晶粒係放置於由該內部晶粒區與該外部區所形成之一凹陷中。
  19. 如申請專利範圍第16項所述之半導體元件的形成方法，更包括以一填充材料覆蓋該半導體晶粒。
  20. 如申請專利範圍第16項所述之半導體元件的形成方法，更包括將該內部晶粒區自該外部區分離。
  21. 如申請專利範圍第16項所述之半導體元件的形成方法，其中該外部區的該內邊界圍繞出一十二邊形。
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