CN101964311A - 形成集成电路结构的方法与集成电路结构 - Google Patents

形成集成电路结构的方法与集成电路结构 Download PDF

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CN101964311A
CN101964311A CN2010102263304A CN201010226330A CN101964311A CN 101964311 A CN101964311 A CN 101964311A CN 2010102263304 A CN2010102263304 A CN 2010102263304A CN 201010226330 A CN201010226330 A CN 201010226330A CN 101964311 A CN101964311 A CN 101964311A
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integrated circuit
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CN101964311B (zh
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李新辉
郑荣伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种形成集成电路结构的方法与集成电路结构，该形成集成电路结构的方法提供一晶片，其具有一芯片侧与一非芯片侧，该芯片侧包括多个半导体芯片。提供多个裸片，各个所述裸片结合至所述多个半导体芯片之一。形成一或多个沟槽于该晶片的该芯片侧上。将该晶片的该芯片侧与所述多个裸片以一保护材料封住，该保护材料实质上填入所述一或多个沟槽。切割该晶片以将其分成各自的半导体封装体。本发明避免了可起因于温度循环测试的可能脱层。

Description

形成集成电路结构的方法与集成电路结构
技术领域
本发明涉及半导体装置的制造，尤其涉及晶片级芯片模压封装(waferlevel chip molded packaging)的结构与方法。
背景技术
于半导体工业中，为响应减少半导体封装的厚度、增加芯片速度及高密度制造的目标，进行减少半导体晶片厚度的努力。于堆叠的晶片制造中，具有集成电路形成于其中的两个或多个半导体晶片互相连接。在相对于含有图案形成化电路系统的表面的表面上，借由所谓半导体晶片的背面研磨来执行厚度减少。由于经薄化的晶片倾向具有不足的强度且较易变形，例如弯曲及/或扭曲，所以在使用一切割工艺将晶片分成各自的芯片封装体前，通常执行一封住步骤，于其中将晶片的一表面封在一成形化合物(molding compound)(例如，热固化环氧树脂(thermocuring epoxy resin))中。之后将这些各自的芯片封装体固定于一基板上，例如一印刷电路板(printed circuit board，PBC)。
然而，并无法进行一般堆叠晶片工艺而无其缺陷。有时，在晶片遭受温度循环测试(temperature cycle test)之处，例如成形化合物会变成自其所贴附的晶片松开或脱层(delamination)。成形脱层(molding delamination)对于制造工艺有害且易减低整体工艺产率并会降低所生产的芯片封装体的品质与可靠程度。此外，已发生自晶片成形脱层之处，于随后的切割工艺与相关处理期间，晶片的芯片的边缘更易受到破裂、形成缺口及/或腐蚀性环境影响。由于这些理由及根据阅读以下的详细叙述会开始变得明显的其他理由，需要一晶片级芯片制造的改善方法，其避免一般晶片结合工艺的缺点。
发明内容
为了解决现有技术的问题，本发明提供一种形成集成电路结构的方法，包括：提供一晶片，其具有一芯片侧与一非芯片侧，该芯片侧包括多个半导体芯片；提供多个裸片，各个所述裸片结合至所述多个半导体芯片之一；形成一或多个沟槽于该晶片的该芯片侧上；将该晶片的该芯片侧与所述多个裸片封住，且实质上以一保护材料填入所述一或多个沟槽；以及切割该晶片以将该晶片分成各自的半导体封装体。
本发明又提供一种形成集成电路结构的方法，包括：提供一晶片，其具有一芯片侧与一非芯片侧，该芯片侧包括多个半导体芯片；提供多个裸片，各个所述裸片结合至所述多个半导体芯片之一；将一高能束聚焦于该晶片的该芯片侧上以形成一或多个沟槽；将该晶片的该芯片侧与所述多个裸片封住，并以一保护材料填入所述一或多个沟槽；烘烤该保护材料以固化该保护材料；以及切割该晶片以将该晶片分成各自的半导体封装体。
本发明还提供一种集成电路结构，包括：一半导体芯片，其具有一裸片侧与一非粒片侧，该裸片侧具有一或多个沟槽形成于其中；至少一个裸片，结合至该半导体芯片的该裸片侧；以及一保护材料封住该至少一裸片且实质上填入所述一或多个沟槽。
本发明避免了可起因于温度循环测试的可能脱层。
为了让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举优选实施例，并配合所附附图，作详细说明如下：
附图说明
图1至图10显示一集成电路结构的一实施例于其各种制造阶段期间的剖面图。
图11显示形成集成电路结构的方法的一实施例的一流程图。
其中，附图标记说明如下：
10～集成电路结构
20～裸片
22～晶片
25～底胶材料(underfill material)
30～裸片20的正表面
35～焊料凸块
40～裸片20的背表面
50～半导体基板
60～沟或沟槽
70～芯片
80～晶片22的正表面
90～晶片22的背表面
93～切割线
100～成形化合物或保护材料
110～切割胶带(dicing tape)
200～形成一集成电路结构的方法
202、204、206、208、210～步骤
具体实施方式
图1为一集成电路结构10的一实施例于其制造阶段期间的一剖面图。裸片20结合于晶片22之上。裸片20可包括存储芯片(memory chip)、射频(radio frequency，RF)芯片、逻辑芯片(logic chip)或其他芯片。裸片20各具有一正表面30与一背表面40。各个裸片20包括半导体基板50，其中裸片20的背表面40也为分别的半导体基板50的背表面。
晶片22包括多个半导体芯片70。晶片22包括半导体晶片，例如硅、砷化镓、水晶晶片(rock crystal wafer)、蓝宝石(sapphire)、玻璃等。芯片70可包括存储芯片、射频芯片、逻辑芯片或其他芯片。在本发明的一实施例中，各个裸片20结合至芯片70之一。或者，一芯片70可具有大于一个裸片20结合于其上。在一些实施例中，裸片20与芯片70为面对面(face-to-face)结合，其中结合方法包括一般使用的方法，例如氧化物至氧化物(oxide-to-oxide)结合、氧化物至硅(oxide-to-silicon)结合、铜至铜(copper-to-copper)结合、附着结合(adhesive bonding)等。在一实施例中，各个裸片20借由焊料凸块(solderbump)35结合至多个芯片之一。在一些实施例中，可使用底胶材料(underfillmaterial)25以填入介于多个裸片20之一与多个芯片70之一间的一缺口，底胶材料实质上封住焊料凸块35。结合至一相同的芯片70的裸片20可各具有相同或不同的电路设计或尺寸。
晶片22可具有一正表面80与一背表面90，其中接合垫(未显示)及/或其他内连线结构(未显示)为接近正表面80，而背表面90为一半导体基板背表面。集成电路(未显示)包括有源与无源装置，例如晶体管、电阻器、电容器等，且形在于晶片22的正表面80。在本发明一实施例中，半导体芯片70包括一或多个穿透硅通孔(through-silicon via，TSV)(未显示)，其自正表面80往下延伸进入晶片22，其中穿透硅通孔连接至一或多个裸片20。
然后参见图2，于晶片22的正表面80上形成一或多个沟(geoove)或沟槽(trench)60。沟槽60可借由一般激光切割(laser scribing)技术或其他适合裁切方法来形成，其中一高能束(high energy beam)，如激光光束，可被使用来例如穿过或切除晶片22的正表面80的一部分。沟槽60代表一体积，其借由沟槽的底部的宽度乘以侧壁的高度乘以于晶片22的正表面80中所制成的沟槽的长度所定义。沟槽60的体积代表借由一激光切割机器或其他适合裁切工具自晶片表面所移除的硅的量。
要被使用于一切割工艺中的适合的激光装备可为任何那些市售可得的激光。例如，可适合地使用具有能量等级介于1与2watts之间的一连续Nd/YAG激光。本领域普通技术人员了解可适合地调整激光的能量以仅移除所需的硅层的深度、宽度及/或长度。本领域普通技术人员也了解深度应够深以允许之后要被沉积的成形化合物(later-to-be deposited molding compound)被形成于沟槽60中以可充分附着或固定至下方晶片22以使在温度循环测试(temperature cycle test)或切割步骤期间，例如成形化合物不会自晶片变形或脱层(delaminate)。于相同意义下，在由于沟槽60形成而在于硅层中建立应力之处，深度应不那么深。在本发明一实施例中，形成沟槽60至介于约100
Figure BSA00000189427700041
至约150,000
Figure BSA00000189427700042
之间的一深度。在另一实施例中，形成沟槽60至介于约1,000
Figure BSA00000189427700043
至约50,000之间的一深度。
如图2中所示，形成一或多个沟槽60于晶片22的正表面上介于多个裸片20的任两个之间。然后参见图3，将一成形化合物或保护材料100涂覆于晶片22的正表面80上、于多个裸片20上，及实质上于沟槽60中。保护材料100由一可固化材料，例如一聚合物材料、树脂材料、聚亚酰胺、氧化硅、环氧树脂、苯并环丁烯(Benzocyclobutene，BCB)、SILKTM(Dow Chemical)或其组合所形成。为了避免晶片22或要被研磨的本体(body)在一研磨工艺中扭曲，例如，在保护材料100固化后，保护材料100较佳具有充分地高刚度(stiffness)与挠曲刚性(flexural rigidity)。可于晶片22上形成保护材料100至厚度大于裸片20的高度以封住裸片20。保护材料20的厚度并无特别限制，只要其可确保一后工艺(later process)，例如晶片22或要被研磨的本体的研磨，所需的厚度一致。然而，为了在基板的研磨后，获得所需的厚度一致，保护材料100的厚度较佳为一致。
使用工艺，如射出成形(injection molding)、压缩成形(compressionmolding)、钢板印刷(stencil printing)、旋涂(spin-on coating)或未来发展的成形工艺(molding process)可将保护材料100提供至集成电路结构10。在保护材料100的涂覆之后与一后来的晶片薄化或切割工艺之前，执行一固化或烘烤步骤以固化保护材料100。在本发明一实施例中，于一加热腔室中在自约100℃至约200℃的温度下，以自约30分钟至约8小时的时间，烘烤保护材料100。在固化保护材料100后，晶片22的非芯片侧可接受一进一步的薄化工艺来研磨非芯片侧以减少晶片的厚度。
回到沟槽60形成的讨论上，图6显示根据本发明一实施例，一集成电路结构10的剖面图，其中沟槽60形成于裸片20的周围(但在裸片切割线区内)且实质上被以成形材料100填入。图5显示相同的集成电路结构，但为一俯视图，其中成形材料100形成于沟槽60中。为了清楚说明，未显示成形材料100形成于裸片20、底胶材料25或晶片22的部分之上。图5显示根据发明一实施例，沟槽60为一环绕裸片20的连续沟槽。然而，在一些实施例中，沟槽60可为一非连续沟槽，换句话说，沟槽60可包括一或多个独立且分离的沟槽，其实质上连续沿着裸片20的周围。
图8显示根据本发明一实施例，集成电路结构10的剖面图，其中沟槽60形成在裸片20的周围但较接近裸片20，且实质上被以成形化合物100填入。图7显示集成电路结构的俯视图，其中显示成形化合物100形成于沟槽60中。另外，为了清楚的目的，于图7中未显示成形化合物100形成于裸片20、底胶材料25或晶片22的部分之上。图7显示根据本发明一实施例，沟槽60为形成于裸片20的周围的一连续沟槽。然而，在一些实施例中，沟槽60可为一非连续沟槽，其意指，沟槽60可包括一些各自分离的沟槽，其实质上连续沿着裸片20的周围。在一些实施例中，沟槽60形成于晶片22中实质上连续沿着晶片的一或多个裸片切割线。
虽然显示于图5至图8中的沟槽60具有矩形的形状，然而可以了解的是，根据依照所实施的制造工艺的设计选择，沟槽60可包括任何形状。例如，沟槽60可具有一圆形、卵形、矩形、三角形、正方形、五边形、六边形、七边形、八边形、星形、十字形或椭圆形的形状。图10与图9显示根据一实施例，包括一矩形、圆形(各种尺寸)与十字形的形状的沟槽。
然后参见图4，一般在晶片已接受一晶片等级测试程序后，接着将晶片22倒置且固定至切割胶带(dicing tape)110或一裸片模(die frame)，其为之后以一般方式沿着切割线93被切割以将经封住的晶片分成用于固定于一基板，例如印刷电路板(printed circuit board，PCB)上的各自的半导体封装体。
图11显示一形成集成电路结构的方法200的一实施例。经由提供一晶片，其具有一芯片侧与一非芯片侧，芯片侧包括多个半导体芯片，方法200开始于步骤202。于步骤204，提供多个裸片，各个裸片结合至多个半导体芯片之一。于步骤206，一或多个沟槽形成于晶片的芯片侧上。于步骤208，将晶片的芯片侧与多个裸片以一保护材料封住，保护材料实质上填入一或多个沟槽。于步骤210，切割晶片以将其分成用于固定于一基板(例如，印刷电路板)上的各自的半导体封装体。
可将根据本发明实施例的形成晶片级芯片模压封装(wafer level chipmolded package)的方法实施于广大范围的封装应用。由于具有成形化合物嵌入于下方晶片中，增强了介于成形化合物与晶片之间的附着。这避免了可起因于温度循环测试的可能脱层，而在温度循环测试中，例如热膨胀系数(coefficient of thermal Expansion，CTE)变成一议题。
虽然本发明已以优选实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (15)

1.一种形成集成电路结构的方法，包括：
提供一晶片，其具有一芯片侧与一非芯片侧，该芯片侧包括多个半导体芯片；
提供多个裸片，各个所述裸片结合至所述多个半导体芯片之一；
形成一或多个沟槽于该晶片的该芯片侧上；
将该晶片的该芯片侧与所述多个裸片封住，且实质上以一保护材料填入所述一或多个沟槽；以及
切割该晶片以将该晶片分成各自的半导体封装体。
2.如权利要求1所述的形成集成电路结构的方法，其中各个所述多个裸片借由焊料凸块结合至所述多个半导体芯片之一。
3.如权利要求2所述的形成集成电路结构的方法，其中形成一底胶材料以填入介于所述多个裸片之一与所述多个芯片之一间的一缺口，该底胶材料实质上封住该焊料凸块。
4.如权利要求1所述的形成集成电路结构的方法，其中形成一或多个沟槽于该晶片的该芯片侧上介于所述多个裸片的任两个之间。
5.如权利要求4所述的形成集成电路结构的方法，其中所述一或多个沟槽借由一高能束形成。
6.如权利要求1所述的形成集成电路结构的方法，其中所述一或多个沟槽使用一激光切割技术形成。
7.如权利要求1所述的形成集成电路结构的方法，其中所述一或多个沟槽实质上连续沿着所述裸片之一的一周围被形成于该晶片中。
8.如权利要求7所述的形成集成电路结构的方法，其中所述一或多个沟槽被形成于该晶片的一裸片切割线区内。
9.如权利要求1所述的形成集成电路结构的方法，其中所述一或多个沟槽实质上连续沿着该裸片的一裸片切割线被形成于该晶片中。
10.如权利要求1所述的形成集成电路结构的方法，还包括在该切割该晶片的步骤前烘烤该保护材料以固化该保护材料。
11.一种形成集成电路结构的方法，包括：
提供一晶片，其具有一芯片侧与一非芯片侧，该芯片侧包括多个半导体芯片；
提供多个裸片，各个所述裸片结合至所述多个半导体芯片之一；
将一高能束聚焦于该晶片的该芯片侧上以形成一或多个沟槽；
将该晶片的该芯片侧与所述多个裸片封住，并以一保护材料填入所述一或多个沟槽；
烘烤该保护材料以固化该保护材料；以及
切割该晶片以将该晶片分成各自的半导体封装体。
12.一种集成电路结构，包括：
一半导体芯片，其具有一裸片侧与一非粒片侧，该裸片侧具有一或多个沟槽形成于其中；
至少一个裸片，结合至该半导体芯片的该裸片侧；以及
一保护材料，封住所述至少一裸片且实质上填入所述一或多个沟槽。
13.如权利要求12所述的集成电路结构，其中所述一或多个沟槽被形成至介于约100
Figure FSA00000189427600021
至约150,000
Figure FSA00000189427600022
之间的一深度。
14.如权利要求12所述的集成电路结构，其中所述一或多个沟槽连续沿着该裸片的一周围被形成于该晶片中。
15.如权利要求14所述的集成电路结构，其中所述一或多个沟槽被形成于该半导体芯片的一切割线区内。
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021960A (zh) * 2011-09-27 2013-04-03 台湾积体电路制造股份有限公司 三维集成电路的制造方法
CN103489832A (zh) * 2012-06-12 2014-01-01 矽品精密工业股份有限公司 封装基板板片结构、封装基板、半导体封装件及其制法
CN104112739A (zh) * 2013-04-16 2014-10-22 展晶科技(深圳)有限公司 发光二极管
CN106469712A (zh) * 2015-08-20 2017-03-01 矽品精密工业股份有限公司 电子封装结构及其制法
CN107068618A (zh) * 2017-03-20 2017-08-18 通富微电子股份有限公司 一种半导体圆片级封装方法
CN107093579A (zh) * 2017-03-20 2017-08-25 通富微电子股份有限公司 半导体圆片级封装方法、器件及封装用刀具
CN110504223A (zh) * 2018-05-18 2019-11-26 南茂科技股份有限公司 半导体封装结构及其制造方法
US11437292B2 (en) 2019-10-11 2022-09-06 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9059187B2 (en) 2010-09-30 2015-06-16 Ibiden Co., Ltd. Electronic component having encapsulated wiring board and method for manufacturing the same
US8569086B2 (en) * 2011-08-24 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of dicing semiconductor devices
US9263360B2 (en) * 2012-07-06 2016-02-16 Henkel IP & Holding GmbH Liquid compression molding encapsulants
US9330954B2 (en) * 2013-11-22 2016-05-03 Invensas Corporation Substrate-to-carrier adhesion without mechanical adhesion between abutting surfaces thereof
US9728511B2 (en) * 2013-12-17 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor wafer and semiconductor die
US9524942B2 (en) 2013-12-18 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-substrate packaging on carrier
US9522822B2 (en) 2014-05-13 2016-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor integration with an outgassing barrier and a stable electrical signal path
US9567204B2 (en) 2014-08-29 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectrochemical systems (MEMS) device having a seal layer arranged over or lining a hole in fluid communication with a cavity of the MEMS device
US10131540B2 (en) 2015-03-12 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method to mitigate soldering offset for wafer-level chip scale package (WLCSP) applications
CN104882385B (zh) * 2015-05-06 2017-10-24 日月光封装测试(上海)有限公司 降低半导体封装进行稳定烘烤时产生裂纹的方法及其装置
WO2017121484A1 (en) * 2016-01-14 2017-07-20 Lantiq Beteiligungs-GmbH & Co.KG Slicing concept for wafers
JP2018046094A (ja) * 2016-09-13 2018-03-22 エイブリック株式会社 半導体チップ、半導体装置、半導体ウェハ、及び半導体ウェハのダイシング方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040121563A1 (en) * 2002-03-06 2004-06-24 Farnworth Warren M. Method for fabricating encapsulated semiconductor components having conductive vias
US20070132104A1 (en) * 2003-03-31 2007-06-14 Farnworth Warren M Semiconductor component having plate, stacked dice and conductive vias
CN101188221A (zh) * 2006-11-20 2008-05-28 松下电器产业株式会社 布线基板和采用该布线基板的半导体器件
US7413927B1 (en) * 2003-02-12 2008-08-19 National Semiconductor Corporation Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages
CN101262002A (zh) * 2007-02-08 2008-09-10 育霈科技股份有限公司 具有晶粒容纳通孔的影像传感器封装与其方法
CN101266933A (zh) * 2007-03-14 2008-09-17 矽品精密工业股份有限公司 半导体装置的制法及其用于该制法的承载件

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2207013A (en) * 1939-08-10 1940-07-09 Laurence A Jolidon Material depositing bag
US20020081771A1 (en) * 2000-12-22 2002-06-27 Yi-Chuan Ding Flip chip process
US6399463B1 (en) * 2001-03-01 2002-06-04 Amkor Technology, Inc. Method of singulation using laser cutting
US6838299B2 (en) * 2001-11-28 2005-01-04 Intel Corporation Forming defect prevention trenches in dicing streets
JP2003332270A (ja) * 2002-05-15 2003-11-21 Renesas Technology Corp 半導体装置およびその製造方法
US7087452B2 (en) * 2003-04-22 2006-08-08 Intel Corporation Edge arrangements for integrated circuit chips
JP2006140404A (ja) * 2004-11-15 2006-06-01 Renesas Technology Corp 半導体装置
TWI303873B (en) * 2005-09-23 2008-12-01 Freescale Semiconductor Inc Method of making stacked die package
US8629532B2 (en) * 2007-05-08 2014-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor wafer with assisting dicing structure and dicing method thereof
US7955955B2 (en) * 2007-05-10 2011-06-07 International Business Machines Corporation Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040121563A1 (en) * 2002-03-06 2004-06-24 Farnworth Warren M. Method for fabricating encapsulated semiconductor components having conductive vias
US7413927B1 (en) * 2003-02-12 2008-08-19 National Semiconductor Corporation Apparatus for forming a pre-applied underfill adhesive layer for semiconductor wafer level chip-scale packages
US20070132104A1 (en) * 2003-03-31 2007-06-14 Farnworth Warren M Semiconductor component having plate, stacked dice and conductive vias
CN101188221A (zh) * 2006-11-20 2008-05-28 松下电器产业株式会社 布线基板和采用该布线基板的半导体器件
CN101262002A (zh) * 2007-02-08 2008-09-10 育霈科技股份有限公司 具有晶粒容纳通孔的影像传感器封装与其方法
CN101266933A (zh) * 2007-03-14 2008-09-17 矽品精密工业股份有限公司 半导体装置的制法及其用于该制法的承载件

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103021960B (zh) * 2011-09-27 2015-11-04 台湾积体电路制造股份有限公司 三维集成电路的制造方法
CN103021960A (zh) * 2011-09-27 2013-04-03 台湾积体电路制造股份有限公司 三维集成电路的制造方法
CN103489832A (zh) * 2012-06-12 2014-01-01 矽品精密工业股份有限公司 封装基板板片结构、封装基板、半导体封装件及其制法
CN103489832B (zh) * 2012-06-12 2017-06-06 矽品精密工业股份有限公司 封装基板板片结构、封装基板、半导体封装件及其制法
CN104112739A (zh) * 2013-04-16 2014-10-22 展晶科技(深圳)有限公司 发光二极管
CN106469712B (zh) * 2015-08-20 2019-04-12 矽品精密工业股份有限公司 电子封装结构及其制法
CN106469712A (zh) * 2015-08-20 2017-03-01 矽品精密工业股份有限公司 电子封装结构及其制法
CN107068618A (zh) * 2017-03-20 2017-08-18 通富微电子股份有限公司 一种半导体圆片级封装方法
CN107093579A (zh) * 2017-03-20 2017-08-25 通富微电子股份有限公司 半导体圆片级封装方法、器件及封装用刀具
CN107068618B (zh) * 2017-03-20 2021-02-19 通富微电子股份有限公司 一种半导体圆片级封装方法
CN110504223A (zh) * 2018-05-18 2019-11-26 南茂科技股份有限公司 半导体封装结构及其制造方法
CN110504223B (zh) * 2018-05-18 2021-02-19 南茂科技股份有限公司 半导体封装结构及其制造方法
US11437292B2 (en) 2019-10-11 2022-09-06 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same

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