CN103021960B - 三维集成电路的制造方法 - Google Patents

三维集成电路的制造方法 Download PDF

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CN103021960B
CN103021960B CN201210189854.XA CN201210189854A CN103021960B CN 103021960 B CN103021960 B CN 103021960B CN 201210189854 A CN201210189854 A CN 201210189854A CN 103021960 B CN103021960 B CN 103021960B
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wafer
semiconductor element
lamination
integrated circuits
manufacture
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CN103021960A (zh
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林俊成
吴文进
施应庆
洪瑞斌
卢思维
郑心圃
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to CN201510438633.5A priority Critical patent/CN105118788B/zh
Priority to CN201510438514.XA priority patent/CN105118810B/zh
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Abstract

一种制造三维集成电路的方法，包括：提供晶圆叠层，其中，将多个半导体管芯安装在第一半导体管芯上方；将模塑料层形成在第一半导体管芯的第一面上方，其中，将多个半导体管芯内嵌在模塑料层中。方法进一步包括：研磨第一半导体管芯的第二面直到暴露多个通孔；将晶圆附接至带框并切割晶圆叠层，从而将晶圆叠层分成多个独立封装件。

Description

三维集成电路的制造方法
技术领域
本发明一般地涉及半导体领域，更具体地来说，涉及一种三维集成电路的制造方法。
背景技术
半导体行业由于各种电子元件（例如，晶体管、二极管、电阻器、电容器等）集成密度的改进而经历了快速增长。在极大程度上，这种集成密的改进源于半导体工艺节点的缩小（例如，朝向低于20nm的节点缩小工艺节点）。由于近来对微型化、更高的速度和更大的带宽、以及更低的功耗和延迟的需求增加，所以增加了对更小和更有创造性的半导体管芯封装技术的需求。
随着半导体技术的发展，作为有效选择，已经出现了基于多芯片晶圆级封装的半导体器件，从而进一步减小了半导体芯片的实际尺寸。在基于晶圆级封装的半导体器件中，在不同的晶圆上制造有源电路，例如，逻辑电路、存储器电路、处理器电路等，采用拾取与放置技术，将每个晶圆管芯堆叠在另一个晶圆管芯的顶部上。可以通过采用多芯片半导体器件实现更高的密度。此外，多管芯半导体器件可以实现更小的外形尺寸、成本效益、提高的性能和更低的功耗。
三维（3D）集成电路（IC）可以包括顶部有源电路层、底部有源电路层和多个中间层。在3D IC中，两个管芯可以通过多个微凸块接合在一起，并且通过多个衬底通孔彼此电连接。微凸块和衬底通孔提供了在3D IC的垂直轴上的电气互连。结果，两个半导体管芯之间的信号路径短于传统的3D IC，在该传统的3D IC中，采用诸如基于引线接合的芯片堆叠封装的互连技术将不同的管芯接合在一起。3D IC可以包括各种堆叠在一起的半导体管芯。在晶圆切割以前，封装多个半导体管芯。晶圆级封装技术具有一些的优点。晶圆级封装多个半导体管芯的一个有利特征是多芯片晶圆级封装技术可以降低制造成本。基于晶圆级封装的多芯片半导体器件的另一个有利特征是通过采用微凸块和衬底通孔降低寄生损失（parasitic loss）。
发明内容
为了解决现有技术中所存在的技术问题，根据本发明的一方面，提供了一种方法，包括：提供叠层，其中，将多个半导体管芯安装在晶圆的第一面上方；模塑料层形成在所述晶圆的所述第一面上方，其中，所述多个半导体管芯内嵌在所述模塑料层中；薄化所述晶圆的第二面直到暴露多个通孔；将叠层附接至带框；以及切割所述叠层，从而将所述叠层分成多个独立封装件。
该方法进一步包括：将第一底部填充层形成在所述晶圆和所述多个半导体管芯之间。
该方法进一步包括：将所述多个通孔形成在所述晶圆中；将多个第一凸块形成在所述晶圆的所述第一面上方；以及将第一再分布层形成在所述晶圆的所述第一面上方。
在该方法中，所述多个半导体管芯通过所述多个第一凸块和所述第一再分布层连接至所述晶圆。
该方法进一步包括：将多个第二凸块形成在所述晶圆的所述第二面上方；以及将第二再分布层形成在所述晶圆的所述第二面上方。
该方法进一步包括：将所述带框与每个独立封装件分离。
该方法进一步包括：将所述独立封装件附接至所述衬底上。
该方法进一步包括：将保护层形成在所述模塑料层的外边缘和所述叠层的外边缘之间。
根据本发明的另一方面，提供了一种方法，包括：提供叠层，其中，将多个半导体管芯安装在晶圆的第一面上方，其中，所述晶圆包括多个通孔；将模塑料层形成在所述晶圆的所述第一面上方，其中，将所述多个半导体管芯内嵌在所述第一模塑料层中；扩展所述模塑料层，以覆盖所述晶圆的外边缘；薄化所述晶圆的第二面，从而暴露所述多个通孔；将所述叠层附接至带框；以及切割所述叠层，从而将所述叠层分成多个独立封装件。
该方法进一步包括：将所述带框与每个独立封装件分离，以及将独立封装件附接至衬底。
该方法进一步包括：将第一底部填充层形成在所述晶圆和所述多个半导体管芯之间；以及将第二底部填充层形成在所述独立封装件和所述衬底之间。
该方法进一步包括：清洗所述独立封装件的表面；以及清洗所述晶圆的所述外边缘。
该方法进一步包括：化学抛光所述晶圆的所述第二面；将第二再分布层形成在所述晶圆的所述第二面上方；以及将多个凸块形成在所述晶圆的所述第二面上方。
该方法进一步包括：将第一再分布层形成在所述晶圆的所述第一面上方；以及将电连接至所述第一再分布层的多个凸块形成在所述晶圆的所述第一面上方。
根据本发明的又一方面，提供了一种结构，包括：基板；以及叠层，被安装在所述基板上方，包括：多个半导体管芯，接合在管芯的第一面上方；以及模塑料层，形成在所述管芯的所述第一面上方并覆盖所述管芯的外边缘，其中，将所述多个半导体管芯内嵌在所述模塑料层中。
该结构进一步包括：多个凸块，形成在所述衬底和所述叠层之间。
在该结构中，所述多个半导体管芯通过多个第一凸块与所述管芯连接。
该结构进一步包括：第一底部填充层，形成在所述多个半导体管芯和所述管芯之间；以及第二底部填充层，形成在所述管芯和所述衬底之间。
该结构进一步包括：多个通孔，位于所述管芯中。
附图说明
为了更完整地理解本发明及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1-5是根据实施例制造三维（3D）集成电路（IC）的中间阶段的横截面图；
图6-10是根据另一个实施例制造3D IC的中间阶段的横截面图；以及
图11-15是根据又一个实施例制造3D IC的中间阶段的横截面图。
除非另有说明，不同附图中的相应数字和符号通常指的是对应部件。为了清楚地说明各个实施例的相关方面绘制这些附图，并且没有必要按比例绘制。
具体实施方式
以下详细讨论了本实施例的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的创造性概念。所讨论的具体实施例仅为制造和使用本发明的具体方式，并且没有限定本发明的范围。
将结合具体上下文的实施例描述本发明，即，制造三维（3D）集成电路（IC）的方法。然而，也可以将本发明应用于各种集成电路的半导体制造。
图1-5是根据实施例制造3D IC的中间阶段的横截面图。晶圆叠层100可以包括晶圆102和安装在该晶圆102顶部的多个半导体管芯。根据实施例，晶圆102是硅晶圆。如图1所示，多个半导体管芯可以包括：第一半导体管芯154、第二半导体管芯156、第三半导体管芯164、以及第四半导体管芯166。晶圆102可以是厚度超过100um的标准晶圆。根据实施例，晶圆102的厚度可以为约700um。晶圆102可以包括多个集成电路（未示出），每个集成电路可以包括各种层，例如，有源电路层、衬底层、层间介电（ILD）层和金属间介电（IMD）层（未示出）。晶圆102可以进一步包括多个微凸块134，形成在晶圆102和多个半导体管芯（例如，第一半导体管芯154）之间。此外，多个微凸块134的连接可以通过形成在晶圆102顶部上的再分布层132进行重新分配。
晶圆102可能进一步包括多个通孔。在一些实施例中，通孔是衬底通孔（TSV）或者硅通孔（TSV），例如TSV 112、TSV 114、TSV 116、TSV118、TSV 122、TSV 124、TSV 126、和TSV 128。可以将晶圆102的有源电路层（未示出）连接至微凸块134和/或多个TSV中的一个或多个（例如，TSV 112）。有源电路层通过多个微凸块134进一步连接至第一半导体管芯154、第二半导体管芯156、第三半导体管芯164、以及第四半导体管芯166。
底部填充材料152可以形成在晶圆102和安装在该晶圆102顶部的多个半导体管芯（例如，第一半导体管芯154）之间的间隙中。根据实施例，底部填充材料152可以是环氧树脂，将该底部填充材料散布在晶圆102和第一半导体管芯154之间的间隙中。可以以液体形式施加环氧树脂，并且可以在固化工艺以后变硬。根据另一个实施例，底部填充层152可以由固化材料形成，例如聚合物材料、树脂基材料、聚酰亚胺、环氧树脂及其任意组合。底部填充层152可以由旋涂工艺、干膜层压工艺等形成。具有底部填充材料（例如，底部填充材料152）的有利特征是底部填充材料152有助于防止微凸块134开裂。此外，底部填充材料152可以有助于减少晶圆叠层100制造过程中的机械应力和热应力。
图2示出了具有形成在晶圆102顶部的模塑料层的3D IC结构的横截面图。如图2所示，将第一半导体管芯154、第二半导体管芯156、第三半导体管芯164、以及第四半导体管芯166内嵌在模塑料层202中。模塑料层202可以由固化材料形成，例如，聚合物材料、树脂基材料、聚酰亚胺、环氧树脂及其任意组合。模塑料层202可以通过旋涂工艺、注入成型工艺等形成。为了在诸如将晶圆叠层100切割成独立的芯片封装件的工艺步骤期间可靠地处理晶圆102和安装在该晶圆102顶部的半导体管芯（例如，第一半导体管芯154），采用模塑料层202，以防止晶圆102和安装在晶圆102顶部的半导体管芯的开裂、弯曲、翘曲等。
图3示出了背面研磨的工艺。晶圆102的背面进行薄化工艺。薄化工艺可以采用机械研磨工艺、化学抛光工艺、蚀刻工艺等。采用薄化工艺，可以研磨晶圆102的背面，从而使得晶圆102的厚度可以大约小于100um。根据实施例，可以将晶圆102的厚度减小到大约20um至大约50um的范围。应该注意，通过研磨晶圆102到低至20um的厚度，装置较薄的晶圆能够实现较小通孔的特征尺寸，例如，通孔直径和深度。形成较小的TSV的有利特征是晶圆叠层100的性能和功耗可以进一步改善。
可选地，可以研磨晶圆102的厚度直到暴露TSV（例如，TSV 112）的内嵌端部。随后，再分布层304形成在晶圆102的新研磨背面顶部的上方。此外，多个凸块302形成在TSV的暴露端顶部。应该注意，凸块302可以形成在除TSV的暴露端以外的位置处并通过再分布层304与TSV（例如，TSV 116）重新连接。
图4示出了晶圆叠层100附接至带框400的工艺。晶圆叠层100安装在带框400的顶部。带框400可以包括涂覆有临时粘合剂的载具。接合工艺可以在处理室内实施，其中，将晶圆叠层100接合到带框400顶部。本领域中众所周知将晶圆叠层附接到带框的工艺，因此此处没有更详细地进行讨论。
图4进一步示出了采用切割工艺将晶圆叠层100分成多个独立封装件的工艺。如图4所示，诸如第一封装件402和第二封装件404的多个独立封装件通过将晶圆叠层100切割为独立封装件形成。每个独立封装件都可以包括至少一个接合到管芯（例如，管芯102a）上方的半导体管芯。本领域中众所周知切割工艺,因此此处没有详细地进行讨论。应该注意，尽管图4示出了将具有晶圆叠层100的多个半导体管芯的面（与倒装芯片凸块的面相反）附接至带框400，然后实施切割工艺，本领域的技术人员将意识到可能存在本发明实施例的多个变型例。例如，可以将晶圆叠层100的倒装芯片凸块面附接至带框400。还可以从晶圆叠层100的半导体管芯面实施切割工艺。
图5示出了在切割工艺之后的3D IC的横截面图。如图5所示，封装件402和404（未示出，而在图4中示出）已采用拾取与放置工艺从带框400（未示出）移除。本领域周所周知拾取与放置工艺，因此此处没有进行更详细地讨论以避免重复。第一封装件402和第二封装件404的表面可以通过化学溶剂进一步进行抛光，然后再次翻转。随后，将诸如第一封装件402的独立封装件安装在衬底502上方从而形成3D IC。根据实施例，衬底502可能是有机衬底。此外，为了减少机械应力和热应力，底部填充材料504形成在第一封装件402和基板502之间的间隙中。
图6至图10是根据另一个实施例制造3D IC的中间阶段的横截面图。除了在图7中模塑料层702扩展到覆盖晶圆102的边缘以外，图6至图10类似图1至图5。为了在诸如将晶圆叠层100切割为独立芯片封装件的工艺步骤期间保护晶圆102的边缘，模塑料层702用来防止边缘开裂。形成模塑料层702的工艺类似于形成模塑料层202的工艺，因此此处没有更详细地讨论以避免不必要的重复。已经参考图3至图5描述了研磨晶圆102背面、将晶圆叠层100附接至带框400并且将晶圆叠层100切割为多个独立封装件的工艺过程，因此没有再次进行讨论以避免重复。
图11至图15是根据又一个实施例制造3D IC的中间阶段的横截面图。除了在模塑料层202边缘和晶圆102的边缘之间形成额外的保护材料1202以外，图11至图15类似于图1至图5。为了在诸如将晶圆切割成独立的芯片封装件的工艺步骤期间保护晶圆102的边缘，采用模塑料层702从而防止边缘开裂。此外，采用额外的保护材料1202，从而提供了缓冲区域，该缓冲区域在制造3D IC过程中吸收机械应力和热应力。额外的保护材料1202可以通过在模塑料层202边缘和晶圆102的边缘之间散布、层压和/或印刷额外的保护材料来形成。根据实施例，保护材料1202可以是诸如聚酰亚胺（PI）、环氧树脂等的高分子材料。已参考图3至图5描述了研磨晶圆102的背面、晶圆叠层100附接至带框400并且将晶圆叠层100切割为多个独立封装件的工艺过程，因此没有再次进行讨论以避免重复。
根据实施例，方法包括：提供晶圆叠层，其中，将多个半导体管芯安装在第一半导体管芯的第一面上；将模塑料层形成在第一半导体管芯的第一面上，其中多个半导体管芯内嵌模塑料层中。方法进一步包括：薄化第一半导体管芯的第二面直到暴露多个通孔；将晶圆叠层附接到带框并切割晶圆叠层，从而将晶圆叠层分成多个独立封装件。
根据另一个实施例，方法包括：提供晶圆叠层，其中，将多个半导体管芯安装在第一半导体管芯的第一面上；在第一半导体管芯的第一面上形成模塑料层，其中，将多个半导体管芯内嵌在模塑料层中并扩展模塑料层以覆盖第一半导体管芯的外边缘。方法进一步包括：薄化第一半导体管芯的第二面直到暴露多个通孔；将晶圆叠层附接至带框并切割晶圆叠层，从而将晶圆叠层分成多个独立封装件。
根据又一个实施例，结构包括：基板层和安装在该基板层上方的第一半导体管芯。第一半导体管芯包括：多个凸块，位于第一半导体管芯的第一面上方的；多个微凸块，位于第一半导体管芯的第二面上方以及再分布层，形成在第一半导体管芯的第二面顶部。结构进一步包括：安装在第一半导体管芯的第二面顶部的多个半导体管芯。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变、替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明的公开，现有的或今后开发的用于执行与本文所述相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，所附权利要求应该包括在这样的工艺、机器、制造、材料组分、装置、方法或步骤的范围内。

Claims (7)

1.一种制造三维集成电路的方法，包括：
提供叠层，其中，将多个半导体管芯安装在晶圆的第一面上方；
模塑料层形成在所述晶圆的所述第一面上方，其中，所述多个半导体管芯内嵌在所述模塑料层中；
将保护层形成在所述模塑料层的外边缘和所述叠层的外边缘之间；
薄化所述晶圆的第二面直到暴露多个通孔；
将叠层附接至带框；以及
切割所述叠层，从而将所述叠层分成多个独立封装件。
2.根据权利要求1所述的制造三维集成电路的方法，进一步包括：
将第一底部填充层形成在所述晶圆和所述多个半导体管芯之间。
3.根据权利要求1所述的制造三维集成电路的方法，进一步包括：
将所述多个通孔形成在所述晶圆中；
将多个第一凸块形成在所述晶圆的所述第一面上方；以及
将第一再分布层形成在所述晶圆的所述第一面上方。
4.根据权利要求3所述的制造三维集成电路的方法，其中，所述多个半导体管芯通过所述多个第一凸块和所述第一再分布层连接至所述晶圆。
5.根据权利要求1所述的制造三维集成电路的方法，进一步包括：
将多个第二凸块形成在所述晶圆的所述第二面上方；以及
将第二再分布层形成在所述晶圆的所述第二面上方。
6.根据权利要求1所述的制造三维集成电路的方法，进一步包括：
将所述带框与每个独立封装件分离。
7.根据权利要求6所述的制造三维集成电路的方法，进一步包括：
将所述独立封装件附接至衬底上。
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