TWI622149B - 封裝結構的製造方法 - Google Patents

封裝結構的製造方法 Download PDF

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Publication number
TWI622149B
TWI622149B TW106117813A TW106117813A TWI622149B TW I622149 B TWI622149 B TW I622149B TW 106117813 A TW106117813 A TW 106117813A TW 106117813 A TW106117813 A TW 106117813A TW I622149 B TWI622149 B TW I622149B
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Taiwan
Prior art keywords
conductive
wafer
layer
package
package structure
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TW106117813A
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English (en)
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TW201826476A (zh
Inventor
徐宏欣
林南君
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力成科技股份有限公司
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Priority to US15/717,956 priority Critical patent/US10332844B2/en
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Publication of TWI622149B publication Critical patent/TWI622149B/zh
Publication of TW201826476A publication Critical patent/TW201826476A/zh

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Abstract

本發明提供一種封裝結構的製造方法。首先，提供載板。於載板上形成導電層。於導電層上形成導電邊框，導電邊框連接導電層。將晶片置於導電層上，導電邊框環繞晶片。形成絕緣封裝體以包覆晶片，絕緣封裝體露出晶片的主動表面。於晶片的主動表面上形成重新佈線層，重新佈線層從主動表面上往絕緣封裝體上延伸。

Description

封裝結構的製造方法
本發明是有關於一種封裝結構的製造方法，且特別是有關於一種包含導電邊框的封裝結構的製造方法。
隨著科的進展，為了符合輕、薄、短、小的市場需求，半導體元件的尺寸逐年縮小，且半導體元件之間的距離也越來越短。然而，半導體元件容易被鄰近的半導體元件所發出的電磁波影響，導致半導體元件無法正確的運作，而這種情況在小尺寸的半導體元件中更加嚴重。
在現有的封裝結構中，常常在封裝結構中加入金屬外殼來減輕半導體元件所受到的電磁干擾(electromagnetic interference,EMI)。然而，包含金屬外殼的封裝結構的製作過程很複雜，且封裝結構的尺寸較大。因此，目前亟需一種能解決上述問題的方法。
本發明提供一種封裝結構的製造方法，製程簡單且能有 效減輕晶片所受到的電磁干擾。
本發明的一種封裝結構的製造方法包括：提供載板。於載板上形成導電層。於導電層上形成導電邊框，導電邊框連接導電層。將多個晶片置於導電層上，每一個晶片包括主動表面以及相對於主動表面的背面，晶片的背面貼於導電層上，導電邊框環繞晶片。形成絕緣封裝體以包覆晶片，絕緣封裝體露出每一個晶片的主動表面。於每一個晶片的主動表面上形成重新佈線層，重新佈線層從主動表面上往絕緣封裝體上延伸。
本發明的一種封裝結構的製造方法包括：提供載板。於載板上形成重新佈線層。於重新佈線層上形成導電邊框。將多個晶片置於重新佈線層上，每一個晶片包括主動表面以及相對於主動表面的背面，每一個晶片的主動表面電性連接重新佈線層，導電邊框環繞晶片。形成絕緣封裝體以包覆晶片。於絕緣封裝體上形成導電層，導電邊框連接導電層。
基於上述，本發明的封裝結構包括導電邊框以及導電層。導電邊框以及導電層能減輕晶片所受到的電磁干擾。本發明封裝結構的製造方法製程簡單，能降低封裝結構的製造成本。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10、20、30、40‧‧‧封裝結構
100‧‧‧載板
102‧‧‧膠層
110、110A‧‧‧導電盒
112‧‧‧導電層
114、114A、114B‧‧‧導電邊框
120、220‧‧‧晶片
122、222‧‧‧晶片接墊
124、224‧‧‧導電凸塊
126‧‧‧黏著層
130‧‧‧絕緣封裝體
140、240‧‧‧重新佈線層
142A、142B、242A、242B‧‧‧接墊
144、244‧‧‧導線層
150‧‧‧導電球
160‧‧‧保護膜
AS‧‧‧主動表面
BS‧‧‧背面
B‧‧‧第一面
T‧‧‧第二面
圖1A~圖1I是依照本發明的一實施例的一種封裝結構的製造方法的剖面示意圖。
圖2是依照本發明的一實施例的一種封裝結構的剖面示意圖。
圖3是依照本發明的一實施例的一種封裝結構的剖面示意圖。
圖4A~圖4I是依照本發明的一實施例的一種封裝結構的製造方法的剖面示意圖。
圖1A~圖1I是依照本發明的一實施例的一種封裝結構的製造方法的剖面示意圖。
請參考圖1A，提供載板100。在一實施例中，載板100包括位於表面的膠層102。膠層102例如包括離型層、黏著層或其組合。
接著請參考圖1B，於載板100上形成導電層112。在一實施例中，形成導電層112的方法包括物理氣相沉積法。在一實施例中，形成導電層112的方法包括電鍍。導電層112的材料例如包括銅、錫、鋁、鋼或其他合適的金屬。
於載板100上形成導電邊框114，導電邊框114連接導電層112。在一實施例中，形成導電邊框114的方法例如是先形成絕緣層，圖案化絕緣層以後進行電鍍製程以將金屬填入圖案化後的絕緣層中，接著在移除絕緣層。在一實施例中，導電邊框114是利用電鍍製程而直接形成在導電層112上。換句話說，導電邊框 114與導電層112連成一體，因此，不需要額外的固定結構來將導電邊框114固定於導電層112上。在一實施例中，導電邊框114的材料例如與導電層112的材料相同。導電邊框114的延伸方向例如垂直於導電層112所在的平面。在一實施例中，導電邊框114與導電層112例如電性連接至接地電壓或是外部電源提供的電壓。在一實施例中，導電邊框114與導電層112都具有優良的熱傳導性，能增強封裝結構的散熱性能。在一實施例中，導電邊框114與導電層112選用堅固的材料，能作為支撐結構使用，並能減輕封裝結構翹曲的問題，使表面更平坦化，增加光蝕刻製程的製程裕度。
請參考圖1C，將多個晶片120置於導電層112上，晶片120包括主動表面AS以及相對於主動表面AS的背面BS。在一實施例中，晶片120的主動表面AS上包括晶片接墊122以及導電凸塊124。導電凸塊124與晶片接墊122電性連接，導電凸塊124的材料包括銅、錫、金、鎳或其他導電材料。舉例來說，導電凸塊124可以是銅、金、鎳或是其他導電材料所構成的單層結構，也可以是銅、金、鎳或是其他導電材料所構成的多層結構。
晶片120的背面BS貼於導電層112上，且導電邊框114環繞晶片120。在一實施例中，晶片120的背面BS上有黏著層126，晶片120藉由黏著層126而黏在導電層112上。
請參考圖1D，形成絕緣封裝體130以包覆晶片120。在一實施例中，絕緣封裝體130可藉由模塑製程形成於載板100上， 絕緣封裝體130的材料例如是環氧樹脂(Epoxy)或其他合適的高分子材料。在一實施例中，絕緣封裝體130中還包括填充物，填充物的材料例如是二氧化矽、氧化鋁或其他合適的材料，填充物能增強絕緣封裝體130的機械強度，以提升絕緣封裝體130保護晶片120的能力。絕緣封裝體130的高度例如高於晶片120與導電邊框114的高度，並包覆晶片120的主動表面AS。
接著請參考圖1E，對絕緣封裝體130進行研磨製程，以移除部分的絕緣封裝體130直到暴露出晶片120的主動表面AS。進行研磨製程的方法包括機械研磨(Mechanical grinding)、化學機械研磨(Chemical-Mechanical Polishing，CMP)、蝕刻或其他合適的製程。在一實施例中，對晶片120進行研磨製程以進一步減薄封裝結構的整體厚度。在其他實施例中，導電邊框114的厚度等於晶片120的厚度。在一實施例中，對絕緣封裝體130進行研磨製程時還會移除部分的導電邊框114，進一步減低封裝結構的厚度。在一實施例中，在研磨製程以後，晶片120的導電凸塊124、導電邊框114的第一面B以及絕緣封裝體130共平面。在一實施例中，由於晶片120的背面BS上具有黏著層126，因此研磨後的導電邊框114在其延伸方向上的厚度等於研磨後的晶片120的厚度加上黏著層126的厚度。
請參考圖1F，於晶片120的主動表面AS上形成重新佈線層140，重新佈線層140從晶片120的主動表面AS上往絕緣封裝體130及導電邊框114的第一面B上延伸。在一實施例中，部 分接墊142A會與導電邊框114電性連接，且兩者電性連接至相同的電壓(例如接地電壓或是外部電源提供的電壓)，然而本發明不以此為限。在其他實施例中，導電邊框114與接墊142A分離，然而導電邊框114可不接電壓。在一實施例中，重新佈線層140包括導線層144、接墊142A以及接墊142B。接墊142A靠近絕緣封裝體130，而接墊142B相較於接墊142A更遠離絕緣封裝體130。接墊142B通過導線層144而與接墊142A電性連接。在本實施例中，導線層144、接墊142A以及接墊142B被數層介電層包覆。重新佈線層140的部分接墊142A會與晶片120的導電凸塊124電性連接。
圖1F雖然繪示出一層導線層，然而本發明不以此為限。在一些實施例中，導線層的層數可依需求而進行調整，且介電層中還可以具有接觸窗，接墊與接觸窗的數目也可以依需求而進行調整。
接著請參考圖1G，移除載板100。在本實施例中，導電盒110、晶片120、絕緣封裝體130以及重新佈線層140都是在載板100上形成，不需要轉移到其他的載板，使製程更簡單，能節省製造成本。
請參考圖1H，於重新佈線層140上形成多個導電球150。導電球150與重新佈線層140的接墊142B電性連接。導電球150對應接墊142B設置，且導電球150透過重新佈線層140而與晶片120電性連接。在一些實施例中，導電球150例如包括錫球，然而 本發明不限於此。呈現其他形狀或材料的導電結構亦可以做為導電球150。舉例來說，在其他實施例中，導電球150是導電柱或是導電凸塊。在一些實施例中，導電球150可以藉由例如植球以及回銲製程形成。在本實施例中，先移除載板100接著才形成多個導電球150，然而本發明不以此為限。在其他實施例中，先形成多個導電球150接著才移除載板100。進行單分製程，以將多個封裝結構10分離。單分製程例如是沿著切線D而將相鄰的封裝結構10分開。在本實施例中，單分製程例如是沿著切線D而將相鄰的晶片120分離。
請參考圖1I，本實施例的封裝結構10包括導電盒110、晶片120、絕緣封裝體130、重新佈線層140以及導電球150。導電盒110包括導電層112和導電邊框114，導電盒110能減輕晶片120所受到的電磁干擾。本發明封裝結構10中的導電盒110、晶片120、絕緣封裝體130以及重新佈線層140都是在載板100上形成，不需要轉移到其他的載板，使製程更簡單，能節省製造成本。
圖2是依照本發明的一實施例的一種封裝結構的剖面示意圖。在此必須說明的是，圖2的實施例沿用圖1A~圖1I的實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。
圖2的封裝結構20與圖1A~圖1I的封裝結構10的差異在於：圖2的封裝結構20還包括保護膜160。
請參考圖2，導電層112包括第一面與相對於第一面的第二面，導電層112的第一面面對晶片120，保護膜160形成於導電層112的第二面上。在一實施例中，保護膜160的材料與絕緣封裝體130的材料相同。在一實施例中，對保護膜160進行圖案化以形成符號。
圖3是依照本發明的一實施例的一種封裝結構的剖面示意圖。在此必須說明的是，圖3的實施例沿用圖1A~圖1I的實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。
圖3的封裝結構30與圖1A~圖1I的封裝結構10的差異在於：圖3的封裝結構30包含兩個以上的晶片120，而圖1I的封裝結構10只包含一個晶片。
在封裝結構30中，導電盒110A還包括導電邊框114B，導電邊框114B隔開每一個晶片120，導電邊框114A環繞晶片120的外側。在一實施例中，導電邊框114B與導電邊框114A是同時形成的。在一實施例中，導電邊框114B、導電邊框114A以及金屬層112連成一體。
圖4A~圖4I是依照本發明的一實施例的一種封裝結構的製造方法的剖面示意圖。在此必須說明的是，圖4A~圖4H的實施例沿用圖1A~圖1I的實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的 說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。
請參考圖4A，於載板100上形成重新佈線層240。在一實施例中，重新佈線層240包括導線層244、接墊242A以及接墊242B。接墊242B靠近載板100，而接墊242A相較於接墊242B更遠離載板。接墊242B通過導線層244而與接墊242A電性連接。在本實施例中，導線層244、接墊242A以及接墊242B被數層介電層包覆。
接著請參考圖4B，於重新佈線層240上形成導電邊框114，導電邊框114的第一面B與重新佈線層240連接。在一實施例中，部分接墊242A會與導電邊框114電性連接，然而本發明不以此為限。在其他實施例中，導電邊框114與接墊242A分離。
再來請參考圖4C，將晶片220設置於重新佈線層240上，晶片220包括主動表面AS以及相對於主動表面AS的背面BS，晶片220的主動表面AS電性連接重新佈線層240，導電邊框114環繞晶片220。在一實施例中，晶片220的主動表面AS上包括晶片接墊222以及導電凸塊224。導電凸塊224與晶片接墊222電性連接，導電凸塊224的材料包括銅、錫、金、鎳或其他導電材料。舉例來說，導電凸塊224可以是銅、金、鎳或是其他導電材料所構成的單層結構，也可以是銅、金、鎳或是其他導電材料所構成的多層結構。
請參考圖4D，形成絕緣封裝體130以包覆晶片120。在 一實施例中，形成絕緣封裝體130的方法例如包括模塑製程。
接著請參考圖4E，對絕緣封裝體130進行研磨製程，以移除部分的絕緣封裝體130直到暴露出導電邊框114的第二面T。進行研磨製程的方法包括機械研磨(Mechanical grinding)、化學機械研磨(Chemical-Mechanical Polishing，CMP)、蝕刻或其他合適的製程。在本實施例中，導電邊框114的延伸方向垂直於載板100，導電邊框114在延伸方向上的厚度大於晶片220的厚度，因此絕緣封裝體130暴露出導電邊框114的第二面T時，不會研磨到晶片220。在一些實施例中，在導電邊框114被暴露出之後，可以繼續研磨導電邊框114以進一步減薄封裝結構的整體厚度。在一實施例中，研磨絕緣封裝體130直到暴露出晶片220的背面BS。在一實施例中，研磨晶片220的背面BS以進一步減少晶片220的厚度。由於是研磨晶片220的背面BS，因此，位於晶片220主動表面AS上的線路不會在研磨的過程中受到傷害。在一實施例中，導電邊框114在延伸方向上的厚度等於晶片220的厚度，因此絕緣封裝體130暴露出導電邊框114的第二面T時，也會同時暴露出晶片220的背面BS。
再來請參考圖4F，於絕緣封裝體130上形成導電層112，導電邊框114的第二面T連接導電層112。在一實施例中，導電邊框114與導電層112連成一體並組成導電盒110，導電盒110覆蓋晶片220除了主動表面AS以外的所有表面。在一實施例中，形成導電層112的方法包括物理氣相沉積法。在一實施例中，形成導 電層112的方法包括電鍍。導電層112的材料例如包括銅、錫、鋁、鋼或其他合適的金屬。在一實施例中，晶片220與導電層112之間夾有絕緣封裝體130，然而本發明不以此為限。在其他實施例中，晶片220的背面BS會與導電層112接觸，因此晶片可以直接透過導電層112來散熱。
接著請參考圖4G，移除載板100。在本實施例中，導電盒110、晶片220、絕緣封裝體130以及重新佈線層240都是在載板100上形成，不需要轉移到其他的載板，使製程更簡單，能節省製造成本。
請參考圖4H，於重新佈線層240上形成多個導電球150，且重新佈線層240位於導電球150以及晶片220之間。導電球150與重新佈線層240的接墊242B電性連接。進行單分製程，以將多個封裝結構40分離。單分製程例如是沿著切線D而將相鄰的封裝結構40分開。在本實施例中，單分製程例如是沿著切線D而將相鄰的晶片220分離，然而本發明不以此為限。在一些實施例中，每個封裝結構中包括有多個晶片220，且封裝結構中的晶片220被導電框架所隔開。
請參考圖4I，本實施例的封裝結構40包括導電盒110、晶片220、絕緣封裝體130、重新佈線層240以及導電球150。導電盒110包括導電層112和導電邊框114，導電盒110能減輕晶片220所受到的電磁干擾。本發明封裝結構40中的導電盒110、晶片220、絕緣封裝體130以及重新佈線層240都是在載板100上形 成，不需要轉移到其他的載板，使製程更簡單，能節省製造成本。
綜上所述，本發明的封裝結構包括有導電盒，導電盒能減輕晶片所受到的電磁干擾。本發明封裝結構中的大部分製程都是在同一個載板上進行，使製程更簡單，能節省製造成本。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。

Claims (9)

  1. 一種封裝結構的製造方法，包括：提供載板；於所述載板上形成導電層；於所述導電層上形成導電邊框，其中所述導電邊框與所述導電層連成一體並組成導電盒；將至少一晶片置於所述導電層上，所述晶片包括主動表面以及相對於所述主動表面的背面，所述背面貼於所述導電層上，所述導電邊框環繞所述晶片；形成絕緣封裝體以包覆所述晶片，所述絕緣封裝體露出所述晶片的所述主動表面；以及於所述晶片的所述主動表面上形成重新佈線層，所述重新佈線層從所述主動表面上往所述絕緣封裝體上延伸。
  2. 如申請專利範圍第1項所述的封裝結構的製造方法，其中所述導電邊框電性連接所述重新佈線層。
  3. 如申請專利範圍第1項所述的封裝結構的製造方法，其中所述封裝結構包括兩個以上的所述晶片，其中所述導電邊框隔開每一所述多個晶片。
  4. 如申請專利範圍第1項所述的封裝結構的製造方法，更包括：於所述晶片的所述背面形成黏著層。
  5. 如申請專利範圍第1項所述的封裝結構的製造方法，其中所述導電層包括第一面與相對於所述第一面的第二面，所述第一面面對所述晶片，且所述封裝結構的製造方法更包括：於所述導電層的所述第二面形成保護膜。
  6. 一種封裝結構的製造方法，包括：提供載板；於所述載板上形成重新佈線層；於所述重新佈線層上形成導電邊框；將多個晶片置於所述重新佈線層上，每一所述多個晶片包括主動表面以及相對於所述主動表面的背面，每一所述多個晶片的所述主動表面電性連接所述重新佈線層，所述導電邊框環繞所述多個晶片；形成絕緣封裝體以包覆所述多個晶片；以及於所述絕緣封裝體上形成導電層，其中所述導電邊框與所述導電層連成一體並組成導電盒，所述導電邊框電性連接所述重新佈線層。
  7. 如申請專利範圍第6項所述的封裝結構的製造方法，更包括：分割所述絕緣封裝體以將所述多個晶片分離，且每一所述封裝結構包括兩個以上的所述晶片。
  8. 如申請專利範圍第6項所述的封裝結構的製造方法，其中所述導電邊框隔開每一所述多個晶片。
  9. 如申請專利範圍第6項所述的封裝結構的製造方法，其中每一所述多個晶片包括位於所述主動表面上的多個晶片接墊，以及位於所述多個晶片接墊上的多個導電凸塊。
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