TW201314755A - 積體電路結構及其製造方法 - Google Patents

積體電路結構及其製造方法 Download PDF

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TW201314755A
TW201314755A TW101110510A TW101110510A TW201314755A TW 201314755 A TW201314755 A TW 201314755A TW 101110510 A TW101110510 A TW 101110510A TW 101110510 A TW101110510 A TW 101110510A TW 201314755 A TW201314755 A TW 201314755A
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wafer
layer
integrated circuit
circuit structure
forming
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TW101110510A
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TWI482215B (zh
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Jing-Cheng Lin
Weng-Jin Wu
Ying-Ching Shih
Jui-Pin Hung
Szu-Wei Lu
Shin-Puu Jeng
Chen-Hua Yu
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Taiwan Semiconductor Mfg
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Abstract

本發明揭示一種積體電路結構之製造方法。提供一晶圓疊層，其中複數個半導體晶粒設置於一第一半導體晶粒上。在第一半導體晶粒的一第一側上形成一成型材料層，其中半導體晶粒埋設於成型材料層內。上述方法更包括對第一半導體晶粒的一第二側進行研磨，直到露出複數個通孔電極。將晶圓疊層貼附於一帶框。切割晶圓疊層，以將晶圓疊層分割成複數個單獨的封裝體。本發明揭示一種積體電路結構。

Description

積體電路結構及其製造方法
本發明係有關於一種積體電路(integrated circuit,IC)，特別是有關於一種積體電路結構及其製造方法。
隨著積體電路(IC)的發展，使半導體業由於各個電子部件(即，電晶體、二極體、電阻、電容等等)的集積度(integration density)持續的改進而持續不斷的快速成長發展。主要來說，集積度的改進來自於縮小半導體製程節點(例如，將製程節點(process node)往次20奈米(nm)節點縮小)不斷縮小而容許更多的部件整合至既有的晶片面積內。近期隨著微縮化(miniaturization)、高速、大頻寬、低耗能及潛在因素的需求成長，因而需要發展更小更具創新的半導體晶片封裝技術。
隨著半導體技術逐漸發展，多重晶片晶圓級封裝的半導體裝置已成為進一步縮減半導體晶片實際尺寸有效的選擇。在晶圓級封裝的半導體裝置裝，主動電路(例如，邏輯、記憶體、微處理器電路等等)製做於不同的晶圓上，且每一晶粒(wafer die)利用拾放(pick-and-place)技術而疊置於另一晶粒的頂部。利用多重晶片半導體裝置可達成高出許多的集積度。再者，多重晶片半導體裝置可達成較小的形狀因素及成本效益、效能增進及低耗能。
三維(three-dimensional,3D)積體電路(IC)可包括一上主動(active)電路層、一下主動電路層及複數個內層。在3DIC中，二個晶粒可透過複數個微凸塊(micro bump)而接合在一起，且透過複數個基底通孔電極(through-substrate via)而彼此電性耦接。微凸塊及基底通孔電極提供了3DIC在垂直軸上的電性內連接。如此一來，二個半導體晶粒之間的信號路徑短於傳統的3DIC(其中不同的晶粒係使用內連技術而接合在一起，例如打線接合的晶片接合封裝)。3DIC可包括各種堆疊的半導體晶粒。多重的半導體晶粒在切割晶圓之前進行封裝。晶圓級封裝技術具有某些優點。晶圓級封裝多重半導體晶粒的優點特徵在於晶圓級封裝技術可降低製造成本。另一晶圓級封裝多重半導體晶粒的優點特徵在於利用微凸塊及基底通孔電極來降低寄生損失。
在本發明一實施例中，一種積體電路結構之製造方法包括：提供一疊層，其中複數個半導體晶粒設置於一晶圓的一第一側上；在晶圓的第一側上形成一成型材料層，其中半導體晶粒埋設於成型材料層內；對晶圓的一第二側進行薄化，直到露出複數個通孔電極；將疊層貼附於一帶框；以及切割疊層，以將疊層分割成複數個單獨的封裝體。
在本發明另一實施例中，一種積體電路結構之製造方法包括：提供一疊層，其中複數個半導體晶粒設置於一晶圓的一第一側上，且其中晶圓包括複數個通孔電極；在晶圓的第一側上形成一成型材料層，其中半導體晶粒埋設於成型材料層內；延伸成型材料層，以覆蓋晶圓的一外側邊緣；對晶圓的一第二側進行薄化，直到露出通孔電極；將疊層貼附於一帶框；以及切割疊層，以將疊層分割成複數個單獨的封裝體。
在本發明又一實施例中，一種積體電路結構包括：一基底；以及一疊層，設置於基底上，其包括：複數個半導體晶粒，接合於一晶粒的一第一側；以及一成型材料層，形成於該晶粒的第一側上，且覆蓋該晶粒的一外側邊緣，其中該等半導體晶粒埋設於成型材料層內。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
本文將以特定背景中實施例之一種三維積體電路(3DIC)之製造方法來進行說明。然而，本說明也可實施於各種積體電路之半導體製造。
第1至5圖係繪示出根據本發明一實施例之三維積體電路(3DIC)結構之製造方法剖面示意圖。一晶圓疊層100包括一晶圓102及複數個半導體晶粒(die)，其設置於晶圓102的頂部。在一實施例中，晶圓102為一矽晶圓。如第1圖所示，上述半導體晶利可包括一第一半導體晶粒154、一第二半導體晶粒156、一第三半導體晶粒164及一第四半導體晶粒166。晶圓102可為一標準晶圓，其厚度大於100微米(μm)。在一實施例中，晶圓102的厚度約為770微米。晶圓102可包括複數個積體電路(未繪示)，每一積體電路可包括不同的膜層，例如主動(active)電路層、基底層、內層介電(inter-layer dielectric,ILD)層及金屬層間介電(inter-metal dielectric,IMD)層。晶圓102更包括複數個微凸塊(micro bump)134形成於晶圓102與上述半導體晶粒(例如，第一半導體晶粒154)之間。再者，可透過形成於晶圓102的頂部上的一重佈線層(redistribution layer)132來進行上述微凸塊134的重佈連接。
晶圓102更包括複數個通孔電極。在一些實施例中，通孔電極為基底通孔電極(through-substrate via,TSV)或矽通孔電極(through-silicon via,TSV)，例如基底通孔電極112、114、116、118、122、124、126及128。晶圓102的主動電路層(未繪示)可耦接至微凸塊134及/或一或一個以上的基底通孔電極(例如，基底通孔電極112)。主動電路層透過微凸塊134而進一步連接至第一半導體晶粒154、一第二半導體晶粒156、一第三半導體晶粒164及一第四半導體晶粒166。
一底膠(underfill)材料層152可形成於晶圓102與設置於其頂部的半導體晶粒(例如，第一半導體晶粒154)之間的間隙。在一實施例中，底膠材料層152可為環氧化物，其塗覆於晶圓102與第一半導體晶粒154之間的間隙。環氧化物可為液態且在進行固化製程之後硬化。在另一實施例中，底膠材料層152可由可固化材料所構成，例如高分子材料、樹脂材料、聚醯亞胺(polyimide)、環氧化物或其任何組合。底膠材料層152可透過旋轉塗佈(spin-on coating)製程、乾膜貼合(dry film lamination)製程等等而形成。具有底膠材料層(例如，底膠材料層152)的優點在於底膠材料層152有助於防止微凸塊134發生破裂。再者，底膠材料層152有助於在晶圓疊層100的製造期間，降低機械及熱應力。
第2圖係繪示出形成於晶圓102頂部上且具有成型材料層的三維積體電路(3DIC)結構剖面示意圖。如第2圖所示，第一半導體晶粒154、一第二半導體晶粒156、一第三半導體晶粒164及一第四半導體晶粒166埋設於成型材料層202內。成型材料層202可由可固化材料所構成，例如高分子材料、樹脂材料、聚醯亞胺、環氧化物或其任何組合。成型材料層202可透過旋轉塗佈製程、射出成型(injection molding)製程等等而形成。為了在製程期間(例如，將晶圓102切割成分開的晶片封裝體)可靠地處置晶圓102及設置於晶圓102的頂部上的半導體晶粒(例如，第一半導體晶粒154)，採用成型材料層202來防止晶圓102及位於晶圓102的頂部上的半導體晶粒發生破裂、彎曲、撓曲等等。
第3圖係繪示出背側研磨製程。在進行晶圓疊層100貼合至帶框(tape flame)400的製程之後，對晶圓102的背側進行薄化製程。薄化製程可包括機械研磨製程、化學研磨製程及蝕刻製程等等。透過薄化製程，晶圓102的背側可進行研磨，使晶圓102的厚度接近100微米以下。在一實施例中，晶圓102的厚度可降至20微米至50微米的範圍。需注意的是透過研磨晶圓102至厚度為20微米時，此薄晶圓可具有小的接觸窗(via)特徵尺寸(feature size)，例如接觸窗的直徑及深度。形成小的基底通孔電極的優點在於晶圓疊層100的效能及功率消耗可進一步獲得改善。
另外，晶圓102的厚度可研磨至露出埋設的基底通孔電極(例如，基底通孔電極112)的端點。隨後，在研磨後的晶圓102新的背側頂部上形成一重佈線層304。再者，在這些基底通孔電極的露出端點頂部上形成複數個凸塊302。需注意的是凸塊302可不形成於基底通孔電極的露出端點上，且透過重佈線層304而與基底通孔電極(例如，基底通孔電極116)重新連接。
第4圖係繪示出晶圓疊層100貼合至帶框(tape flame)400的製程。晶圓100設置於帶框400上。帶框400可包括一載板，其上塗覆了臨時黏著層。可在一反應室內進行接合製程，其中晶圓疊層100接合至帶框400上。晶圓疊層100貼附至帶框的接合製程屬習知技術，在此不再予以贅述。
第4圖更繪示出使用切割製程將晶圓疊層100分割成複數個單獨封裝體之製程。如第4圖所示，複數個封裝體，例如第一封裝體402及第二封裝體404，透過切割晶圓疊層100成複數個單獨封裝體而形成。每一單獨的封裝體可包括至少一半導體晶粒，其接合至一晶粒(例如，晶粒102a)。切割製程為習知技術，在此不再詳細說明。需注意的是雖然第4圖繪示出在晶圓疊層100中具有複數個半導體晶粒的一側(相對於覆晶凸塊側)係貼附至帶框400，接著進行切割製程，然而熟習此技藝之人士可知本說明的實施例可有許多變化。舉例來說，晶圓疊層100的覆晶凸塊側可貼附至帶框400。也可在晶圓疊層100中的半導體晶粒側進行切割製程。
第5圖係繪示出進行切割製程之後的三維積體電路剖面示意圖。如第5圖所示，封裝體402及404(未繪示，但繪示於第4圖)已利用拾放(pick-and-place)製程而自帶框400(未繪示)移出。拾放製程為習知技術，在此為了避免重複而不再詳細說明。第一封裝體402及第二封裝體404兩者的表面可透過化學溶劑來進一步研磨，接著再一次翻轉。隨後，單獨的封裝體，例如第一封裝體402，設置於一基底502上，以形成三維積體電路。在一實施例中，基底502可為有機基底。再者，為了降低機械及熱應力，在第一封裝體402與基底502之間的間隙內形成一底膠材料層504。
第6至10圖係繪示出根據本發明另一實施例之三維積體電路結構之製造方法剖面示意圖。第6至10圖相似於第1至5圖，除了第7圖中的成型材料層702延伸覆蓋晶圓102的邊緣。為了在製程步驟(例如，將晶圓疊層100切割成分開的晶片封裝體)期間，保護晶圓102的邊緣，因此利用成型材料層702來防止邊緣發生破裂。成型材料層702的形成方法相似於形成成型材料層202的方法，在此為了避免不必要的重複而不再詳細說明。晶圓102的背側研磨、將晶圓疊層100貼附於帶框400以及將晶圓疊層100切割成複數個單獨的封裝體等製程步驟已敘述於第3至5圖的說明中，在此為了避免重複而不再提出說明。
第11至15圖係繪示出根據本發明又一實施例之三維積體電路結構之製造方法剖面示意圖。第11至15圖相似於第1至5圖，除了一額外的保護材料層1202形成於成型材料層202的邊緣與晶圓102的邊緣之間。為了在製程步驟(例如，將晶圓疊層100切割成分開的晶片封裝體)期間，保護晶圓102的邊緣，因此利用保護材料層1202來防止邊緣發生破裂。另外，額外的保護材料層1202係用以提供一緩衝區，以在製造三維積體電路期間，吸收機械及熱應力。額外的保護材料層1202可透過在成型材料層202的邊緣與晶圓102的邊緣之間塗覆(dispensing)、貼合(lamination)及/或印刷額外的保護材料而形成。在一實施例中，保護材料層1202可為一高分子材料，例如，聚醯亞胺、環氧化物等等。晶圓102的背側研磨、將晶圓疊層100貼附於帶框400以及將晶圓疊層100切割成複數個單獨的封裝體等製程步驟已敘述於第3至5圖的說明中，在此為了避免重複而不再提出說明。
根據一實施例，一種積體電路結構之製造方法包括：提供一晶圓疊層，其中複數個半導體晶粒設置於一第一半導體晶粒上；在第一半導體晶粒的一第一側上形成一成型材料層，其中半導體晶粒埋設於成型材料層內。上述方法更包括：對第一半導體晶粒的一第二側進行薄化，直到露出複數個通孔電極；將晶圓疊層貼附於一帶框；以及切割晶圓疊層，以將晶圓疊層分割成複數個單獨的封裝體。
根據另一實施例中，一種積體電路結構之製造方法包括：提供一晶圓疊層，其中複數個半導體晶粒設置於一第一半導體晶粒的一第一側上；在第一半導體晶粒的第一側上形成一成型材料層，其中半導體晶粒埋設於成型材料層內；延伸成型材料層，以覆蓋第一半導體晶粒的一外側邊緣。上述方法更包括對第一半導體晶粒的一第二側進行薄化，直到露出複數個通孔電極；將晶圓疊層貼附於一帶框；以及切割晶圓疊層，以將晶圓疊層分割成複數個單獨的封裝體。
根據又另一實施例中，一種積體電路結構包括：一基底層；以及一第一半導體晶粒，設置於基底層上。第一半導體晶粒包括：複數個凸塊，位於第一半導體晶粒的一第一側上；複數個微凸塊，位於第一半導體晶粒的一第二側上；以及一重佈線層，形成於第一半導體晶粒的第二側的頂部上。上述結構更包括複數個半導體晶粒，設置於第一半導體晶粒的第二側的頂部。
雖然本發明實施例及其優點已詳細揭露如上，然而可以理解的是其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。
再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。
100．．．晶圓疊層
102．．．晶圓
102a．．．晶粒
112、114、116、118、122、124、126、128．．．基底通孔電極/矽通孔電極
132、304．．．重佈線層
134．．．微凸塊
152、504．．．底膠材料層
154．．．第一半導體晶粒
156．．．第二半導體晶粒
164．．．第三半導體晶粒
166．．．第四半導體晶粒
202、702．．．成型材料層
302．．．凸塊
402．．．第一封裝體
404．．．第二封裝體
502．．．基底
1202．．．保護材料層
第1至5圖係分別繪示出根據本發明一實施例之三維(3D)積體電路(IC)結構之製造方法剖面示意圖；
第6至10圖係分別繪示出根據本發明另一實施例之三維積體電路結構之製造方法剖面示意圖；以及
第11至15圖係分別繪示出根據本發明又一實施例之三維積體電路結構之製造方法剖面示意圖。
102a．．．晶粒
112、114、116、118．．．基底通孔電極/矽通孔電極
154．．．第一半導體晶粒
156．．．第二半導體晶粒
202．．．成型材料層
302．．．凸塊
502．．．基底
504．．．底膠材料層

Claims (10)

  1. 一種積體電路結構之製造方法，包括：提供一疊層，其中複數個半導體晶粒設置於一晶圓的一第一側上；在該晶圓的該第一側上形成一成型材料層，其中該等半導體晶粒埋設於該成型材料層內；對該晶圓的一第二側進行薄化，直到露出複數個通孔電極；將該疊層貼附於一帶框；以及切割該疊層，以將該疊層分割成複數個單獨的封裝體。
  2. 如申請專利範圍第1項所述之積體電路結構之製造方法，更包括：在該晶圓內形成該等通孔電極；在該晶圓的該第一側上形成複數個第一凸塊；以及在該晶圓的該第一側上形成一第一重佈線層，其中該等半導體晶粒透過該等第一凸塊及該第一重佈線層而連接至該晶圓。
  3. 如申請專利範圍第1項所述之積體電路結構之製造方法，更包括：在該晶圓的該第二側上形成複數個第二凸塊；以及在該晶圓的該第二側上形成一第二重佈線層。
  4. 如申請專利範圍第1項所述之積體電路結構之製造方法，更包括：在該成型材料的一外側邊緣與該疊層的一外側邊緣之間形成一保護層。
  5. 一種積體電路結構之製造方法，包括：提供一疊層，其中複數個半導體晶粒設置於一晶圓的一第一側上，且其中該晶圓包括複數個通孔電極；在該晶圓的該第一側上形成一成型材料層，其中該等半導體晶粒埋設於該成型材料層內；延伸該成型材料層，以覆蓋該晶圓的一外側邊緣；對該晶圓的一第二側進行薄化，直到露出該等通孔電極；將該疊層貼附於一帶框；以及切割該疊層，以將該疊層分割成複數個單獨的封裝體。
  6. 如申請專利範圍第5項所述之積體電路結構之製造方法，更包括：自該帶框拆離每一單獨的封裝體；將該單獨的封裝體貼附於一基底上；在該晶圓與該等半導體晶粒之間形成一第一底膠材料層；以及在該單獨的封裝體與該基底之間形成一第二底膠材料層。
  7. 如申請專利範圍第5項所述之積體電路結構之製造方法，更包括：化學研磨該晶圓的該第二側；在該晶圓的該第二側上形成一第二重佈線層；在該晶圓的該第二側上形成複數個第二凸塊；在該晶圓的該第一側上形成一第一重佈線層；以及形成複數個第一凸塊，以電性耦接該晶圓的該第一側上的該第一重佈線層。
  8. 一種積體電路結構，包括：一基底；以及一疊層，設置於該基底上，包括：複數個半導體晶粒，接合於一晶粒的一第一側；以及一成型材料層，形成於該晶粒的該第一側上，且覆蓋該晶粒的一外側邊緣，其中該等半導體晶粒埋設於該成型材料層內。
  9. 如申請專利範圍第8項所述之積體電路結構，更包括複數個凸塊，形成於該基底與該疊層之間。
  10. 如申請專利範圍第8項所述之積體電路結構，更包括：一第一底膠材料，形成於該等半導體晶粒與該晶粒之間；以及一第二底膠材料層形成於該晶粒與該基底之間。
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