CN100413044C - 晶圆级芯片尺寸封装的填胶结构及其方法 - Google Patents
晶圆级芯片尺寸封装的填胶结构及其方法 Download PDFInfo
- Publication number
- CN100413044C CN100413044C CNB200510068973XA CN200510068973A CN100413044C CN 100413044 C CN100413044 C CN 100413044C CN B200510068973X A CNB200510068973X A CN B200510068973XA CN 200510068973 A CN200510068973 A CN 200510068973A CN 100413044 C CN100413044 C CN 100413044C
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- Prior art keywords
- glued membrane
- mentioned
- crystal grain
- filler structure
- film
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 65
- 239000000463 material Substances 0.000 claims abstract description 25
- 239000003292 glue Substances 0.000 claims abstract description 19
- 239000013078 crystal Substances 0.000 claims description 53
- 239000000945 filler Substances 0.000 claims description 49
- 239000012528 membrane Substances 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 28
- 238000005538 encapsulation Methods 0.000 claims description 24
- 229920002379 silicone rubber Polymers 0.000 claims description 18
- 238000005266 casting Methods 0.000 claims description 13
- 229920001296 polysiloxane Polymers 0.000 claims description 13
- 238000007639 printing Methods 0.000 claims description 13
- 229920000800 acrylic rubber Polymers 0.000 claims description 12
- 229920000058 polyacrylate Polymers 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 11
- 239000013536 elastomeric material Substances 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- 150000001875 compounds Chemical class 0.000 claims description 9
- 239000010453 quartz Substances 0.000 claims description 8
- 239000004593 Epoxy Substances 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 239000000919 ceramic Substances 0.000 claims description 3
- 239000012530 fluid Substances 0.000 claims description 3
- 239000000565 sealant Substances 0.000 claims description 3
- 238000012856 packing Methods 0.000 claims 4
- 239000000853 adhesive Substances 0.000 abstract 2
- 230000001070 adhesive effect Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 17
- 239000004065 semiconductor Substances 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000004945 silicone rubber Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01094—Plutonium [Pu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Adhesives Or Adhesive Processes (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Die Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/026,488 | 2004-12-30 | ||
US11/026,488 US7400037B2 (en) | 2004-12-30 | 2004-12-30 | Packaging structure with coplanar filling paste and dice and with patterned glue for WL-CSP |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1797728A CN1797728A (zh) | 2006-07-05 |
CN100413044C true CN100413044C (zh) | 2008-08-20 |
Family
ID=36639496
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB200510068973XA Active CN100413044C (zh) | 2004-12-30 | 2005-04-27 | 晶圆级芯片尺寸封装的填胶结构及其方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US7400037B2 (zh) |
JP (1) | JP2006190975A (zh) |
KR (1) | KR100693664B1 (zh) |
CN (1) | CN100413044C (zh) |
DE (1) | DE102005019553B4 (zh) |
SG (1) | SG123653A1 (zh) |
TW (1) | TWI302731B (zh) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8999736B2 (en) * | 2003-07-04 | 2015-04-07 | Epistar Corporation | Optoelectronic system |
TW200807526A (en) * | 2006-07-27 | 2008-02-01 | Touch Micro System Tech | Method of wafer segmenting |
US7830004B2 (en) * | 2006-10-27 | 2010-11-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging with base layers comprising alloy 42 |
KR100826393B1 (ko) | 2007-05-22 | 2008-05-02 | 삼성전기주식회사 | 전도성 패턴을 갖는 실링 라인으로 구비된 웨이퍼 레벨디바이스 패키지 및 그 패키징 방법 |
US20090079064A1 (en) * | 2007-09-25 | 2009-03-26 | Jiamiao Tang | Methods of forming a thin tim coreless high density bump-less package and structures formed thereby |
CN100595897C (zh) | 2008-08-20 | 2010-03-24 | 晶方半导体科技(苏州)有限公司 | 晶圆级封装对象及其形成的方法 |
JP5389490B2 (ja) * | 2009-03-23 | 2014-01-15 | 東京エレクトロン株式会社 | 三次元集積回路の製造方法及び装置 |
CN103199023A (zh) * | 2009-08-17 | 2013-07-10 | 晶元光电股份有限公司 | 系统级光电结构及其制作方法 |
CN102376590B (zh) * | 2010-08-05 | 2013-11-27 | 矽品精密工业股份有限公司 | 芯片尺寸封装件及其制法 |
TW201331984A (zh) * | 2012-01-31 | 2013-08-01 | Chenming Mold Ind Corp | Ic屏蔽膜層及其製程方法 |
US9768038B2 (en) | 2013-12-23 | 2017-09-19 | STATS ChipPAC, Pte. Ltd. | Semiconductor device and method of making embedded wafer level chip scale packages |
CN105390403B (zh) * | 2015-10-13 | 2017-10-20 | 中国电子科技集团公司第五十四研究所 | 一种ltcc厚薄膜混合基板制造中的基板腔体填充方法 |
CN105568329A (zh) * | 2016-02-23 | 2016-05-11 | 河源市众拓光电科技有限公司 | 一种在led外延片上电镀铜的方法 |
JP6598723B2 (ja) * | 2016-04-06 | 2019-10-30 | 株式会社ディスコ | パッケージウェーハの製造方法 |
CN107393840A (zh) * | 2017-06-15 | 2017-11-24 | 江苏长电科技股份有限公司 | 一种陶瓷基板封装的切割方法 |
CN107738135A (zh) * | 2017-11-24 | 2018-02-27 | 深圳市精品诚电子科技有限公司 | 镜片加工排屑的方法 |
WO2020132801A1 (zh) * | 2018-12-24 | 2020-07-02 | 深圳市柔宇科技有限公司 | 电子器件及其制作方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002134638A (ja) * | 2000-10-27 | 2002-05-10 | Kyocera Corp | 光半導体素子収納用パッケージ |
US6387728B1 (en) * | 1999-11-09 | 2002-05-14 | Advanced Semiconductor Engineering, Inc. | Method for fabricating a stacked chip package |
US6429045B1 (en) * | 2001-02-07 | 2002-08-06 | International Business Machines Corporation | Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage |
US20020192927A1 (en) * | 1999-01-19 | 2002-12-19 | Fujitsu Limited | Semiconductor device production method and apparatus |
US6627477B1 (en) * | 2000-09-07 | 2003-09-30 | International Business Machines Corporation | Method of assembling a plurality of semiconductor devices having different thickness |
CN1464540A (zh) * | 2002-06-26 | 2003-12-31 | 威宇科技测试封装(上海)有限公司 | 一种能提高多芯片封装合格率的封装方法 |
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DE2436600A1 (de) | 1974-07-30 | 1976-02-19 | Semikron Gleichrichterbau | Verfahren zur erzielung einer oberflaechenstabilisierenden schutzschicht bei halbleiterbauelementen |
JPS61188957A (ja) * | 1985-02-18 | 1986-08-22 | Toshiba Corp | 回路モジユ−ルの製造方法 |
US5353498A (en) | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US6130116A (en) | 1996-12-13 | 2000-10-10 | Tessera, Inc. | Method of encapsulating a microelectronic assembly utilizing a barrier |
US5953588A (en) | 1996-12-21 | 1999-09-14 | Irvine Sensors Corporation | Stackable layers containing encapsulated IC chips |
US6025638A (en) * | 1998-06-01 | 2000-02-15 | International Business Machines Corporation | Structure for precision multichip assembly |
JP2001044226A (ja) | 1999-07-27 | 2001-02-16 | Mitsubishi Electric Corp | 半導体装置の製造方法および半導体装置 |
JP2001313350A (ja) | 2000-04-28 | 2001-11-09 | Sony Corp | チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法 |
US6489185B1 (en) | 2000-09-13 | 2002-12-03 | Intel Corporation | Protective film for the fabrication of direct build-up layers on an encapsulated die package |
JP2002093830A (ja) * | 2000-09-14 | 2002-03-29 | Sony Corp | チップ状電子部品の製造方法、及びその製造に用いる疑似ウェーハの製造方法 |
JP5035580B2 (ja) * | 2001-06-28 | 2012-09-26 | ナガセケムテックス株式会社 | 弾性表面波デバイスおよびその製法 |
TW497236B (en) | 2001-08-27 | 2002-08-01 | Chipmos Technologies Inc | A soc packaging process |
JP2004063510A (ja) * | 2002-07-25 | 2004-02-26 | Sony Corp | 素子の転写方法 |
DE10234951B4 (de) | 2002-07-31 | 2009-01-02 | Qimonda Ag | Verfahren zur Herstellung von Halbleiterschaltungsmodulen |
US6965160B2 (en) | 2002-08-15 | 2005-11-15 | Micron Technology, Inc. | Semiconductor dice packages employing at least one redistribution layer |
US20050249945A1 (en) * | 2004-05-10 | 2005-11-10 | Wen Kun Yang | Manufacturing tool for wafer level package and method of placing dies |
-
2004
- 2004-12-30 US US11/026,488 patent/US7400037B2/en active Active
-
2005
- 2005-01-06 TW TW094100360A patent/TWI302731B/zh not_active IP Right Cessation
- 2005-04-11 SG SG200502825A patent/SG123653A1/en unknown
- 2005-04-27 CN CNB200510068973XA patent/CN100413044C/zh active Active
- 2005-04-27 DE DE102005019553A patent/DE102005019553B4/de active Active
- 2005-05-11 KR KR1020050039461A patent/KR100693664B1/ko active IP Right Grant
- 2005-10-24 JP JP2005308090A patent/JP2006190975A/ja active Pending
-
2007
- 2007-05-03 US US11/799,923 patent/US7476565B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020192927A1 (en) * | 1999-01-19 | 2002-12-19 | Fujitsu Limited | Semiconductor device production method and apparatus |
US6387728B1 (en) * | 1999-11-09 | 2002-05-14 | Advanced Semiconductor Engineering, Inc. | Method for fabricating a stacked chip package |
US6627477B1 (en) * | 2000-09-07 | 2003-09-30 | International Business Machines Corporation | Method of assembling a plurality of semiconductor devices having different thickness |
JP2002134638A (ja) * | 2000-10-27 | 2002-05-10 | Kyocera Corp | 光半導体素子収納用パッケージ |
US6429045B1 (en) * | 2001-02-07 | 2002-08-06 | International Business Machines Corporation | Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage |
CN1464540A (zh) * | 2002-06-26 | 2003-12-31 | 威宇科技测试封装(上海)有限公司 | 一种能提高多芯片封装合格率的封装方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20060079057A (ko) | 2006-07-05 |
DE102005019553B4 (de) | 2006-12-21 |
SG123653A1 (en) | 2006-07-26 |
TWI302731B (en) | 2008-11-01 |
TW200623350A (en) | 2006-07-01 |
JP2006190975A (ja) | 2006-07-20 |
KR100693664B1 (ko) | 2007-03-14 |
US7476565B2 (en) | 2009-01-13 |
CN1797728A (zh) | 2006-07-05 |
US7400037B2 (en) | 2008-07-15 |
US20060145364A1 (en) | 2006-07-06 |
US20080044945A1 (en) | 2008-02-21 |
DE102005019553A1 (de) | 2006-07-20 |
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