CN100413044C - 晶圆级芯片尺寸封装的填胶结构及其方法 - Google Patents

晶圆级芯片尺寸封装的填胶结构及其方法 Download PDF

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CN100413044C
CN100413044C CNB200510068973XA CN200510068973A CN100413044C CN 100413044 C CN100413044 C CN 100413044C CN B200510068973X A CNB200510068973X A CN B200510068973XA CN 200510068973 A CN200510068973 A CN 200510068973A CN 100413044 C CN100413044 C CN 100413044C
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杨文焜
杨锦成
邱政贤
孙文彬
赵匡祺
袁禧霙
余俊辉
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Abstract

本发明涉及一种晶圆级封装的填胶结构及其方法。上述方法包括将一黏性材料填满于复数个晶粒之间,并且覆盖上述复数个晶粒。上述复数个晶粒黏着于常态下具有黏性的胶膜图案上,并且形成于一可移除基板上。一相对刚性基板利用黏性材料的涂布以黏着上述晶粒。然后,于附着上述相对刚性基板之后,由一特殊环境将上述复数个晶粒从上述胶膜图案中分离。

Description

晶圆级芯片尺寸封装的填胶结构及其方法
技术领域
本发明是与一种晶圆级封装的填胶结构及其方法有关,特别是有关于一种利用正面朝下(top side face down)地填满胶使与晶粒表面平坦而不超过(overflowing)或凹陷(recessing)于上述晶粒表面的结构及其方法,用以增进填胶效果及提升可靠度测试中的使用寿命(life cycle)。
背景技术
一种具有球数组(Ball Grid Array,BGA)结构的半导体组件被发展以适用于高脚位数(high-pin-count)封装的半导体组件。在上述具有球数组结构的半导体组件中,一半导体芯片利用黏性材料黏着(mounted)于基板(base substrate)主表面上的一芯片刚性区域,数个凸块电极(bumpelectrodes)以一数组而置于上述基板背面上,其是在上述基板主表面的对面。
传统的芯片尺度封装(CSP)是利用一半导体晶圆切割成半导体芯片的方法形成,接着上述半导体芯片以一预定的位置而固定于一作为封装基底(package base)的基板上,并且以树脂将上述芯片密封,然后上述密封树脂与基板于上述半导体芯片之间的部分一起被切割。在另一传统的方法中,一半导体晶圆(尚未被切割成半导体芯片)附着于一基板上,然后上述晶圆以及基板一起被切割,上述切割与分离的半导体芯片以及封装基底是以一树脂密封。
然而,早期传统的制造方法中存在一问题,即是已切割与分离的半导体芯片是以一个接着一个的方式定位(positioning)与黏着(mounting)于上述基板上。之后的传统制造方法中也存在一问题,即是已切割与分离的半导体芯片以及封装基底是一个接着一个以树脂来密封。上述二种传统的方法皆需要一与半导体芯片个数同样多的工作程序(working processes),因此造成低产量(productivity)的缺点。
另外,目前各种型态集成电路组件封装的填胶方法是采用直接印刷填胶于晶粒之间,如图1所示。上述复数个晶粒91形成于玻璃基板90上。硅橡胶(Silicone rubber)92是利用一印刷方法形成于玻璃基板90上。一般而言,这种填胶技术会导致晶粒表面于印刷方向的过度填胶(overflow),或者在晶粒表面于非印刷方向造成凹陷(recess),其分别如图2A以及图2B所示。上述填胶可能覆盖上述晶粒的焊垫(bonding pads)。换言之,此种背景技术的填胶方法将因为晶粒表面填胶的不佳的均匀度而造成低良率以及可靠度的问题。
发明内容
本发明的主要目的在于提供一种晶圆级封装的填胶结构及其方法。良好的晶粒由已制造的晶圆中选出,然后利用一挑选置放(Pick&Place)系统放置于一工具上。本发明的填胶方法可以改善晶圆级封装晶粒的良率以及可靠度。
本发明的另一目的在于使用正面朝下填胶以使上述晶粒表面平坦化,并且使在上述晶粒表面不会产生过度(overflow)或凹陷的填胶。
本发明的再一目的在于利用新的填胶方法以改善填胶效果与可靠度测试中的使用寿命(life cycle)。
为实现上述目的,本发明提的填胶的封装结构,包括:
一可移除的基板;
一胶膜图案,形成于该可移除的基板上;
复数个晶粒,位于该胶膜图案中;以及
一黏性材料,填满该复数个晶粒之间并且覆盖该复数个晶粒。
所述封装的填胶结构,其中该胶膜图案利用一印刷方法形成于上述可移除的基板上,其中该胶膜的材料为密封胶(seeling glue)、水溶性UV胶、可重复使用的UV胶或高熔点蜡。
所述封装的填胶结构,其中该可移除的基底材料为聚硅氧、玻璃、石英或陶瓷,其中该黏性材料为一弹性材料,其中该弹性材料为硅树脂、弹性PU、多孔PU、丙烯酸橡胶、蓝膜或UV膜。
所述封装的填胶结构,其中该复数个晶粒是背面朝上地黏着于该胶膜图案上,该复数个晶粒的背面黏着于该黏性材料。
所述封装的填胶结构,还包括一刚性基板置于该黏性材料上,其中该刚性基板的材料包括聚硅氧、玻璃、石英、陶瓷、合金42或印刷电路板。
所述封装的填胶结构,还包括一保护膜形成于该刚性基板上,其中该保护膜的材料为树脂、复合物、环氧物、聚硅氧、蓝膜、UV膜、硅橡胶、硅树脂、弹性PU、多孔PU或丙烯酸橡胶。
本发明提供的封装的填胶结构,还可以包括:
复数个晶粒;以及
一黏性材料,填满于该复数个晶粒之间并且覆盖该复数个晶粒。
所述封装的填胶结构,其中该黏性材料为一弹性材料,其中该弹性材料为硅树脂、弹性PU、多孔PU、丙烯酸橡胶、蓝膜或UV膜。
所述封装的填胶结构,还包括一刚性基板置于该黏性材料的上,其中该刚性基板的材料包括聚硅氧、玻璃、石英、陶瓷、合金42或印刷电路板。
所述封装的填胶结构,还包括一保护膜形成于该刚性基板的上,其中该保护膜的材料为树脂、复合物、环氧物、聚硅氧、硅橡胶、硅树脂、弹性PU、多孔PU、丙烯酸橡胶、蓝膜、或UV膜,其中该保护膜系利用印刷、涂布、黏贴或铸膜方式所形成。
附图说明
图1为根据公知技术的印刷填胶于形成于一玻璃基板上的晶粒之间的示意图。
图2A与图2B为根据公知技术在印刷方向以及非印刷方向的填胶的示意图。
图3为本发明的黏贴一复数个晶粒于一形成于可移除基板的上的胶膜图案上的示意图。
图4为本发明的黏贴上述复数个晶粒于形成于上述可移除基板的上的胶膜图案的上的上视图。
图5为本发明的填满一黏性材料于上述复数个晶粒之间并且覆盖上述复数个晶粒的示意图。
图6为本发明的黏贴一刚性基板至上述黏性材料的示意图。
图7为本发明的形成一保护膜于上述刚性基板上的示意图。
图8为本发明的从上述胶膜图案中移除上述复数个晶粒的示意图。
图9为本发明的形成一保护膜于上述刚性基板上的示意图。
图10A与图10B为一晶圆与一具有铸膜复合物的晶圆的示意图。
图11A与图11B为附着于基板上的晶粒铸膜前与后的示意图。
图12为形成一保护膜于上述基板背面的上的示意图。
具体实施方法
本发明的一些实施例将详细地叙述。然而,应该了解的是除了这些明确的叙述外,本发明可以实施在一广泛范围的其它实施例中,并且本发明的范围没有明确限制于上述实施例中,其当视专利申请范围而定。此外,不同组件的部件并未依照比例显示。上述相关部件的尺寸系被扩大,并且无意义的部份将不显示,以提供本发明更清楚的叙述与理解。
参考图3,描述本发明的黏贴复数个晶粒于一形成于可移除的暂时基板102的上的胶膜图案上。如图3所示,复数个晶粒100置放于一胶膜图案101上。上述复数个晶粒100通常利用一挑选置放(Pick&Place)系统置放于上述胶膜图案101上。上述挑选置放系统可被视为一可移动的移动芯片黏着机(Flip Chip Bonder)。上述胶膜图案101形成于一可移除的暂时基板102上。在一实施例中,上述可移除的基板102为硅橡胶、玻璃、石英或陶瓷。
参考图4,胶膜图案101利用一印刷方法被形成于上述可移除基板102上(如图3所示)。上述参考标号(reference)200为非胶膜印刷区域。在一实施例中,上述复数个晶粒100为背部朝上地黏贴于上述胶膜图案101上。此外,每一上述复数个晶粒100的一边(称为正面)201为向下地(具有焊垫面)黏贴于上述胶膜图案101上。换言之,上述晶粒100的正面201黏贴于上述胶膜图案上。一般而言,上述正面201包含晶粒100的一切割道,因此上述晶粒100的內连线(inter-connectors)並未黏贴至上述胶膜图案101上。如图6所显示,一胶膜图案101形成于晶粒100的正面201,因此并于可移除基板102与晶粒100间形成一密闭空间。要注意的是,上述晶粒100的焊垫(bonding pads)面置于胶膜图案101上。上述复数个晶粒基本上约略对准胶膜图案的边缘以防止上述复数个晶粒的焊垫被其它材料覆盖。
参考图5,为本发明的填满一黏性材料于上述复数个晶粒之间并且覆盖上述复数个晶粒的步骤的示意图。如图5所示,上述黏性材料300填满于复数个晶粒100之间并且覆盖上述复数个晶粒100。在一实施例中,上述黏性材料300为一弹性材料,例如硅橡胶、硅树脂、弹性PU、多孔PU、丙烯酸橡胶、蓝胶或UV胶。上述黏性材料300可以利用旋转涂布、印刷或铸膜灌胶(injection molding)形成。因此,上述复数个晶粒100为背部朝上地黏贴于上述黏性材料300上。
此时,本发明的封装填胶结构包括一可移除基板或一临时基板102。一胶膜图案101形成在上述可移除基板102上。复数个晶粒100置放于上述胶膜图案101上。一黏性材料300填满于上述复数个晶粒100之间并且覆盖上述复数个晶粒100,如图5所示。
参考图6,为本发明的黏贴一相对刚性基板400至上述黏性材料300的步骤的示意图,此称的相对刚性是相对于上述黏性材料300为一弹性材料而言。如图6所示,一相对刚性或称刚性基板400黏贴黏性材料300。在一实施例中,上述刚性基板400的材料包括硅橡胶、玻璃、石英、陶瓷、合金42(商用名称)或印刷电路板。在附着上述刚性基板400至上述黏性材料300之后,一UV烘烤或热烘烤的步骤可加强黏着效果。
上述封装填胶结构还包括一刚性材料400置放于上述黏性材料300上,如图6所示。上述封装填胶结构还包括一保护膜500,形成于上述相对刚性基板400上,如图7所示。上述临时基板102可移除。
此外,一保护膜500形成于上述相对刚性基板400上,如图7所示。上述保护膜500可利用一印刷、涂布、黏贴或铸膜方法形成。在一实施例中,上述保护膜500为树脂、复合物、环氧物、硅橡胶(silicone)、硅橡胶(silicone rubber)、硅树脂、弹性PU、多孔PU、丙烯酸橡胶、蓝胶或UV胶。参考图8,为利用一特殊或特定的处理将上述胶膜图案101或上述临时基板102从上述复数个晶粒剥离(stripping)的示意图。换言之,上述胶膜图案101的表面在一般状况下具有黏性,当上述胶膜图案101置于一特殊或特定的环境中会失去黏性。上述特殊或特定的环境可能为去离子水、溶剂、根据溶液而定约略为摄氏20-40度的特定温度或特殊光(如UV光)等。通过上述特殊或特定环境的处理,上述胶膜图案101与上述晶粒100的键结(engagement)将消失。接着,上述胶膜图案101可以从上述晶粒中剥离。在一实施例中,上述胶膜图案101的材料为密封胶(seeling glue)、水溶性UV胶、可重复使用(reworkable)UV胶或高熔点蜡。
本发明的晶圆级封装的填胶方法还包括一形成一保护膜500于上述刚性基板400背面的步骤,其作为一缓冲物(buffer),如图9所示。上述保护膜500可利用一印刷、涂布、黏贴或铸膜方式形成。在一实施例中,上述保护膜500为树脂、复合物、环氧物、硅橡胶(silicone)、硅橡胶(siliconerubber)、硅树脂、弹性PU、多孔PU、丙烯酸橡胶、蓝胶或UV胶。
本发明的一封装填胶结构包括复数个晶粒100、一黏性材料300填充于上述复数个晶粒100之间并且覆盖上述复数个晶粒。一刚性基板400置于上述黏性材料300的上,如图8所示。再者,上述封装填胶结构还包括一保护膜500形成于上述刚性基板400的上,如图9所示。
参考图10A与图10B,其为一晶圆600与一含有铸膜复合物(moldingcompound)601的晶圆600的示意图。
参考图11A与图11B,其为附着于基板上的晶粒铸膜前与后的示意图。一已完成制造的晶圆切割成为复数个晶粒602,并且上述晶粒602被固定于一基板600上。一黏性材料603利用一铸膜方法灌胶填满于上述复数个晶粒602之间。
参考图12,其为形成一保护膜于上述基板背面的上的示意图。上述保护膜604可以利用一印刷、涂布、黏贴或铸膜方法来形成。在一实施例中,上述保护膜604为树脂、复合物、环氧物、硅橡胶(silicone)、硅橡胶(siliconerubber)、硅树脂,弹性PU、多孔PU、丙烯酸橡胶、蓝胶或UV胶。上述保护膜604可以加强上述晶圆级封装的硬度、可以利用激光或墨水作标记并且易于切割。
在本发明中,由铸膜/印刷方法以填胶于上述复数个晶粒100之间,其平坦度可达到+/-20微米(micron)。其与传统的直接铸膜填胶于上述晶粒之间的方法不同。因此,本发明的封装填胶方法可以避免上述晶粒表面填胶过度或凹陷,结果增进了填胶效果以及可靠度测试中的使用寿命(lifecycle)。
虽然特殊实施例已被描述与叙述,凡熟悉此领域的技术人员,在不脱离本专利精神或范围内,所作的更动或润饰,均属于本发明所描述精神下所完成的等效改变或设计,且应包含在申请专利范围内。

Claims (10)

1. 一种封装的填胶结构,包括:
一可移除的基板;
一胶膜图案,形成一胶膜印刷区域与一非胶膜印刷区域于该可移除的基板上;
复数个晶粒,背部朝上,位于该胶膜印刷区域且该非胶膜印刷区域、该可移除的基板与该晶粒形成复数封闭空间;以及
以一黏性材料,填满该复数个晶粒之间并且覆盖该复数个晶粒;
其中该黏性材料为一弹性材料,其中该弹性材料为硅树脂、弹性PU、多孔PU、丙烯酸橡胶、蓝膜或UV膜。
2. 如权利要求1的封装的填胶结构,其特征在于,其中该胶膜图案利用一印刷方法形成于上述可移除的基板上,其中该胶膜的材料为密封胶、水溶性UV胶、可重复使用的UV胶或高熔点蜡。
3. 如权利要求1的封装的填胶结构,其特征在于,其中该可移除的基板材料为聚硅氧、玻璃、石英或陶瓷。
4. 如权利要求1的封装的填胶结构,其特征在于,其中该复数个晶粒是背面朝上地黏着于该胶膜图案上,该黏性材料覆盖于该复数个晶粒的背面。
5. 如权利要求1的封装的填胶结构,其特征在于,还包括一刚性基板置于该黏性材料上,其中该刚性基板的材料包括聚硅氧、玻璃、石英、陶瓷、合金42或印刷电路板。
6. 如权利要求5的封装的填胶结构,其特征在于,还包括一保护膜形成于该刚性基板上,其中该保护膜的材料包括树脂、复合物、环氧物、聚硅氧、蓝膜、UV膜、硅橡胶、弹性PU、多孔PU或丙烯酸橡胶。
7. 一种填胶结构的封装方法,包括:
于一可移除的基板上形成一胶膜图案;
放置复数个晶粒于该胶膜图案上,其中该胶膜图案、该基板与该晶粒形成复数空间;以及
以一黏性材料,填满于该复数个晶粒之间并且覆盖该复数个晶粒。
8. 如权利要求7的填胶结构的封装方法,其特征在于,其中该黏性材料为一弹性材料,其中该弹性材料为硅树脂、弹性PU、多孔PU、丙烯酸橡胶、蓝膜或UV膜。
9. 如权利要求7的填胶结构的封装方法,其特征在于,还包括一刚性基板置于该黏性材料之上,其中该刚性基板的材料包括聚硅氧、玻璃、石英、陶瓷、合金42或印刷电路板。
10. 如权利要求9的填胶结构的封装方法,其特征在于,还包括形成一保护膜于该刚性基板之上,其中该保护膜的材料包括树脂、复合物、环氧物、聚硅氧、硅橡胶、弹性PU、多孔PU、丙烯酸橡胶、蓝膜、或UV膜,其中该保护膜利用包括印刷、涂布、黏贴或铸膜方式所形成。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8999736B2 (en) * 2003-07-04 2015-04-07 Epistar Corporation Optoelectronic system
TW200807526A (en) * 2006-07-27 2008-02-01 Touch Micro System Tech Method of wafer segmenting
US7830004B2 (en) * 2006-10-27 2010-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with base layers comprising alloy 42
KR100826393B1 (ko) 2007-05-22 2008-05-02 삼성전기주식회사 전도성 패턴을 갖는 실링 라인으로 구비된 웨이퍼 레벨디바이스 패키지 및 그 패키징 방법
US20090079064A1 (en) * 2007-09-25 2009-03-26 Jiamiao Tang Methods of forming a thin tim coreless high density bump-less package and structures formed thereby
CN100595897C (zh) 2008-08-20 2010-03-24 晶方半导体科技(苏州)有限公司 晶圆级封装对象及其形成的方法
JP5389490B2 (ja) * 2009-03-23 2014-01-15 東京エレクトロン株式会社 三次元集積回路の製造方法及び装置
CN103199023A (zh) * 2009-08-17 2013-07-10 晶元光电股份有限公司 系统级光电结构及其制作方法
CN102376590B (zh) * 2010-08-05 2013-11-27 矽品精密工业股份有限公司 芯片尺寸封装件及其制法
TW201331984A (zh) * 2012-01-31 2013-08-01 Chenming Mold Ind Corp Ic屏蔽膜層及其製程方法
US9768038B2 (en) 2013-12-23 2017-09-19 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of making embedded wafer level chip scale packages
CN105390403B (zh) * 2015-10-13 2017-10-20 中国电子科技集团公司第五十四研究所 一种ltcc厚薄膜混合基板制造中的基板腔体填充方法
CN105568329A (zh) * 2016-02-23 2016-05-11 河源市众拓光电科技有限公司 一种在led外延片上电镀铜的方法
JP6598723B2 (ja) * 2016-04-06 2019-10-30 株式会社ディスコ パッケージウェーハの製造方法
CN107393840A (zh) * 2017-06-15 2017-11-24 江苏长电科技股份有限公司 一种陶瓷基板封装的切割方法
CN107738135A (zh) * 2017-11-24 2018-02-27 深圳市精品诚电子科技有限公司 镜片加工排屑的方法
WO2020132801A1 (zh) * 2018-12-24 2020-07-02 深圳市柔宇科技有限公司 电子器件及其制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002134638A (ja) * 2000-10-27 2002-05-10 Kyocera Corp 光半導体素子収納用パッケージ
US6387728B1 (en) * 1999-11-09 2002-05-14 Advanced Semiconductor Engineering, Inc. Method for fabricating a stacked chip package
US6429045B1 (en) * 2001-02-07 2002-08-06 International Business Machines Corporation Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage
US20020192927A1 (en) * 1999-01-19 2002-12-19 Fujitsu Limited Semiconductor device production method and apparatus
US6627477B1 (en) * 2000-09-07 2003-09-30 International Business Machines Corporation Method of assembling a plurality of semiconductor devices having different thickness
CN1464540A (zh) * 2002-06-26 2003-12-31 威宇科技测试封装(上海)有限公司 一种能提高多芯片封装合格率的封装方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2436600A1 (de) 1974-07-30 1976-02-19 Semikron Gleichrichterbau Verfahren zur erzielung einer oberflaechenstabilisierenden schutzschicht bei halbleiterbauelementen
JPS61188957A (ja) * 1985-02-18 1986-08-22 Toshiba Corp 回路モジユ−ルの製造方法
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US6130116A (en) 1996-12-13 2000-10-10 Tessera, Inc. Method of encapsulating a microelectronic assembly utilizing a barrier
US5953588A (en) 1996-12-21 1999-09-14 Irvine Sensors Corporation Stackable layers containing encapsulated IC chips
US6025638A (en) * 1998-06-01 2000-02-15 International Business Machines Corporation Structure for precision multichip assembly
JP2001044226A (ja) 1999-07-27 2001-02-16 Mitsubishi Electric Corp 半導体装置の製造方法および半導体装置
JP2001313350A (ja) 2000-04-28 2001-11-09 Sony Corp チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法
US6489185B1 (en) 2000-09-13 2002-12-03 Intel Corporation Protective film for the fabrication of direct build-up layers on an encapsulated die package
JP2002093830A (ja) * 2000-09-14 2002-03-29 Sony Corp チップ状電子部品の製造方法、及びその製造に用いる疑似ウェーハの製造方法
JP5035580B2 (ja) * 2001-06-28 2012-09-26 ナガセケムテックス株式会社 弾性表面波デバイスおよびその製法
TW497236B (en) 2001-08-27 2002-08-01 Chipmos Technologies Inc A soc packaging process
JP2004063510A (ja) * 2002-07-25 2004-02-26 Sony Corp 素子の転写方法
DE10234951B4 (de) 2002-07-31 2009-01-02 Qimonda Ag Verfahren zur Herstellung von Halbleiterschaltungsmodulen
US6965160B2 (en) 2002-08-15 2005-11-15 Micron Technology, Inc. Semiconductor dice packages employing at least one redistribution layer
US20050249945A1 (en) * 2004-05-10 2005-11-10 Wen Kun Yang Manufacturing tool for wafer level package and method of placing dies

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020192927A1 (en) * 1999-01-19 2002-12-19 Fujitsu Limited Semiconductor device production method and apparatus
US6387728B1 (en) * 1999-11-09 2002-05-14 Advanced Semiconductor Engineering, Inc. Method for fabricating a stacked chip package
US6627477B1 (en) * 2000-09-07 2003-09-30 International Business Machines Corporation Method of assembling a plurality of semiconductor devices having different thickness
JP2002134638A (ja) * 2000-10-27 2002-05-10 Kyocera Corp 光半導体素子収納用パッケージ
US6429045B1 (en) * 2001-02-07 2002-08-06 International Business Machines Corporation Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage
CN1464540A (zh) * 2002-06-26 2003-12-31 威宇科技测试封装(上海)有限公司 一种能提高多芯片封装合格率的封装方法

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