TWI302731B - Filling paste structure and process for wl-csp - Google Patents
Filling paste structure and process for wl-csp Download PDFInfo
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Description
1302731 九、發明說明: 【發明所屬之技術領域】 本發明係與一種晶圓級封裝之填膠結構及其方法有 關特別疋有關於一種利用頂邊朝下t〇p side face d〇Wn ) $填滿膠使與日日日粒表面平坦而不超過(。爾flQwing)或凹 fe (recessing)於上述晶粒表面之結構及其方法,結果增 進了填膠之效果以及可靠度測試中之使用壽命(丨说 cycle) 〇 _【先前技術】 一種具有球陣列(Bal! Grid Array,BGA )結構之半導 體兀件被發展以適用於高腳位數(high_pin_c〇unt)封裝之 ,半導體兀件。在上述具有球陣列結構之半導體元件中,一 ‘半導體晶片利用黏性材料固定(m〇unted)於基板㈤^ substrate )主表面上之一晶片固定區域,數個凸塊電極 (bump electrodes)以一陣列而置於上述基板背面之上, # 其係在上述基板主表面之對面。 ^傳統之晶片尺度封裝(CSP)係利用一半導體晶圓切 割成半導體晶片之方法形成,接著上述半導體晶片以一預 定之位置而固定於一作為封裝基底(package base)之基板 上,並且以樹脂將上述晶片密封,然後上述密封樹脂與基 板於上述半導體晶片之間的部分一起被切割。在另外一個 傳統之方法中,一半導體晶圓(尚未被切割成半導體晶片) 附著於一基板之上,然後上述晶圓以及基板一起被切割, 上述切割與分離之半導體晶片以及封裝基底係以一樹脂密 6 1302731 * » 封。 以而,早期傳統之製造方法中存在-問題,即是已切 割與分離之半導體晶片係以一個接著一個的方式定位 (positioning )與以(m〇unting )於上述基板上 之傳統製造方法中亦存在一問題,即是已切割與 導體晶片以及封裝基底係一個接著一個以樹脂來密封。上 j一種傳統之方法皆需要一與半導體晶片個數同樣多之工 作程序(working processes ),目此造成低產旦 (productivity)之缺點。 -里 另外,目前各種型態積體電路元件封裝之填膠 採用直接印刷填膠於晶粒之間,如圖-所示。上述複數個 晶㈣形成於破璃基板9〇 31稷數個 92 孫剎田 ^ ^ (Slllc〇ne rubber) 係利用-印刷方法形成於玻璃基板9g上。 刪膠技術會導致晶粒表面於印刷方向之過又而二 (overflow ),哎老力曰私主 又異膠 (r e c e s s ),其係分別如圖二Α以及二 、珉凹fe 以覆蓋上述晶粒之焊墊不。上述填膠可 ^ ( η__。換言之,此種弈 、==膠方法將因為晶粒表面填膠之不佳 把成低良率以及可靠度之問題。 又而 因此,本發明提供一種新的晶圓級 增進晶圓級封裝晶粒之良率以及可靠度。填膠方法以 【發明内容】 又 及其方-種晶圓級封襄之填膠結構 良好的曰曰粒由已製造之晶圓中選出,然後利用 7 1302731 -挑選置放(Pick&Place)系統放置於一工具上。本發明 之填膠:法可以改善晶圓級封裝晶粒之良率以及可靠度。 本發明之另一目的在於使用頂面朝下填膠以使上述晶 粒表面平坦化,並且使在上述晶粒表面不會產生過度 (overflow )或凹陷之填膠。 本發明之再一目的在於利用新的填膠方法以改善填膠 效果與可靠度測試中之使用壽命(lifeeyele)。 …
7種填膠之封裝結構,包括—可移除基板以及一膠膜 圖=成於上述可移除基板之上。複數個晶粒被放置於上 述膠膜圖案之上。一黏性材料被填滿於上述複數個晶粒之 間並且覆蓋上述複數個晶粒。 上述填膠之封裝結構更包括一堅固基板,放置於上述 黏性材料之上。一保護膜選擇性地形成於上述堅固基板 上。上述保護膜可以利用印刷、塗佈、黏貼或鑄模方法來 形成。 上述可移除基板之材料包括:矽橡膠(silic〇ne)、玻 离石英或陶瓷。上述堅固基板之材料包括:矽橡膠 (silicone )、玻璃、石英、陶瓷、合金42或印刷電路板 (PCB)。上述黏性材料為彈性材料,上述之彈性材料包括: 矽橡膠(silicone rubber)、矽樹脂(smc〇ne resin)、彈性 pu、多孔PU、丙烯酸橡膠(aeryHc 或晶粒切割 膠(藍膠/UV膠)。上述彈性材料可利用旋轉塗佈以及印刷 形成。 上述複數個晶粒為背部朝上地(backupwardly)黏貼 8 1302731 述膠膜圖案上,並且上述晶粒之背部黏貼於黏性材 :上述每一複數個晶粒之切割道之内黏貼上述膠膜圖 案,接著填滿上述黏性材料。 本發明之晶圓尺寸封裝之填勝方法更包括於黏貼一堅 土板之後進订一 UV烘烤(uv curing)或熱洪烤(heat curing)之步驟。 【實施方式】 本發明之一些實施例將詳細地敘述。然而,應該了解 的是除了這些明確之敘料,本發明可以實施在—廣泛範 圍之八匕實轭例中,並且本發明之範圍沒有明確限制於上 述實施例中,其當視其後面之專利申請範圍而定。此外, 不同元件之部件並未依照比例顯示。上述相關部件之尺寸 係被擴大’並且無意義之部份將不顯示,以提供本發明更 清楚之敘述與理解。
參考第三圖,描述本發明之黏貼複數個晶粒於一形成 於可移除基板1G2之上之膠膜圖案上。如第三圖所示,複 數個晶粒100¾放於-膠膜圖t 1〇1上。上述複數個晶粒 1〇〇通常利用一挑選置放(Pick&piace)系統置放於上述 膠膜圖案lGi_L。上述挑選置放系統可被視為—可移動之 移動晶片黏著機”叶^^如以^^上述膠膜圖案…丨形 成於一可移除之基板102上。在一實施例中,上述可移除 之基板102為石夕橡膠、玻璃、石英或陶曼。 參考第四圖,膠膜圖案101利用一 102上(如第三圖所示)。 上述可移除基板 印刷方法被形成於 上述參考標號 9 1302731 (reference ) 200為非膠膜印刷區域。在一實施例中,上 述複數個晶粒100為背部朝上地黏貼於上述膠膜圖案i 】 上。此外,每一上述複數個晶粒100之一邊201為向下地 (具有焊墊面)黏貼於上述膠膜圖案101上。換言之,上 述晶粒100之邊201黏貼於上述膠膜圖案上。一般而言, 上述邊201為晶粒1〇〇之一切割道,因此上述晶粒i㈧之 内連線(inter-connectors)並未黏貼至上述膠膜 〇1 上。要注意的是,上述晶粒100之焊墊(b〇ndingpad、s)面 置於膠膜圖案1G1 Ji。上述複數個晶粒基本上約略對準膠 膜圖案之邊緣以防止上述複數個晶粒之焊墊被其它材料覆 參考第五圖,為本發明之填滿-黏性材料於上述複數 個曰曰粒之間並且覆蓋上述複數個晶粒之步驟之示意圖。如 第五圖所示’上述黏性材料填滿於複數個晶粒ι〇〇之 間並且覆蓋上述複數個晶粒!⑼。在—實施例中,上述黏 φ性材料3 〇 〇 4 一彈性材料,例如石夕橡膠、石夕樹脂、彈性抑、 -多孔PU、丙婦酸橡膠、藍膠或UV膠。上述黏性材料3〇〇 可以利用旋轉塗佈、印刷或注入鎊模(injecti〇nm〇iding) 形成。因此,上述複數個晶粒1〇〇為背部朝上地黏貼於上 述黏性材料300上。 之封裝轉結構包括—可錄基板或一 臨時基板102。一膠膜圖幸丨〇〗^ ,口茶101形成在上述可移除基板102 。後數個晶粒100置放於上述膠膜圖t ι〇ι上。 材料300填滿於上述複數個曰 " 双1固日日粒100之間並且覆蓋上述複 1302731 數個晶粒100,如第五圖所示。 參考第六圖,為本發明之黏貼—堅固基板400至上述 黏性材料300之步驟之示意圖。如第六圖所示,一堅固基 板400黏貼黏性材料3〇〇。在一實施例中,上述堅固基板 彻之材料包括石夕橡膠、玻璃、石英、陶兗、合金42(商 用名稱)或印刷電路板。在附著上述堅固基板4〇〇至上述 黏性材料3GG之後,一 UV烘烤或熱烘烤之步驟可加強黏 者效果。
上述封裝填膠結構更包括一堅固材料4〇〇置放於上述 黏性材料300 _L,如第六圖所示。上述封裝填膠結構更包 括:保護膜500 ’形成於上述堅固基板侧上,如第七圖 所示。上述臨時基板1 可移除。 此外,一保護膜500形成於上述堅固基板獅上,如 =圖所*。上述保護膜500可利用一印刷、塗佈、黏貼 =果方法形成。在一實施例中,上述保護膜 ^物、環氧物、㈣膠(Sllie_)1橡膠(s=ne 或彈性PU、多孔印、丙烯酸橡膠、藍膠 述勝膜图宰;〇ί!八圖’為利用一特殊或特定之處理將上 之示意圖。換言之,上述二 矛面在一般狀況下具有黏性,當上 特殊或特定之環境中會失去黏性。上述==置於-:能為去離子水、溶劑、根據溶液而定===境 11 1302731 特疋壤境之處理’上述膜腺圖安 ,,. ^膘固案1〇1與上述晶粒100之鍵 結c engagement)將洁生。社朴 接耆,上述膠膜圖案101可以 從上述晶粒中剝離。在一眚 實轭例中,上述膠膜圖案101之 材料為密封膠(seeling Μ )、 ggiue)、水洛性UV膠、可重複使用 (reworkable) UV膠或高熔點蠟。 本發明之晶圓級封裝之填膠方法更包括 膜500於上述堅固基极4〇〇 ^ … 板彻之背面之步驟,其係作為-緩 衝物(buffer ),如圖六卸:+ L .,.
回九所不。上述保護膜500可利用一印 刷、塗佈、黏貼或鑄模方式形成。在一實施例中,上述保 護膜5〇0為樹月旨、複合物、環氧物、矽橡膠“ilicone)、 石夕橡膠(S1Hc_ rubber)、石夕樹脂、彈性pu、多孔扣、 丙烯酸橡膠、藍膠或UV膠。 本發明之-封裝填膠結構包括複數個晶粒⑽、一黏 性材料300填充於上述複數個晶粒i⑼之間並 複數個晶粒。一堅固基板4〇〇晋於卜、十.針以u 土攸置於上述黏性材料3⑼之上, 如圖八所示。再者,上述封裳填膠結構更包括一保護膜綱 形成於上述堅固基板400之上,如圖九所示。 參考第十Α圖與第十Β圖,其係為一晶圓6〇〇與一含 有鑄膜複合物(molding comp〇und) 6〇1之晶圓_之示 意圖。 參考第十一 A圖與第十一 B圖,其係為附著於基板上 之晶粒鑄膜前與後之示意圖。—已完成製造之晶圓切割成 為複數個晶粒602,並且上述晶粒6〇2被固定於一基板6〇〇 上。一黏性材料603利用一鑄膜方法填滿於上述複數個 12 1302731 考 < 粒602之間。 之卜:考ΐΐ—圖、’、其係為形成一保護膜於上述基板背面 、:心回上述保護膜604可以利用一印刷、塗佈、 黏貼或鑄膜方法來形g ^ .ii+ Ht 、卜& 成在一實施例中,上述保護膜6〇4 為枒月曰、* “勿、環氧物、矽橡膠(siHc〇ne)、矽橡膠 silicone rubber)、矽樹脂,彈性 pu 橡膠、藍膠或UV膠。卜内烯酉夂 少上述保蠖Μ 604可以加強上述晶圓 、、及封权硬度、可以利用雷射或墨水作標記並且易於切割。 在本毛月中’藉由鎊模/印刷方法以填膠於上述複數個 晶粒1〇0之間,其平坦度可達到仏20微米⑽cron)。其係 與傳統的直接鎢膜填膠於上述晶粒之間的方法不同。因 此,本發明之封t填膠方法可以避免上述晶粒表面填膠過 ,或凹’結果增進了填膠效果以及可靠度測試中之使用 壽命(life cycle )。 雖然特殊實施例已被描述與敘述,凡熟悉此領域之技 藝者’在不脫離本專利精神或範圍内,所作之更動或潤飾, 均屬於本發明所揭補神下所完成之#效改變或設計,且 應包含在下述之申請專利範圍内。 【圖式簡單說明】 第一圖係為根據習知技術之印刷填膠於形成於一玻璃 基板上之晶粒之間之示意圖。 第一 A圖與第二b圖係為根據習知技術在印刷方向以 及非印刷方向之填膠之示意圖。 第二圖係為本發明之黏貼一複數個晶粒於一形成於可 13 1302731 移除基板之上之膠膜圖案上之示意圖。 第四圖係為本發明之黏貼上述複數個晶粒於形成於上 述可移除基板之上之膠膜圖案之上之上視圖。 、 第五圖係為本發明之填滿一黏性材料於上述複數個曰 粒之間並且覆蓋上述複數個晶粒之示意圖。 曰曰 $六圖係為本發明之黏貼—堅固基板至上述 之示意圖。 Ύ =圖係為本發明之形成—保護膜於上述堅固基板上 之不思圖。 第八圖係為本發明之從上述谬膜圖 個晶粒之示意圖。 义後数 ^九圖係為本發明之形成—保護膜 之示意圖。 <王口丞极上 第十A圖與第 之晶圓之示意圖。σ糸為-晶圓與-具有鑄膜複合物 一 B圖係為附著於基板上之晶粒鑄 第十’一 Α圖與第 膜前與後之示意圖。 第十二圖係為形成一 意圖。 成保瘦膑於上述基板背面之上之示 【主要元件符號說明】 玻璃基板9〇 晶粒91 矽橡膠92 晶粒100 14 102 1302731 < 4 膠膜圖案(glue pattern) 101 可移除基板(removable substrate ) 參考標號(reference) 200 邊(edge ) 201 黏性材料300 堅固基板(rigid substrate ) 400 保護膜(protection film ) 500 晶圓(pure wafer ) 600 601 Φ 鑄膜複合物(molding compound ) 15
Claims (1)
1302731 4 < 十、申請專利範圍: 1· 一種封装之填膠結構,包括: 一可移除之基板; 案’形成於該可移除之基板上以產生非勝膜圖 案&域與膠膜圖案區域; 固:粒’其,墊面置於該膠膜圖案區域中使得相鄰 板:二2附者於该膠膜圖案上,該晶粒與該可移除基 板之間包含一空隙;以及 • ΓΓΓΓ填滿該複數個晶粒之間並且覆蓋該複數個 =,/、中部分該黏性材料連接該《圖㈣非該晶粒 其中該黏性材料不會外流或凹進於該晶粒之上。 2 ·如申凊專利範圍第1 之晶圓利用-挑選置放r ρ袁之填膠結構’其中該複數 ►膠膜圖案:。放(Pick&piace)系統放置於該 3 ·如申凊專利範圍第1 圖案利用-印丄幵=㈣膠結構,其中該膠膜 方法形成於上述可移除之基板上。 如申凊專利範圍第1頊 之材料為密封膠(seein “填膠結構,其中該膠模 葙# " ng glue)、水溶性UV膠、可重 後使用之UV膠或高炼點蠟。 7重 16 1302731 5 ·如申睛專利範圍第 除之基底材料為聚錢,2之填膠結構,其中該可去 破璃,石英或陶瓷。 6·如申請專利範園第】項 材料為-彈性材料。、、衣之填膠結構,其令該黏性 7·如申請專利範圍第6馆^ 其中該彈性 材料為石夕樹脂、彈性Pu封多膠結構, 或UV膜。 丙稀酸橡膠、藍膜 8·如申請專利範園第6項之 材料係利用旋轉塗佈、、^填料構,其中該彈性 P刷或注入鑄模所形成。 9·如申請專利範圍第1項之封壯* 個晶粒係背面朝上_著於2填膠結構,其中該複數 粒之背面黏著於該黏性材料_案上’該複數個晶 1 〇·如申請專利範圍第9 複數個晶粒之-㈣道^ 轉結構,其中每一該 dJ道之内黏著於該膠膜圖案之上。 膠結構,更包括一堅 u’=f專利範圍第1項之封裂之填 口基板置於該黏性材料上。 膠結構,其中該堅 12,如申請專利範圍第11項之封裂之填 1302731 固基板之材料包括聚矽氧、玻璃 42或印刷電路板。
石英、陶瓷、合金 .13.如:請專利範圍第u項之封裝之填膠結構,更包括一 保濩膜形成於該堅固基板上。 14.=f專:^圍第13項之封襄之填膠結構,其中該保 書 4臈可以被雷射或墨水做印記(耐㈣)。 15.2請專·圍第13項之封U填膠結構,其中該保 :、之材枓為樹脂、複合物、環氧物、聚矽氧、誌膜、 - 胰、矽橡膠、矽樹脂、彈性pu、多孔Pu $ $ / Λ 橡膠。 夕札pU或丙烯酸 16.如申請專利範圍第13項之封 ,•護膜係利用印刷、塗佈、黏貼:㈣模;;:形其成中該保 18
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Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8999736B2 (en) * | 2003-07-04 | 2015-04-07 | Epistar Corporation | Optoelectronic system |
TW200807526A (en) * | 2006-07-27 | 2008-02-01 | Touch Micro System Tech | Method of wafer segmenting |
US7830004B2 (en) * | 2006-10-27 | 2010-11-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packaging with base layers comprising alloy 42 |
KR100826393B1 (ko) | 2007-05-22 | 2008-05-02 | 삼성전기주식회사 | 전도성 패턴을 갖는 실링 라인으로 구비된 웨이퍼 레벨디바이스 패키지 및 그 패키징 방법 |
US20090079064A1 (en) * | 2007-09-25 | 2009-03-26 | Jiamiao Tang | Methods of forming a thin tim coreless high density bump-less package and structures formed thereby |
CN100595897C (zh) | 2008-08-20 | 2010-03-24 | 晶方半导体科技(苏州)有限公司 | 晶圆级封装对象及其形成的方法 |
JP5389490B2 (ja) * | 2009-03-23 | 2014-01-15 | 東京エレクトロン株式会社 | 三次元集積回路の製造方法及び装置 |
CN101996892B (zh) * | 2009-08-17 | 2013-03-27 | 晶元光电股份有限公司 | 系统级光电结构及其制作方法 |
CN102376590B (zh) * | 2010-08-05 | 2013-11-27 | 矽品精密工业股份有限公司 | 芯片尺寸封装件及其制法 |
TW201331984A (zh) * | 2012-01-31 | 2013-08-01 | Chenming Mold Ind Corp | Ic屏蔽膜層及其製程方法 |
US9768038B2 (en) | 2013-12-23 | 2017-09-19 | STATS ChipPAC, Pte. Ltd. | Semiconductor device and method of making embedded wafer level chip scale packages |
CN105390403B (zh) * | 2015-10-13 | 2017-10-20 | 中国电子科技集团公司第五十四研究所 | 一种ltcc厚薄膜混合基板制造中的基板腔体填充方法 |
CN105568329A (zh) * | 2016-02-23 | 2016-05-11 | 河源市众拓光电科技有限公司 | 一种在led外延片上电镀铜的方法 |
JP6598723B2 (ja) * | 2016-04-06 | 2019-10-30 | 株式会社ディスコ | パッケージウェーハの製造方法 |
CN107393840A (zh) * | 2017-06-15 | 2017-11-24 | 江苏长电科技股份有限公司 | 一种陶瓷基板封装的切割方法 |
CN107738135A (zh) * | 2017-11-24 | 2018-02-27 | 深圳市精品诚电子科技有限公司 | 镜片加工排屑的方法 |
CN113169076A (zh) * | 2018-12-24 | 2021-07-23 | 深圳市柔宇科技股份有限公司 | 电子器件及其制作方法 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2436600A1 (de) | 1974-07-30 | 1976-02-19 | Semikron Gleichrichterbau | Verfahren zur erzielung einer oberflaechenstabilisierenden schutzschicht bei halbleiterbauelementen |
JPS61188957A (ja) * | 1985-02-18 | 1986-08-22 | Toshiba Corp | 回路モジユ−ルの製造方法 |
US5353498A (en) | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
US6130116A (en) * | 1996-12-13 | 2000-10-10 | Tessera, Inc. | Method of encapsulating a microelectronic assembly utilizing a barrier |
US5953588A (en) | 1996-12-21 | 1999-09-14 | Irvine Sensors Corporation | Stackable layers containing encapsulated IC chips |
US6025638A (en) * | 1998-06-01 | 2000-02-15 | International Business Machines Corporation | Structure for precision multichip assembly |
JP3816253B2 (ja) * | 1999-01-19 | 2006-08-30 | 富士通株式会社 | 半導体装置の製造方法 |
JP2001044226A (ja) * | 1999-07-27 | 2001-02-16 | Mitsubishi Electric Corp | 半導体装置の製造方法および半導体装置 |
TW434854B (en) * | 1999-11-09 | 2001-05-16 | Advanced Semiconductor Eng | Manufacturing method for stacked chip package |
JP2001313350A (ja) | 2000-04-28 | 2001-11-09 | Sony Corp | チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法 |
US6627477B1 (en) * | 2000-09-07 | 2003-09-30 | International Business Machines Corporation | Method of assembling a plurality of semiconductor devices having different thickness |
US6489185B1 (en) | 2000-09-13 | 2002-12-03 | Intel Corporation | Protective film for the fabrication of direct build-up layers on an encapsulated die package |
JP2002093830A (ja) * | 2000-09-14 | 2002-03-29 | Sony Corp | チップ状電子部品の製造方法、及びその製造に用いる疑似ウェーハの製造方法 |
JP2002134638A (ja) * | 2000-10-27 | 2002-05-10 | Kyocera Corp | 光半導体素子収納用パッケージ |
US6429045B1 (en) * | 2001-02-07 | 2002-08-06 | International Business Machines Corporation | Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage |
JP5035580B2 (ja) * | 2001-06-28 | 2012-09-26 | ナガセケムテックス株式会社 | 弾性表面波デバイスおよびその製法 |
TW497236B (en) * | 2001-08-27 | 2002-08-01 | Chipmos Technologies Inc | A soc packaging process |
CN100401485C (zh) * | 2002-06-26 | 2008-07-09 | 威宇科技测试封装有限公司 | 一种能提高多芯片封装合格率的封装方法 |
JP2004063510A (ja) * | 2002-07-25 | 2004-02-26 | Sony Corp | 素子の転写方法 |
DE10234951B4 (de) | 2002-07-31 | 2009-01-02 | Qimonda Ag | Verfahren zur Herstellung von Halbleiterschaltungsmodulen |
US6965160B2 (en) * | 2002-08-15 | 2005-11-15 | Micron Technology, Inc. | Semiconductor dice packages employing at least one redistribution layer |
US20050249945A1 (en) | 2004-05-10 | 2005-11-10 | Wen Kun Yang | Manufacturing tool for wafer level package and method of placing dies |
-
2004
- 2004-12-30 US US11/026,488 patent/US7400037B2/en active Active
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2005
- 2005-01-06 TW TW094100360A patent/TWI302731B/zh not_active IP Right Cessation
- 2005-04-11 SG SG200502825A patent/SG123653A1/en unknown
- 2005-04-27 CN CNB200510068973XA patent/CN100413044C/zh active Active
- 2005-04-27 DE DE102005019553A patent/DE102005019553B4/de active Active
- 2005-05-11 KR KR1020050039461A patent/KR100693664B1/ko active IP Right Grant
- 2005-10-24 JP JP2005308090A patent/JP2006190975A/ja active Pending
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KR20060079057A (ko) | 2006-07-05 |
SG123653A1 (en) | 2006-07-26 |
US20060145364A1 (en) | 2006-07-06 |
TW200623350A (en) | 2006-07-01 |
KR100693664B1 (ko) | 2007-03-14 |
US7476565B2 (en) | 2009-01-13 |
US7400037B2 (en) | 2008-07-15 |
DE102005019553B4 (de) | 2006-12-21 |
US20080044945A1 (en) | 2008-02-21 |
CN1797728A (zh) | 2006-07-05 |
JP2006190975A (ja) | 2006-07-20 |
DE102005019553A1 (de) | 2006-07-20 |
CN100413044C (zh) | 2008-08-20 |
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