200423357200423357
【發明所屬之技術領域】 本發明係有關於一種晶圓級封裝方法，特別係有關於 一種防止具有應力緩衝層之晶圓翹曲之晶圓級封裝製程。' 【先前技術】 晶圓級封裝〔wafer level packaging〕係為—種技 術先進之半導體封裝，在晶圓級封裝製程中，其係在一曰 __ 曰日 圓上完成對多個晶片之封裝，再切割為個別之晶圓級晶片· 尺寸封裝結構〔wafer level chip scale package〕，與 習知個別晶片封裝方式更具有低成本大面積封裝之特性，' 而該些晶圓級晶片尺寸封裝結構係具有複數個凸起電極 〔bump electrode〕，如銲球或銅柱，而被要求直接表面 接合至外部印刷電路板，但習知印刷電路板之熱膨脹係數 係遠大於半導體晶片，為了消除在接合界面處凸起電極之 應力作用，習知在該些凸起電極與該晶片之間係形成有一 具有適當厚度之應力緩衝層〔如聚亞醯胺〕，其厚度約在 8 0〜1 6 0微米’用以減輕對該些凸起電極之應力，防止因金 屬疲勞〔metal fatigue〕可能引起凸起電極之斷損。 我國專利公告第5 1 1 2 6 7號「緩衝式雙塾片晶圓級封裝 結構」係揭示有一種晶圓級封裝結構，請參閱第1圖，該 晶圓級封裝結構1 〇 0係包含有一晶圓11 〇、一絕緣保護層 1 2 0及複數個導電凸塊1 3 0 ’其中該晶圓11 〇係具有複數個 電極113，設於該晶圓110之正面ill 〔或稱主動面active surface〕，而該絕緣保護層120係形成於該晶圓11〇之正 面111，用以介電與保護晶圓11 〇及緩衝應力，並在該晶圓[Technical field to which the invention belongs] The present invention relates to a wafer-level packaging method, and more particularly, to a wafer-level packaging process for preventing warpage of a wafer having a stress buffer layer. '[Previous technology] Wafer level packaging is a kind of advanced semiconductor packaging. In the wafer level packaging process, it completes the packaging of multiple wafers on a Japanese yen. It is then cut into individual wafer-level wafer-size package structures (wafer level chip scale package), and it is known that individual wafer packaging methods have the characteristics of low-cost large-area packaging, and these wafer-level wafer-size package structures are It has a plurality of bump electrodes, such as solder balls or copper pillars, and is required to be directly surface-bonded to an external printed circuit board. However, the thermal expansion coefficient of the conventional printed circuit board is much larger than that of a semiconductor wafer. It is known that a stress buffer layer (such as polyimide) with an appropriate thickness is formed between the raised electrodes and the wafer, and the thickness is about 80 to 160 microns. 'It is used to reduce the stress on the raised electrodes, and prevent breakage of the raised electrodes due to metal fatigue. China's Patent Bulletin No. 5 1 1 2 6 7 "Buffered Double-Chip Wafer-Level Packaging Structure" discloses a wafer-level packaging structure. Please refer to Figure 1. The wafer-level packaging structure 100 includes There is a wafer 110, an insulating protective layer 120, and a plurality of conductive bumps 130. Among them, the wafer 110 has a plurality of electrodes 113, and is disposed on the front side of the wafer 110. active surface], and the insulating protection layer 120 is formed on the front surface 111 of the wafer 110, for dielectricizing and protecting the wafer 110 and buffering stress, and on the wafer
第7頁 200423357 五、發明說明（2) 110之每一電極113上設置有複數個導體柱131及其上之一 凸塊墊片132，該些凸塊墊片132係接合有該些導電凸塊 1 30，如鉛錫凸塊，然而該晶圓級封裝結構1 〇〇之晶圓1 1 0 背面11 2係呈顯露狀，不具有良好保護性，並且該絕緣保 護層1 2 0係為達應力緩衝之效，其厚度須比習知晶圓防護 層〔wafer passivation layer )來得更厚，在該絕緣保 護層120形成過程，由於熱固化收縮〔shrink〕現象，固 化後絕緣保護層1 2 0之體積將微量縮小，導致該晶圓之11 〇 之勉曲〔請參閱第1圖〕，使得後續之單離切割及搬儲作 業更加困難，甚至引發晶圓丨丨〇破裂，尤其，當該晶圓n 〇 之背面112需要研磨薄化或者是該晶圓11〇之尺寸愈大〔特 ‘別是1 2忖晶圓〕時，該具有絕緣保護層丨2 〇之晶圓丨丨〇將翹 曲得更嚴重，此外，在完成積體電路之晶圓丨丨〇本身亦殘 留有因沉積金屬層之應力作用，而產生製程中晶圓翹曲之 現象’另’該絕缘保護層1 2 G之熱膨脹係數l CTE〕〔約5 0 Ppm/K〕係與半導體矽晶圓11〇之熱膨脹係數〔約2.4 ppm/K〕極不匹配，隨製程溫度不同對該矽晶圓11〇亦 生一定之應力作用。 另，我國專利公告第5 1 研磨方法」’揭示有一種凸 其係在晶圓形成好凸塊之後 成有一有機材料層並黏附一 研磨，利用熱處理揮發去除 全剝離該晶圓之背面，但在 6116號「凸起封裝晶圓之背面 起封裝晶圓之背面研磨方法， ’在該晶圓之具凸塊表面係形 膠帶’再對該晶圓之背面進行 該有機材料層，而使該膠帶完 研磨後，該晶圓之具凸塊之表Page 7 200423357 V. Description of the invention (2) Each electrode 113 of 110 is provided with a plurality of conductor posts 131 and a bump pad 132 thereon, and the bump pads 132 are connected with the conductive bumps. Block 1 30, such as a lead-tin bump, however, the wafer-level package structure 1000 of the wafer 1 110, the back surface 11 2 is exposed, does not have good protection, and the insulating protective layer 1 2 0 is In order to achieve the effect of stress buffering, its thickness must be thicker than the conventional wafer passivation layer. During the formation of the insulating protective layer 120, due to the shrinkage phenomenon of thermal curing, the cured insulating protective layer 1 2 0 The volume will be reduced by a small amount, which leads to a slight warp of the wafer (see Figure 1), which makes subsequent single-off cutting and storage operations more difficult, and even causes the wafer to break, especially when the wafer When the back surface 112 of the circle n 0 needs to be thinned or the size of the wafer 11 is larger (especially a 12 mm wafer), the wafer with an insulating protective layer 丨 2 〇 丨 〇 will be warped The curve is more serious. In addition, the wafers that complete the integrated circuit are completed. There is also a residual phenomenon of wafer warping during the process due to the stress of the deposited metal layer. In addition, the thermal expansion coefficient of the insulating protective layer 1 2 G l CTE] [about 50 Ppm / K] is related to semiconductor silicon. The thermal expansion coefficient [about 2.4 ppm / K] of the wafer 110 is extremely mismatched, and a certain stress effect is also exerted on the silicon wafer 11 depending on the process temperature. In addition, the Chinese Patent Bulletin No. 5 1 Grinding Method "'discloses that a convex system is formed by forming an organic material layer on a wafer after the bumps have been formed and adhered to a grind. No. 6116 "A method for polishing the back surface of a packaged wafer from the back surface of the packaged wafer, 'the bump-shaped tape on the surface of the wafer', and then performing the organic material layer on the back surface of the wafer to make the tape After polishing, the bumped surface of the wafer
200423357 五、發明說明（3) 面係已形成有凸塊、有機材料層及膠帶，將導致該凸起封 裝晶圓之翹曲，並且在研磨之後，該晶圓之背面並不具有 保護措施。 【發明内容】 本發明之主要目的係在於提供一種晶圓級封裝製程， 其特徵係在於’在形成應力緩衝層之步驟與形成凸起電極 之步驟之間，形成有一防翹曲層於研磨後之晶圓背面，以 修正該應力緩衝層對該晶圓之勉曲度，以利後續之凸起電 極形成、單離切割、搬運及表面接合等運用，同時又可增 進封裝後晶圓背面之保護。 θ 本發明之次一目的係在於提供一種晶圓級封裝結構， 、其係利用一防翹曲層形成於一晶圓之背面，以消除該應力 緩衝層對該晶圓之不當翹曲影響，有利於在晶圓級封裝製 程中之形成凸起電極與晶圓切割等後續製程及運用，並能 對該晶圓達到良好保護。 依本發明之晶圓級封裝製程，其包含之步驟有： 供一晶圓’該晶圓係具有一正面、一背面以及複數 個設於該正面之銲墊，較佳地，該晶圓之正面更形成有一 重分配線路層〔redistribution wiring layer〕； 形成一應力緩衝層於該晶圓之正面； 研磨該晶圓之背面； 形成一防翹曲層於該晶圓之背面，用以修正該具有應 力緩衝層之晶圓之翹曲度；及 形成複數個凸起電極於該應力緩衝層上，且該些凸起200423357 V. Description of the invention (3) The bumps, layers of organic materials and tape have been formed on the surface, which will cause warpage of the bump-encapsulated wafer, and after grinding, the backside of the wafer has no protective measures. [Summary of the Invention] The main object of the present invention is to provide a wafer-level packaging process, which is characterized in that 'a warpage prevention layer is formed between the step of forming a stress buffer layer and the step of forming a bump electrode after grinding. The backside of the wafer is used to correct the warpage of the stress buffer layer to the wafer, which facilitates subsequent bump electrode formation, single-cut cutting, handling and surface bonding. At the same time, it improves the backside of the wafer after packaging. protection. θ A second object of the present invention is to provide a wafer-level packaging structure, which is formed on the back of a wafer by using a warpage prevention layer to eliminate the influence of the stress buffer layer on the wafer's improper warpage. It is beneficial for subsequent processes and applications such as forming bump electrodes and wafer cutting in the wafer-level packaging process, and can achieve good protection for the wafer. The wafer-level packaging process according to the present invention includes the steps of: providing a wafer. The wafer has a front surface, a back surface, and a plurality of pads disposed on the front surface. Preferably, the wafer A redistribution wiring layer is formed on the front surface; a stress buffer layer is formed on the front surface of the wafer; a back surface of the wafer is ground; a warpage preventing layer is formed on the back surface of the wafer to correct the Warpage of a wafer with a stress buffer layer; and forming a plurality of bump electrodes on the stress buffer layer, and the bumps
第9頁 200423357 五、發明說明（4) 電極係電性連接至對應銲墊。 【實施方式】 參閱所附圓式，本發明將列舉以下之實施例說明。 曰a 請參閱第2圓，依本發明之一具體實施例所例 圓級封裝製程，其包含之步驟有：「提供一晶圓」丨i、 「形成一重分配線路層於該晶圓之正面」12、「形 一 力緩衝層於該晶圓之正面」丨3、「研磨該晶圓之背面」& 14、「形成一防翹曲層於該晶圓之背面」15及「形成 個凸起電極於該應力緩衝層上」16等步驟。 ^依本發明之晶圓級封裝製程，首先請參閱第3A圖，在 4步驟11中’所提供之晶圓2 〇係具有一正面21、一背面2 2 >乂及複數個設於該正面21之銲墊23，該些銲墊23係配設於 该晶圓20之每一晶片區域，如中央排列、周邊排列或矩陣 排列，在本實施例中，該些銲墊23係對應於每一晶片區域 而1 ·=排列，泫晶圓2 0係可包含有複數個記憶體、顯示 器驅動器、微處理器或圖形處理器等等，該晶圓2〇之尺寸 係為4至12吋，而該晶圓2〇之厚度約在5〇〇〜75〇微米，較佳 地，本發明之晶圓級封裝製程用以解決較大尺寸〔如12或 8寸〕之b曰圓2 〇在晶圓級封裝製程中之組曲度，較佳地， ϋ供晶圓步驟11之後，另包含有一重分配線路層形成步 ，請參閱第3Β圖，其係利用濺鍍或電鍍技術在該晶圓 八之正面2 1形成一金屬層，再將該金屬層顯影蝕刻為一重 ，配，路層30〔redistribution wiring layer, RDL〕， 4重刀配線路層3 〇之第一端3丨係連接至對應銲墊2 3，而該Page 9 200423357 V. Description of the invention (4) The electrode system is electrically connected to the corresponding pad. [Embodiment] Referring to the attached circle form, the present invention will enumerate the following examples. A Please refer to the second circle. According to a specific example of the embodiment of the present invention, a round-level packaging process includes the steps of: "providing a wafer" i, "forming a redistribution circuit layer on the front side of the wafer. "12," form a force buffer layer on the front side of the wafer "3," grind the back side of the wafer "& 14," form a warpage prevention layer on the back side of the wafer "15 and" form a The bump electrode is on the stress buffer layer. ^ According to the wafer-level packaging process of the present invention, please first refer to FIG. 3A. In step 11 of step 4, the wafer 2 provided has a front surface 21, a back surface 2 2 > The pads 23 on the front surface 21 are arranged on each wafer area of the wafer 20, such as a central arrangement, a peripheral arrangement or a matrix arrangement. In this embodiment, the pads 23 correspond to Each wafer area is 1 · = aligned. The wafer 20 can contain multiple memories, display drivers, microprocessors or graphics processors, etc. The size of the wafer 20 is 4 to 12 inches. , And the thickness of the wafer 20 is about 500-750 microns, preferably, the wafer-level packaging process of the present invention is used to solve a larger circle [such as 12 or 8 inches]. The group curvature in the wafer-level packaging process, preferably, includes a redistribution circuit layer forming step after the wafer supply step 11, see FIG. 3B, which uses sputtering or electroplating technology on the wafer. The front side of the round eight 2 1 forms a metal layer, and then develops and etches the metal layer into a single layer. The road layer 30 [redistribut ion wiring layer, RDL], the first end 3 of the 4-layer knife with wiring layer 3 is connected to the corresponding pad 2 3, and the
第10頁 200423357 五、發明說明（5) "一"—~ 重分配線路層3 0之第二端3 2係矩陣排列於該晶圓2 〇正面21 之每，一晶片區域。 之後，執行該應力緩衝層形成步驟13，請參閱第％ 圖，利用旋塗〔spin coating〕、印刷或貼附方式將一如 聚亞醢胺或石夕膠等材質之應力緩衝層4〇形成於該晶圓2〇之 正面21 ’該應力緩衝層40之厚度係約為5〇〜3〇〇微米，在本 實施例中’ 5亥應力緩衝層4 〇係全面覆蓋該晶圓2 〇之正面21 及该重分配線路層3 0，較佳地，對該應力緩衝層4 〇進行平 坦化處理。 之後’執行晶背研磨步驟14，請參閱第3D圖，其係先 將該晶圓20放置於一晶圓研磨設備之載台8丨，該載台8丨係 •吸附該晶圓2 0之正面21平貼，並使該晶圓2 〇之背面2 2顯 露’然後，請參閱第3E圖，以該晶圓研磨設備之研磨頭82 研磨薄化該晶圓2 0之背面2 2，在研磨之後，該晶圓2 〇之厚 度約；！於50〜300歡米’接著執行該防翹曲層形成步驟i 5， 請參閱第3F圖，利用旋塗、印刷或貼附方式將一如聚亞醯 胺等具高熱膨脹係數熱固性材質或者是如銅片等高硬度材 質之防魅曲層50形成於該晶圓2〇之背面22，較佳地，該防 勉曲層50之固化收縮率係不小於該應力緩衝層4 〇之固化收 縮率，該防翹曲層50之厚度係介於50〜300微米為較佳，該 防魅曲層50之厚度設計依該防翹曲層50之固化收縮率、該 晶圓20内部積體電路殘留應力及該應力緩衝層4 〇之固化收 細率與厚度之不同而不同，用以修正該應力緩衝層4 0對該 晶圓20之輕曲度，在本實施例中，該防翹曲層5 〇係全面覆Page 10 200423357 V. Description of the invention (5) " 一 "-~ The redistribution circuit layer 30 second end 3 2 series matrix is arranged on each of the wafer 20 front surface 21, a wafer area. After that, the stress buffer layer forming step 13 is performed. Referring to FIG.%, A stress buffer layer 40 made of a material such as polyimide or stone rubber is formed by spin coating, printing or attaching. On the front surface 21 of the wafer 20, the thickness of the stress buffer layer 40 is about 50 to 300 microns, and in this embodiment, the stress buffer layer 40 is a full coverage of the wafer 200. The front surface 21 and the redistribution circuit layer 30 are preferably planarized with respect to the stress buffer layer 40. After that, the wafer back grinding step 14 is performed, please refer to FIG. 3D, which first places the wafer 20 on a stage 8 of a wafer polishing equipment, which stage 8 adsorbs the wafer 20 The front surface 21 is flat, and the back surface 2 2 of the wafer 20 is exposed. Then, referring to FIG. 3E, the back surface 22 of the wafer 20 is thinned by the grinding head 82 of the wafer polishing equipment. After lapping, the thickness of the wafer 20 is about !! At 50 ~ 300 Huanmi ', the step 5 for forming the warpage preventing layer is then performed. Please refer to FIG. 3F, and apply spin coating, printing, or attaching a thermosetting material with high thermal expansion coefficient such as polyimide or An anti-curvy layer 50 of a high-hardness material such as a copper sheet is formed on the back surface 22 of the wafer 20. Preferably, the curing shrinkage of the anti-curvature layer 50 is not less than the curing shrinkage of the stress buffer layer 40. The thickness of the anti-warping layer 50 is preferably between 50 and 300 microns. The thickness of the anti-warping layer 50 is designed according to the curing shrinkage of the anti-warping layer 50 and the integrated circuit inside the wafer 20. Residual stress and the solidification rate and thickness of the stress buffer layer 40 are different. It is used to correct the lightness of the stress buffer layer 40 on the wafer 20. In this embodiment, the warpage prevention Layer 5 〇 full coverage
第11頁 200423357 五、發明說明（6) 蓋該晶圓2 0之背面2 2，且在該 中’該載台8 1係持續吸附該晶 驟1 5之後，當該載台8丨停止對 有應力緩衝層40與防翹曲層5〇 晶圓2 0係具有良好之平坦度， 之後’執行該凸起電極形 圖’利用顯影曝光或蝕刻技術 複數個開孔4 1，在本實施例中 配線路層30之第二端32，或者 之狀況下，該些開孔41係直接 著’請參閱第3H圖，利用電鍍 .個導電元件6 0於該些開孔41， 料、電鍍層、導電樹脂或金屬 接合有複數個凸起電極7〇，如 性導電凸塊或針卿等等，於本 係以銲球示意之，以製造一晶 因此’依據本發明之晶圓 了在晶圓級封裝製程中該應力 該晶圓2 0之翹曲度影響，有利 起電極形成、單離切割、搬運 該防翹曲層5 0係可保留作為該 層’即使在單離該晶圓2 0為複 構之後，該防翹曲層5 0仍保護 本發明之保護範圍當視後 防勉曲層 圓20，在 該晶圓2 0 之已封裝 不會產生 成步驟1 6 使得該應 ，該些開 ，在不具 顯露該晶 、印刷或 該些導電 柱，並在 鮮球、金 實施例中 圓級封裝 級封裝方 緩衝層40 於後續晶 及表面接 晶圓級封 數個晶圓 晶片之背 附之申請 形成步驟15之過程 該防翹曲層形成步 之平貼吸附，該具 卻未有凸起電極之 嚴重之翹曲。 ’首先請參閱第3G 力緩衝層40形成有 孔41係顯露該重分 有重分配線路層3 0 圓20之銲墊23，接 填充方式形成複數 元件6 0係可為銲 該些導電元件60上 凸塊、金屬柱、彈 ，該些凸起電極T0 結構。 法及其結構，解決 或該晶圓2 0本身對 圓級封裝製程之凸 合等運用，同時， 裝結構之晶背保護 級晶片尺寸封裝結 面0 專利範圍所界定者Page 11 200423357 V. Description of the invention (6) Cover the back surface 22 of the wafer 20, and after 'the stage 8 1 continues to adsorb the crystal step 15, when the stage 8 丨 stops The stress buffer layer 40 and the warpage preventing layer 50 have good flatness, and then the “embossed electrode pattern” is used to perform a plurality of openings 41 using a development exposure or etching technique. In this embodiment, In the second end 32 of the middle distribution circuit layer 30, or in the case, the openings 41 are directly connected. 'Please refer to FIG. 3H, using electroplating. A conductive element 60 is used in the openings 41. The conductive resin or metal is bonded with a plurality of raised electrodes 70, such as conductive conductive bumps or needles, etc., which are illustrated by solder balls in this series to make a crystal. Therefore, the wafer according to the present invention is in crystal The stress of the wafer in the round-level packaging process affects the warpage of the wafer 20, which is beneficial for electrode formation, single-cut cutting, and handling of the warpage-preventing layer 50, which can be retained as the layer. 0 is the anti-warping layer 5 after the reconstruction, 0 0 still protects the protection scope of the present invention. 0, the package of 20 on the wafer will not be generated into step 16 to make the application, the opening, the exposure of the crystal, printing, or the conductive pillars, and the round level in the fresh ball, gold embodiment Package-level package square buffer layer 40 is used to form several wafer wafers on the back of the wafer and the surface. The process of applying step 15 for the formation of the warpage-preventing layer, but the protrusion is not convex. Severe warping of the electrode. 'First, please refer to the 3G force buffer layer 40. The formation of holes 41 reveals the redistributed redistribution circuit layer 30. The pads 23 of the circle 20 are connected to form a plurality of components 60. The system 60 can be used to solder the conductive components 60. There are upper bumps, metal pillars, and springs, and these raised electrodes T0 structure. Method and its structure, to solve the application of the wafer 20 itself to the round-level packaging process, etc., and at the same time, the structure of the wafer back protection level wafer size packaging surface 0 defined by the patent scope
第12頁 200423357 五、發明說明（7) 為準，任何熟知此項技藝者，在不脫離本發明之精神和範 圍内所作之任何變化與修改，均屬於本發明之保護範圍。 200423357Page 12 200423357 V. Description of the invention (7) shall prevail. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention. 200423357
圓式簡單說明 【圖式簡單說明 第 1 第 2 圖： 圖： 習知晶圓級封裝結構之截面圖； 依照本發明之晶圓級封裝製程之流程示意 圓；及 第3A至3H圖··依照本發明之晶圓級封裝製程，所提供之 圓在各製程中之截面示意圖。 元件符號簡單說明： 11 提供一晶圓 形成一重分配線路層於該晶圓之正面 形成一應力緩衝層於該晶圓之正面 研磨該晶圓之背面 形成一防魅曲層於該晶圓之背面 形成複數個凸起電極於該應力緩衝層上 晶圓 21 正面 22 背面 銲墊 重分配線路層 31 第一端 32 第二端 應力緩衝層 41 開孔 防翹曲層 60 導電元件 70 凸起電極 載台 82 研磨頭 晶圓級封裝結 構 晶圓 111 正面 112 背面 電極 120 絕緣保護層 導電凸塊 131 導體柱 132 凸塊墊片 12 13 14 15 16 20 2 3 30 40 50 81 100 110 113 130Circular type simple explanation [Schematic illustration 1st 2nd figure: Figure: A cross-sectional view of a conventional wafer-level packaging structure; a schematic circle of a wafer-level packaging process according to the present invention; and Figures 3A to 3H. Invented wafer-level packaging process, the cross-section diagram of the circle provided in each process. Brief description of component symbols: 11 Provide a wafer to form a redistribution circuit layer, form a stress buffer layer on the front side of the wafer, grind the back side of the wafer, and form an anti-curvy layer on the back side of the wafer A plurality of bump electrodes are formed on the stress buffer layer. The wafer 21 front surface 22 back pads redistribute circuit layer 31 first end 32 second end stress buffer layer 41 hole anti-warping layer 60 conductive element 70 bump electrode Table 82 Grinding head Wafer level package structure