588422 五、發明說明（l) 【發明所屬之技術領域】 本發明係有關於一種晶圓級封裝方法，特別係有關於 一種防止凸起電極在晶背研磨過程損傷之晶圓級封裝製 程。 【先前技術】588422 V. Description of the invention (l) [Technical field to which the invention belongs] The present invention relates to a wafer-level packaging method, and more particularly, to a wafer-level packaging process that prevents bump electrodes from being damaged during wafer back grinding. [Prior art]
晶圓級封裝〔wafer levei packaging〕係為一種技 術先進之半導體封裝，在晶圓級封裝製程中，其係在一晶 圓上完成對多個晶片之封裝，再切割為個別之晶圓級晶片 尺寸封裝結構〔wafer level chip scale package〕，與 習知個別晶片封裝方式更具有低成本大面積封裝之特性， 而該些晶圓級晶片尺寸封裝結構係具有複數個凸起電極 〔bump elec t rode〕，如銲球或銅柱，而被要求直接表面 接合至外部印刷電路板，但習知印刷電路板之熱膨脹係數 係遠大於半導艘晶片，為了消除在接合界面處凸起電極之 應力作用’習知在該些凸起電極與該晶片之間係形成有一 具有適當厚度之應力緩衝層〔如聚亞醯胺〕，其厚度約在 80〜160微米，用以減輕對該些凸起電極之應力，防止因金 屬疲勞〔metal fatigue〕可能引起凸起電極之斷損，為 了達到被小溥化’在晶圓級封裝製程中需要適當研磨晶 背，導致該些凸起電極常在研磨過程中損傷。 我國專利公告第516116號「凸起封裝晶圓之背面研磨 製程」’揭示有一種凸起封裝晶圓之背面研磨製程，其係 在晶圓形成好凸塊之後，在該晶圓之具凸塊表面係形成有 一有機材料層並黏附一膠帶，再對該晶圓之背面進行研[Wafer level package wafer levei packaging system] as a technique of advanced semiconductor package, wafer level packaging process, which is based on complete packaging a plurality of wafer, and then cut into individual wafer level of a wafer on the wafer The size package structure (wafer level chip scale package) has the characteristics of low cost and large area packaging with the conventional individual chip packaging methods, and these wafer level chip scale package structures have a plurality of bump electrodes [bump elec t rode ], Such as solder balls or copper pillars, which are required to be directly surface-bonded to external printed circuit boards, but the thermal expansion coefficient of conventional printed circuit boards is much larger than that of semi-conductor wafers. 'It is known that a stress buffer layer (such as polyimide) with an appropriate thickness is formed between the raised electrodes and the wafer, and the thickness is about 80 ~ 160 microns to relieve the raised electrodes. Stress to prevent possible breakage of the bump electrode due to metal fatigue. In order to achieve miniaturization, it is necessary to adapt the wafer-level packaging process. Grinding the backside, the plurality of projecting electrodes often cause damage during grinding. China Patent Bulletin No. 516116 "Backside grinding process for bump packaged wafers" discloses a backside grinding process for bump packaged wafers, which is formed after bumps are formed on the wafer. The surface is formed with an organic material layer and an adhesive tape is adhered, and then the back surface of the wafer is studied.
588422 五、發明說明（2) ----- 磨’利用熱處理揮發去除該有機材料層，而使該膠帶完全 剝離該晶圓之背面，使得該晶圓之具凸塊表面不會殘留有 ，附之膠帶’而在每一片晶圓之製造過程，均需要耗用一 定數量之有機材料層與膠帶，該膠帶在黏附該具凸塊表面 之後’已具有複數個凹陷部，無法再次被使用。 【發明内容】 本發明之主要目的係在於提供一種晶圓級封装製程， 其特徵係在於，用以形成複數個凸起電極之光阻層係保留 於一晶背研磨步驟，而在晶背研磨步驟中藉由該光阻層保 護該些凸起電極，在研磨之後方移除該光阻層，省卻額外 之凸起電極保護裝置〔例如有機材料層與膠帶〕，達到有 效率且低成本保護凸出電極，而不致於晶背研磨步驟中損 傷。 本發明之次一目的係在於提供一種晶圓級封裝製程， 其特徵係在於，用以形成複數個凸起電極之光阻層係保留 於一晶背研磨步驟，且在研磨之後，形成一防翹曲層於一 晶圓之背面，用以修正一應力緩衝層對該晶圓之翹曲度， 最後方移除該光阻層，使得該晶圓與該些凸起電極在晶圓 ^級封裝製程中有較佳之保護。 依本發明之晶圓級封裝製程，其包含之步驟有： 提供一晶圓，該晶圓係具有一正面、一背面以及複數 個設於該正面之銲墊，較佳地，該晶圓之正面更形成有一 重分配線路層〔redistribution wiring layer〕； 形成一應力緩衝層於該晶圓之正面； 588422 五、發明說明（3) 形成一光 個開孔； 形成複數 電極係電性連 研磨該晶 層，較佳地， 面，用以修正 移除該光 在移除該光阻 【實施方式】 參閱所附 請參閱第 圓級封裝製程 「形成一重分 力緩衝層於該 緩衝層」1 4、 、「研磨該 圓之背面」1 7 極」19等步驟 面」13、 「形 該些凸起電極 驟’其詳述如 依本發明 該步驟11中， 阻層於該應力緩衝 曰 且该光阻層具有複數 個凸起電極於該光阻層 接至對應銲墊； 省孔，且該些凸起 圓之背面，其中該曰圓你/ 在研磨之I，形成一防翹：持覆蓋有該光阻 該具有應力緩衝層之晶：：：晶圓之背 a β 日〜日日圓之翹曲度；及 L層二貝露*該些凸起電⑯，如有需要， 層之後，回銲該些凸起電極。 圖式，本發明將列舉以下之實施例說明。 1圖，依本發明之一具體實施例所例舉之晶 ’其包含之步驟有：「提供一晶圓」u、 配線路層於該晶圓之正面」12、「 晶圓之正面」13、「形成一光阻層=應： 形成複數個凸起電極於該光阻層之開孔」 晶圓之背面」16、「形成一防翹曲層於該晶 、「移除該光阻層」18及「回銲該些凸起電 ，其中「形成一應力緩衝層於該晶圓之正 成一防翹曲層於該晶圓之背面」17及「回銲 」1 9係為本實施例之具體較佳而非必要步 后。 之晶圓級封裝製程，首先請參閱第2A圖，在 所提供之晶圓20係具有一正面21、一背面22588422 5. Description of the invention (2) ----- Grinding removes the organic material layer by heat treatment and volatilization, so that the tape completely peels off the back of the wafer, so that the bumped surface of the wafer will not remain, Attached tape 'and in the manufacturing process of each wafer, a certain amount of organic material layer and tape are required. After the tape is adhered to the surface of the bump, the tape already has a plurality of depressions and cannot be used again. SUMMARY OF THE INVENTION The main object of the system of the present invention is to provide a wafer-level packaging process, characterized in that the system for forming a plurality of bump electrodes of a photoresist layer based on a reservation back grinding step, and in the back grinding In the step, the protruding electrodes are protected by the photoresist layer, and the photoresist layer is removed after grinding, eliminating the need for additional protruding electrode protection devices (such as organic material layers and adhesive tapes) to achieve efficient and low-cost protection. The electrodes are protruded without being damaged during the back grinding process. A second object of the present invention is to provide a wafer-level packaging process, which is characterized in that the photoresist layer used to form a plurality of raised electrodes is retained in a crystal back grinding step, and after the grinding, a protection layer is formed. The warped layer is on the back of a wafer, and is used to correct the warpage of a stress buffer layer to the wafer. Finally, the photoresist layer is removed, so that the wafer and the raised electrodes are at the wafer level. Better protection in the packaging process. The wafer-level packaging process according to the present invention includes the steps of: providing a wafer having a front surface, a back surface, and a plurality of pads disposed on the front surface. Preferably, the wafer A redistribution wiring layer is formed on the front surface; a stress buffer layer is formed on the front surface of the wafer; 588422 V. Description of the invention (3) A light opening is formed; a plurality of electrodes are formed by electrically polishing A crystal layer, preferably, a surface, is used to correct the removal of the light and the removal of the photoresist. [Embodiment] Please refer to the appendix. Please refer to the round-level packaging process "forming a heavy component buffer layer on the buffer layer" 1 4 ", Grinding the back side of the circle", "7 poles", "19 and other step surfaces" 13, "shape the raised electrodes" as detailed in step 11 according to the present invention, the resistance layer is in the stress buffer and the a photoresist layer having a plurality of projections on the electrode pad to the corresponding photoresist layer; province hole and the back surface of the plurality of circular projections, wherein the said circle you / polishing of I, forming an anti-Alice: holding cover With the photoresist, it should have a stress buffer layer Crystal ::: warpage of the wafer a β day to Japanese yen; and L-layer two bellows * the raised electrodes, if necessary, back solder the raised electrodes after the layer. , the present invention will include the following description of the embodiment of FIG. 1, under this embodiment of the invention one specific embodiment exemplified the grain 'has the steps comprising: "providing a wafer" u, with the wiring layer on the wafer "Front side" 12, "Front side of the wafer" 13, "Forming a photoresist layer = should: form a plurality of raised electrodes in the openings of the photoresist layer" Back side of the wafer "16," Forming a warpage prevention layer In the crystal, "remove the photoresist layer" 18 and "resolder the bumps, in which" a stress buffer layer is formed on the wafer and a warpage prevention layer is formed on the back of the wafer "17 and "Resoldering" 19 is a specific and preferred step of this embodiment, but not an essential step. Wafer-level packaging process, first refer to Figure 2A. The wafer 20 provided has a front surface 21 and a back surface 22
第9頁 588422 五、發明說明（4) 以及複數個設於該正面21之銲墊23，該些銲墊23係配設於 該晶圓2 0之每一晶片區域，如中央排列、周邊排列或矩陣 挑列’在本實施例中，該些銲墊23係對應於每一晶片區域 而為中央排列，該晶圓2 0係可包含有複數個記憶體、顯示 器驅動器、微處理器或圖形處理器等等，該晶圓2〇之尺寸 係為4至12吋，而該晶圓20之厚度約在500〜750微米，較佳 地’在晶圓提供步驟11之後，另包含有一重分配線路層形 成步驟12，請參閱第2B圖，其係利用濺鍍或電鍍技術在該 晶圓20之正面21形成一金屬層，在將該金屬層顯影蝕刻為 一重分配線路層 30〔redistribution wiring layer， RDL〕’該重分配線路層30之第一端31係連接至對應銲墊 2 3 ’而該重分配線路層3 〇之第二端3 2係矩陣排列於該晶圓 20正面21之每一晶片區域。 之後，執行該應力緩衝層形成步驟13，請參閱第2C 圖’利用旋塗〔spin coating〕、印刷或貼附方式將一如 聚亞醯胺或矽膠等材質之應力緩衝層4〇形成於該晶圓2〇之 正面21 ’該應力緩衝層4〇之厚度係約為50〜300微米，在本 實施例中’該應力緩衝層4 〇係全面覆蓋該晶圓2 〇之正面21 及該重分配線路層30，並請參閱第2D圖，利用曝光蝕刻技 術，使該應力緩衝層40形成有複數個開孔41，在本實施例 中’該些開孔41係顯露該重分配線路層3〇之第二端32，或 者’在不具有重分配線路層3〇之狀況下，該些開孔41係直 接顯露該晶圓2 0之銲墊2 3，並利用電鍵、印刷或填充方式 形成複數個導電元件42於該些開孔41，該些導電元件42係Page 9 588422 5. Description of the invention (4) and a plurality of pads 23 provided on the front surface 21, the pads 23 are arranged on each wafer area of the wafer 20, such as a central arrangement and a peripheral arrangement Or matrix picking 'In this embodiment, the pads 23 are arranged centrally corresponding to each chip area. The wafer 20 series may include a plurality of memories, a display driver, a microprocessor, or graphics. Processors, etc., the size of the wafer 20 is 4 to 12 inches, and the thickness of the wafer 20 is about 500 ~ 750 microns, preferably after the wafer providing step 11, a redistribution is included. wiring layer forming step 12, see FIG. 2B, which is based by sputtering or electroplating techniques to form a metal layer on the front side 20 of the wafer 21, the etching of the metal layer is developed to a redistribution wiring layer 30 [redistribution wiring layer , RDL] 'The first end 31 of the redistribution circuit layer 30 is connected to the corresponding pad 2 3' and the second end 3 2 of the redistribution circuit layer 30 is arranged in a matrix on the front surface 21 of the wafer 20 A wafer area. After that, the step 13 for forming the stress buffer layer is performed. Please refer to FIG. 2C. A spin buffer layer, printing or attaching is used to form a stress buffer layer 40 such as polyimide or silicone. Front surface 21 of wafer 20 'The thickness of the stress buffer layer 40 is approximately 50 to 300 micrometers. In this embodiment,' the stress buffer layer 40 'covers the front surface 21 of the wafer 20 and the weight The circuit layer 30 is allocated, and referring to FIG. 2D, the stress buffer layer 40 is formed with a plurality of openings 41 by using an exposure etching technique. In this embodiment, 'the openings 41 are exposed to the redistribution circuit layer 3' The second end 32 of 〇, or 'without a redistribution circuit layer 30, the openings 41 directly expose the pads 23 of the wafer 20, and are formed by means of electric keys, printing or filling. A plurality of conductive elements 42 are formed in the openings 41. The conductive elements 42 are
第10頁 588422 五、發明說明（5) 可為銲料、電鍍層、導電樹脂或金屬柱，並且在該些導電 兀件42上方結合有一金屬墊片43，以利接合對應之凸起電 極6 0〔如第2 F圖所示〕。Page 10 588422 V. Description of the invention (5) It can be solder, electroplated layer, conductive resin or metal pillars, and a metal gasket 43 is bonded above the conductive elements 42 to facilitate the bonding of corresponding raised electrodes 60. [As shown in Figure 2F].
之後’執行該光阻層形成步驟1 4，請參閱第2 E圖，利 用旋塗、印刷或貼附方式將一高厚度之光阻層5 〇形成於該 應力緩衝層40〔即該晶圓20之正面21上方〕，在本實施例 中，該光阻層50係可為一種感光型乾膜〔ph〇t〇sensitive dry film〕或是一種可旋塗成形之厚光阻劑，如 MICRO-CHEMICAL公司提供之SU-8系列厚光阻劑，該光阻層 50之厚度係依凸起電極6〇之需求形成量而介於5〇〜2〇〇微米 或更高，並以露光顯影技術使該光阻層5 〇形成有複數個開 .孔5 1 ’該些開孔51係對應於該重分配線路層3 〇之第二端 3 2 ’如在不具有重分配線路層3 〇之狀況下，該些開孔5丨係 對應於§亥晶圓20之鲜塾23。 之後，執行該凸起電極形成步驟15，首先請參閱第2F 圖，利用電鍍或印刷技術，使得在該光阻層5 〇之該些開孔 51係形成有複數個凸起電極60，如鉛錫合金、金或其合金 或其它銲料，於本實施例中，該些凸起電極6 〇係為鉛錫合 金之銲料，較佳地，對該些凸起電極60進行平坦化處理， 使得該些凸起電極60具有一致之高度。 之後，執行晶背研磨步驟16，請參閱第2G圖，其係先 將該晶圓20放置於一晶圓研磨設備之載台81，該載台81係 吸附該晶圓2 0上之光阻層50，使得該晶圓20平貼，並顯露 該晶圓20之背面22，然後，以該晶圓研磨設備之研磨頭82Afterwards, perform the photoresist layer forming step 14, see FIG. 2E, and use spin coating, printing or attaching to form a high thickness photoresist layer 50 on the stress buffer layer 40 (that is, the wafer). 21] over the front surface 20, in the present embodiment, the photoresist layer 50 may be based dry film as a photosensitive dry film ph〇t〇sensitive [A] or spin molding of thick photoresist coating, such as MICRO -SU-8 series thick photoresist provided by Chemicical Company. The thickness of the photoresist layer 50 is 50 ~ 200 microns or more according to the required formation amount of the raised electrode 60, and it is developed by exposure. The technology makes the photoresist layer 50 to form a plurality of openings. The holes 5 1 'the openings 51 correspond to the second end 3 2' of the redistribution circuit layer 3 0 'as in the absence of a redistribution circuit layer 3 0'. In this case, these openings 5 丨 correspond to 塾 23 of the wafer 20. Thereafter, a step of forming the bump electrode 15, first see FIG. 2F, by plating or printing techniques, such that a plurality of projections formed on the plurality of electrodes 60 in the openings 51 of the square-based photoresist layer 5, such as lead tin alloy, gold or a solder alloy or other, in the present embodiment, the plurality of projecting electrodes 6 square-based solder tin alloy, preferably, the projections of these electrodes 60 is planarized, so that the The bump electrodes 60 have a uniform height. After that, the wafer back grinding step 16 is performed. Please refer to FIG. 2G, which first places the wafer 20 on a stage 81 of a wafer polishing equipment, and the stage 81 absorbs the photoresist on the wafer 20 Layer 50, so that the wafer 20 is flat, and the back surface 22 of the wafer 20 is exposed, and then the polishing head 82 of the wafer polishing equipment is used.
第11頁 588422 五、發明說明（6) 研磨薄化該晶圓20之背面22，在該晶背研磨步驟中，該晶 圓係保持復蓋有該光阻層5〇，藉由該光阻層50保護該些 凸起電極60不在研磨過程中損傷，而在研磨之後，該晶園 20之厚度約介於5 0〜300微米。如有需要，接著，在同一研 磨載台81上執行該防翹曲層形成步雜17，請參閱第2jj圖， 利用旋塗、印刷或貼附方式將一如聚亞醯胺等具高熱膨脹 係數材質或者是如銅片等高硬度材質之防翹曲層7〇形成於 δ亥晶圓2 0之背面2 2，較佳地，該防麵曲層7 0之固化收縮率 係不小於該應力緩衝層4 〇之固化收縮率，該防翹曲層7 〇之 厚度係介於50〜3 0 0微米為較佳，該防翹曲層7〇之厚度設計 係依該防麵曲層7 0之固化收縮率、該晶圓2 〇内部積艘電路 殘留應力及該應力緩衝層40之固化收縮率與厚度之不同而 不同，用以修正該應力緩衝層4〇對該晶圓20之翹曲度，在 本實施例中，該防翹曲層7 〇係全面覆蓋該晶圓2 〇之背面 22 ’且在該防翹曲層形成步驟17之過程中，該載台81係持 續吸附該晶圓20 ’在該防勉曲層形成步驟I?之後，當該載 台81停止對該晶圓20之平貼吸附，該具有應力緩衝層4〇與 防翹曲層7 0之已封裝卻未有凸起電極之晶圓2 〇係具有良好 之收縮平衡，不會產生嚴重之翹曲。 在晶背研磨步驟1 6之後，執行光阻層移除步驟1 8，請 參閱第2 I圖，利用光阻去除劑〔如過氧一硫酸、發煙硝酸 或丁酮等等〕或電漿去光阻技術，將附著於該晶圓2 〇之光 阻層5 0加以移除，使得該些凸起電極6 〇顯露出，此外，當 遠些凸起電極60係由可回銲之銲料構成時，執行一回銲Page 11 588422 V. Description of the invention (6) Polishing and thinning the back surface 22 of the wafer 20, during the wafer back grinding step, the wafer is kept covered with the photoresist layer 50, and by the photoresist The layer 50 protects the raised electrodes 60 from being damaged during the grinding process. After the grinding, the thickness of the crystal garden 20 is about 50˜300 μm. If necessary, then, the warpage preventing layer forming step 17 is performed on the same polishing stage 81. Please refer to FIG. 2jj, using a method such as spin coating, printing, or attaching, such as polyurethane with high thermal expansion. An anti-warping layer 70 of a coefficient material or a high-hardness material such as a copper sheet is formed on the back surface 22 of the delta wafer 20, and preferably, the curing shrinkage of the anti-curving layer 70 is not less than that. The curing shrinkage of the stress buffer layer 40, the thickness of the warpage prevention layer 70 is preferably between 50 and 300 microns, and the thickness design of the warpage prevention layer 70 is based on the warpage prevention layer 7. The curing shrinkage ratio of 0, the residual stress of the internal circuit of the wafer 20, and the curing shrinkage ratio and thickness of the stress buffer layer 40 are different, which are used to correct the warpage of the stress buffer layer 40 on the wafer 20. Curvature. In this embodiment, the warpage prevention layer 70 covers the back surface 22 ′ of the wafer 20 completely, and the stage 81 continuously absorbs the warpage during the warpage prevention layer formation step 17. After the wafer 20 ′ is formed in the anti-buckling layer forming step I, when the stage 81 stops the flat bonding of the wafer 20, 4〇 having a stress buffer layer and the warpage preventing layer 70 has not been encapsulated wafers electrodes 2 square projection system having a good balance of shrinkage, warpage of no serious. After the wafer back grinding step 16, perform the photoresist layer removal step 18, see FIG. 2I, using a photoresist remover (such as peroxymonosulfuric acid, fuming nitric acid or methyl ethyl ketone, etc.) or a plasma The photoresist removal technology removes the photoresist layer 50 attached to the wafer 20, so that the bump electrodes 60 are exposed. In addition, when the bump electrodes 60 are distant from solder that can be reflowed When constructed, perform a reflow
第12頁 588422 五、發明說明（7) 〔 ref lowing〕步驟19，利用一加熱溫度回銲該些凸起電 極60’使得該些凸起電極6〇呈球狀〔請參閱第2J圖〕。 因此’依據本發明之晶圓級封裝製程，達到了在晶圓 級封裝製程中以該光阻層5〇低成本保護該些凸起電極6〇之 功效，依本製程不需要耗用 能在該晶背研磨步驟1 6中有 電極，而不致損傷。 本發明之保護範圍當視 為準，任何熟知此項技藝者 圍内所作之任何變化與修改 額外之凸起電極保護材料，而 效率且低成本地保護該些凸出Page 12 588422 V. Description of the invention (7) [ref lowing] In step 19, the raised electrodes 60 'are re-soldered using a heating temperature to make the raised electrodes 60 spherical (see FIG. 2J). Therefore, according to the wafer-level packaging process of the present invention, the photoresist layer 50 can be used to protect the raised electrodes 60 at a low cost during the wafer-level packaging process. There are electrodes in the crystal back grinding step 16 without damage. The protection scope of the present invention shall prevail, any changes and modifications made by those skilled in the art will be provided with additional raised electrode protection materials, which can efficiently and cost-effectively protect the protrusions.
後附之申請專利範圍所界定者 ’在不脫離本發明之精神和範 ’均屬於本發明之保護範圍。Those defined by the scope of the appended patent application ‘without departing from the spirit and scope of the present invention’ all belong to the protection scope of the present invention.
釅 第13頁 588422 圖式簡單說明 【圖式簡單說明 第1 圖 ••依照本發明之晶圓級封裝製程之流程示意 圖；及 ‘ 第2 A至2 J圖·依照本發明之晶圓級封裝製程，所提供之 圓在各製程中之截面示意圖。 元件符號簡單說明·· 11 提供一晶圓 12 形成一重分配線路層於該晶圓之正面 13 形成一應力緩衝層於該晶圓之正面 14 形成一光阻層於該應力緩衝層 15 形成複數個凸起電極於該光阻層之開孔 16 研磨該晶圓之背面 17 形成一防翹曲層於該晶圓之背面 18 移除該光阻層 19 回銲該些凸起電極 20 晶圓 21 正面 22 背面 23 銲墊 30 重分配線路層 31 第一端 32 第二端 40 43 應力緩衝層 金屬墊片 41 開孔 42 導電元件 50 光阻層 51 開孔 60 凸起電極 70 防翹曲層 81 研磨載台 82 研磨頭588Page 13 588422 Brief description of the drawings [Schematic description of the first Figure 1 •• Flow diagram of the wafer-level packaging process according to the present invention; and 'Figures 2 A to 2 J · Wafer-level packaging according to the present invention Manufacturing process, cross-section diagram of the circle provided in each manufacturing process. Brief description of the component symbols ... 11 Provide a wafer 12 Form a redistribution circuit layer on the front side of the wafer 13 Form a stress buffer layer on the front side of the wafer 14 Form a photoresist layer on the stress buffer layer 15 Form a plurality The raised electrode is in the opening of the photoresist layer. 16 The back surface of the wafer is ground. 17 An anti-warp layer is formed on the back surface of the wafer. The photoresist layer is removed. Front 22 Back 23 Pads 30 Redistribution circuit layer 31 First end 32 Second end 40 43 Stress buffer layer metal pad 41 Opening hole 42 Conductive element 50 Photoresist layer 51 Opening hole 60 Raised electrode 70 Anti-warping layer 81 Grinding stage 82