JP4095047B2 - ウエハレベルパッケージのチップ配置方法 - Google Patents
ウエハレベルパッケージのチップ配置方法 Download PDFInfo
- Publication number
- JP4095047B2 JP4095047B2 JP2004209770A JP2004209770A JP4095047B2 JP 4095047 B2 JP4095047 B2 JP 4095047B2 JP 2004209770 A JP2004209770 A JP 2004209770A JP 2004209770 A JP2004209770 A JP 2004209770A JP 4095047 B2 JP4095047 B2 JP 4095047B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- chips
- elastic material
- chip
- wafer level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims description 44
- 239000013013 elastic material Substances 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 19
- 239000000853 adhesive Substances 0.000 claims description 14
- 230000001070 adhesive effect Effects 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000011521 glass Substances 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 claims description 6
- 238000007639 printing Methods 0.000 claims description 6
- 238000004528 spin coating Methods 0.000 claims description 6
- 229920000800 acrylic rubber Polymers 0.000 claims description 3
- 229920000058 polyacrylate Polymers 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000002904 solvent Substances 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 description 17
- 238000004806 packaging method and process Methods 0.000 description 6
- 238000012360 testing method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000003908 quality control method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/5313—Means to assemble electrical device
- Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate
- Y10T29/53178—Chip component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/5313—Means to assemble electrical device
- Y10T29/53191—Means to apply vacuum directly to position or hold work part
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/53274—Means to disassemble electrical device
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/28—Web or sheet containing structurally defined element or component and having an adhesive outermost layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Adhesives Or Adhesive Processes (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Dicing (AREA)
Description
Claims (2)
- ウエハレベルパッケージのためのチップ配置方法であって、該方法が、
複数のチップをその裏面を上にして、スピンコーティング、プリンティングもしくは接着により第1基板上に形成され、前記複数のチップを付着するための通常状態において粘性を有し、DI水、溶媒もしくはUV光を含む特定環境において粘性を失う弾性材料上にピックアップ・配置システムにより配置する工程と、
スピンコーティングもしくはプリンティングにより接着材料が形成される第2基板を前記複数のチップの裏面と対向するように裏返し、前記接着材料を介して前記複数のチップの裏面を、前記第2基板上に接着する工程と、
前記複数のチップを、前記特定環境において前記弾性材料から剥離する工程と、
ウエハレベルパッケージを形成する工程と、
を含み、
前記弾性材料はシリコン樹脂、弾性PU、多孔質PU、アクリルゴム、もしくはダイソーイングテープ材料である、
チップ配置方法。 - 前記第1基板はシリコン、ガラス、水晶もしくはセラミックからなる基板であり、前記第2基板はシリコン、ガラス、水晶もしくはセラミックからなる基板、またはプリント基板もしくはリードフレームである、請求項1に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/842,959 US20050249945A1 (en) | 2004-05-10 | 2004-05-10 | Manufacturing tool for wafer level package and method of placing dies |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005322869A JP2005322869A (ja) | 2005-11-17 |
JP4095047B2 true JP4095047B2 (ja) | 2008-06-04 |
Family
ID=35238364
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004209770A Expired - Lifetime JP4095047B2 (ja) | 2004-05-10 | 2004-07-16 | ウエハレベルパッケージのチップ配置方法 |
Country Status (7)
Country | Link |
---|---|
US (2) | US20050249945A1 (ja) |
JP (1) | JP4095047B2 (ja) |
KR (1) | KR100590394B1 (ja) |
CN (1) | CN100372053C (ja) |
DE (1) | DE102004033645B4 (ja) |
SG (1) | SG129292A1 (ja) |
TW (1) | TWI240391B (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7400037B2 (en) * | 2004-12-30 | 2008-07-15 | Advanced Chip Engineering Tachnology Inc. | Packaging structure with coplanar filling paste and dice and with patterned glue for WL-CSP |
JP2007281264A (ja) * | 2006-04-10 | 2007-10-25 | Elpida Memory Inc | 半導体装置の製造方法 |
KR20110050547A (ko) * | 2008-09-01 | 2011-05-13 | 네덜란제 오르가니자티에 포오르 토에게파스트-나투우르베텐샤펠리즈크 온데르조에크 테엔오 | 픽앤드플레이스 장치 |
CN103187317B (zh) * | 2011-12-31 | 2015-08-05 | 百容电子股份有限公司 | 半导体元件的组装方法 |
EP2839522A4 (en) | 2012-04-20 | 2015-12-09 | Rensselaer Polytech Inst | LIGHT-EMITTING DIODES AND METHOD OF PACKAGING THEREOF |
CN103579069A (zh) * | 2012-07-20 | 2014-02-12 | 久元电子股份有限公司 | 晶粒取放方法、晶粒取放的承载结构、及晶粒取放装置 |
DE102015112518B3 (de) * | 2015-07-30 | 2016-12-01 | Asm Assembly Systems Gmbh & Co. Kg | Bestückmaschine und Verfahren zum Bestücken eines Trägers mit ungehäusten Chips |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1805174A1 (de) * | 1968-10-25 | 1970-05-14 | Telefunken Patent | Verfahren zum Aufbringen von Einzelkoerpern auf einen Grundkoerper |
DE3923023A1 (de) * | 1989-07-12 | 1991-01-24 | Siemens Ag | Uv-haertbarer klebstoff fuer ein halbleiterchipmontageverfahren |
US4941255A (en) * | 1989-11-15 | 1990-07-17 | Eastman Kodak Company | Method for precision multichip assembly |
JPH03181147A (ja) * | 1989-12-11 | 1991-08-07 | Casio Comput Co Ltd | ウェハのダイシング方法 |
JPH03212940A (ja) * | 1990-01-17 | 1991-09-18 | Rohm Co Ltd | リードフレームに対する半導体チップの供給方法 |
JP2682250B2 (ja) * | 1991-03-20 | 1997-11-26 | 株式会社村田製作所 | 電子部品チップ用ホルダおよび電子部品チップの取扱方法 |
JP3410202B2 (ja) * | 1993-04-28 | 2003-05-26 | 日本テキサス・インスツルメンツ株式会社 | ウェハ貼着用粘着シートおよびこれを用いた半導体装置の製造方法 |
US5474958A (en) * | 1993-05-04 | 1995-12-12 | Motorola, Inc. | Method for making semiconductor device having no die supporting surface |
JPH08107088A (ja) | 1994-10-04 | 1996-04-23 | Fujitsu Ltd | 半導体装置の製造方法 |
US5681757A (en) * | 1996-04-29 | 1997-10-28 | Microfab Technologies, Inc. | Process for dispensing semiconductor die-bond adhesive using a printhead having a microjet array and the product produced by the process |
DE19840226B4 (de) * | 1998-09-03 | 2006-02-23 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zum Aufbringen eines Schaltungschips auf einen Träger |
US6212767B1 (en) * | 1999-08-31 | 2001-04-10 | Micron Technology, Inc. | Assembling a stacked die package |
US6425971B1 (en) * | 2000-05-10 | 2002-07-30 | Silverbrook Research Pty Ltd | Method of fabricating devices incorporating microelectromechanical systems using UV curable tapes |
US6772510B1 (en) * | 2000-08-22 | 2004-08-10 | David J. Corisis | Mapable tape apply for LOC and BOC packages |
JP3906962B2 (ja) * | 2000-08-31 | 2007-04-18 | リンテック株式会社 | 半導体装置の製造方法 |
US6472728B2 (en) * | 2001-03-05 | 2002-10-29 | Delphi Technologies, Inc. | Condition sensitive adhesive tape for singulated die transport devices |
US6589809B1 (en) * | 2001-07-16 | 2003-07-08 | Micron Technology, Inc. | Method for attaching semiconductor components to a substrate using local UV curing of dicing tape |
TWI241674B (en) * | 2001-11-30 | 2005-10-11 | Disco Corp | Manufacturing method of semiconductor chip |
JP4211256B2 (ja) * | 2001-12-28 | 2009-01-21 | セイコーエプソン株式会社 | 半導体集積回路、半導体集積回路の製造方法、電気光学装置、電子機器 |
JP3553551B2 (ja) * | 2002-01-11 | 2004-08-11 | 沖電気工業株式会社 | 半導体ウェハを用いた半導体装置の製造方法 |
CN1215541C (zh) * | 2002-03-20 | 2005-08-17 | 育霈科技股份有限公司 | 一种晶片型态封装及其制作方法 |
US7535100B2 (en) * | 2002-07-12 | 2009-05-19 | The United States Of America As Represented By The Secretary Of The Navy | Wafer bonding of thinned electronic materials and circuits to high performance substrates |
DE10234951B4 (de) * | 2002-07-31 | 2009-01-02 | Qimonda Ag | Verfahren zur Herstellung von Halbleiterschaltungsmodulen |
US6848162B2 (en) * | 2002-08-02 | 2005-02-01 | Matrics, Inc. | System and method of transferring dies using an adhesive surface |
CN1298046C (zh) * | 2002-08-21 | 2007-01-31 | 南茂科技股份有限公司 | 在晶粒表面形成结合粘性的晶圆处理方法 |
US6780733B2 (en) * | 2002-09-06 | 2004-08-24 | Motorola, Inc. | Thinned semiconductor wafer and die and corresponding method |
US6777267B2 (en) * | 2002-11-01 | 2004-08-17 | Agilent Technologies, Inc. | Die singulation using deep silicon etching |
KR100486290B1 (ko) * | 2002-12-23 | 2005-04-29 | 삼성전자주식회사 | 반도체 패키지 조립방법 및 반도체 패키지 공정의보호테이프 제거장치 |
US7244326B2 (en) * | 2003-05-16 | 2007-07-17 | Alien Technology Corporation | Transfer assembly for manufacturing electronic devices |
TWI236058B (en) * | 2004-08-06 | 2005-07-11 | Touch Micro System Tech | Method of performing double side processes upon a wafer |
-
2004
- 2004-05-10 US US10/842,959 patent/US20050249945A1/en not_active Abandoned
- 2004-05-25 TW TW093114832A patent/TWI240391B/zh not_active IP Right Cessation
- 2004-06-04 SG SG200403353A patent/SG129292A1/en unknown
- 2004-06-30 KR KR1020040050088A patent/KR100590394B1/ko active IP Right Grant
- 2004-07-12 DE DE102004033645A patent/DE102004033645B4/de not_active Expired - Fee Related
- 2004-07-13 CN CNB200410063849XA patent/CN100372053C/zh not_active Expired - Fee Related
- 2004-07-16 JP JP2004209770A patent/JP4095047B2/ja not_active Expired - Lifetime
-
2005
- 2005-06-20 US US11/158,167 patent/US7985626B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US7985626B2 (en) | 2011-07-26 |
TW200537665A (en) | 2005-11-16 |
DE102004033645B4 (de) | 2006-08-31 |
US20050249945A1 (en) | 2005-11-10 |
KR20050107720A (ko) | 2005-11-15 |
DE102004033645A1 (de) | 2005-12-15 |
US20050247398A1 (en) | 2005-11-10 |
CN100372053C (zh) | 2008-02-27 |
CN1697125A (zh) | 2005-11-16 |
SG129292A1 (en) | 2007-02-26 |
TWI240391B (en) | 2005-09-21 |
JP2005322869A (ja) | 2005-11-17 |
KR100590394B1 (ko) | 2006-06-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7476565B2 (en) | Method for forming filling paste structure of WL package | |
KR100572525B1 (ko) | 플립 칩 반도체 장치를 제조하는 방법 | |
US6653731B2 (en) | Semiconductor device and method for fabricating same | |
US6710454B1 (en) | Adhesive layer for an electronic apparatus having multiple semiconductor devices | |
KR100517075B1 (ko) | 반도체 소자 제조 방법 | |
JP3553551B2 (ja) | 半導体ウェハを用いた半導体装置の製造方法 | |
US20090230567A1 (en) | Method of post-mold grinding a semiconductor package | |
TW200818350A (en) | Semiconductor packaging method by using large panel size | |
US7985626B2 (en) | Manufacturing tool for wafer level package and method of placing dies | |
JP2002093830A (ja) | チップ状電子部品の製造方法、及びその製造に用いる疑似ウェーハの製造方法 | |
US6680221B2 (en) | Bare chip mounting method and bare chip mounting system | |
JP4276535B2 (ja) | 信号処理装置を製造する方法 | |
US20080142939A1 (en) | Tools structure for chip redistribution and method of the same | |
KR100355744B1 (ko) | 반도체 패키지 구조 | |
JP2001267342A (ja) | 半導体装置の製造方法 | |
JP2009027127A (ja) | 大型パネルサイズ採用による半導体パッケージ製造方法 | |
KR101081735B1 (ko) | 엘. 오. 씨(loc) 다이접착 장비를 이용한 플립 칩 패키지 제조방법 및 이에 의한 플립 칩 패키지 | |
JP2002252308A (ja) | 半導体装置の製造方法および半導体装置 | |
JP2003203938A (ja) | チップ状電子部品の製造方法、並びにその製造に用いる疑似ウェーハの製造方法 | |
KR20070040538A (ko) | 보호 수단을 이용한 반도체 칩 분리 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20070125 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070130 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20070427 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20070507 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070524 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070619 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070919 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20071016 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20080116 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20080121 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080131 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20080226 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080306 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110314 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4095047 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120314 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120314 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130314 Year of fee payment: 5 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140314 Year of fee payment: 6 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |