JP2001267342A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JP2001267342A
JP2001267342A JP2000080753A JP2000080753A JP2001267342A JP 2001267342 A JP2001267342 A JP 2001267342A JP 2000080753 A JP2000080753 A JP 2000080753A JP 2000080753 A JP2000080753 A JP 2000080753A JP 2001267342 A JP2001267342 A JP 2001267342A
Authority
JP
Japan
Prior art keywords
substrate
resin
semiconductor
semiconductor device
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000080753A
Other languages
English (en)
Inventor
Takashi Hosaka
俊 保坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2000080753A priority Critical patent/JP2001267342A/ja
Priority to US09/941,146 priority patent/US6528354B1/en
Publication of JP2001267342A publication Critical patent/JP2001267342A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

(57)【要約】 【課題】 ＩＣチップと同じ大きさで品位の高いＩＣパ
ッケージの提供。 【解決手段】 半導体チップを保護するための樹脂を覆
う工程で、半導体チップを搭載している側と反対の基板
側にも樹脂を付着する。

Description

【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は多数の半導体チップ
を基板に搭載するＩＣパッケージを形成する方法に関す
る。
【０００２】
【従来の技術】多数の半導体チップを基板に搭載しその
半導体チップを保護するために樹脂で半導体チップを覆
い、その後に個個の半導体パッケージに分割する場合に
おいて、従来は図２に示すように基板の一方にだけ樹脂
を付着するため基板が反ってしまう。
【０００３】
【発明が解決しようとする課題】図２に示すように基板
の一方側だけに樹脂を付着させているため基板が片側に
反ってしまう。このためその後の工程においてこの反り
を考慮して作業する必要がある。たとえば、基板をマガ
ジンに搭載する時には上下の基板同士が接触しないよう
にスペースを充分にとるとか、基板検査の時に顕微鏡の
焦点をいちいち合せていくとか余分な手間がかかってい
た。さらに、基板を切断し半導体パッケージにする時に
この反り分を考慮しなければならず精度よく切断できな
い。
【０００４】
【課題を解決するための手段】上記の問題点を解決する
ために、本発明は基板に搭載された半導体チップを樹脂
で覆うときに、基板の反対側も樹脂を付着する。これに
より基板にはその両側から樹脂の応力が同程度にかかる
ので応力が相殺されてしまうので基板は反らない。この
半導体チップと反対側に付着した樹脂は基板を切断する
前に除去する。
【０００５】
【発明の実施の形態】本発明は、多数のチップを基板に
搭載し半導体チップを樹脂で覆い半導体パッケージに分
割する半導体装置の製造法において、基板を反らないよ
うにするための技術に関するものである。以下にこの発
明の実施例を図面に基づいて説明する。図１は、本発明
の製造方法を示す図である。図１(ａ)は基板１１上に半
導体チップ１２を搭載し基板１１内の配線１４と半導体
チップ１２とを金属配線１９にて接続している状態を示
す断面図である。基板として、ガラスエポキシ基板、セ
ラミック基板、ポリイミド基板などが挙げられる。次に
図１(ｂ)に示すように、金型１７に基板１１を入れて樹
脂１５、１５'を流し込み固化する。従来は半導体チッ
プ１２のある側にだけ樹脂を付着させていたが、本発明
では基板１１の表裏の両側に樹脂１５、１５'を流し込
む。この時半導体チップ１２のない側にはテープ１６を
基板１１と樹脂１５'の間にはさむ。樹脂１５、１５'が
固化した後で金型１７をはずす。
【０００６】図１(ｃ)は、基板１１の表裏を樹脂１５、
１５'で覆った状態を示す。次に図１(ｄ)に示すよう
に、半導体チップのある側の樹脂１５の面をダイシング
テープ１８に貼り付ける。基板１１は反っていないため
容易にダイシングテープ１８に貼りつく。
【０００７】次にテープ１６を基板１１から剥がす。こ
の時テープ側の樹脂１５'も一緒に剥がれる。この剥が
した後の状態が図１(ｅ)である。
【０００８】この後にダイシングで基板を切断し、図１
(ｆ)に示すように、基板１１、樹脂１５および外部電極
20からなる半導体パッケージができる。
【０００９】
【発明の効果】以上、説明したように半導体チップの搭
載している側ばかりではなく反対側にも樹脂を付着して
いるので、基板が反ることもなくその後の工程の作業を
容易に問題なく進めることができる。特に基板切断する
前にダイシングテープに貼る作業が簡単であり、完全に
ダイシングテープに密着させて貼ることができる。また
裏側の基板面と樹脂との間にはテープを挟んでいるの
で、ダイシングテープに基板を貼った後で、比較的容易
に裏側の樹脂を基板から除去することができる。尚基板
裏側のテープ及び樹脂は半導体パッケージにしてから剥
がすこともできる。
【図面の簡単な説明】
【図１】本発明の半導体装置の製造方法を示す図であ
る。
【図２】従来の半導体装置を示す図である。 １１、２１ 半導体基板 １２、 半導体チップ １４ 金属配線 １５、１５‘、２５ 樹脂 １６ テープ １７、１７‘ 金型 １８ ダイシングテープ １９ ダイシングリング ２０ 外部電極

Claims (2)

    【特許請求の範囲】
  1. 【請求項１】基板に多数の半導体チップを搭載し半導体
    チップを保護するための樹脂で覆う半導体装置の製造方
    法において、前記半導体チップを保護するための樹脂で
    覆う工程に前記半導体チップを搭載している側と反対の
    基板側にも樹脂を付着する工程を具備していることを特
    徴とする半導体装置の製造方法。
  2. 【請求項２】基板に多数の半導体チップを搭載し半導体
    チップを保護するための樹脂で覆う半導体装置の製造方
    法において、前記半導体チップを保護するための樹脂で
    覆う工程の前後に前記半導体チップを搭載している側と
    反対の基板側にも樹脂を付着する工程を具備しているこ
    とを特徴とする半導体装置の製造方法。
JP2000080753A 2000-03-22 2000-03-22 半導体装置の製造方法 Pending JP2001267342A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000080753A JP2001267342A (ja) 2000-03-22 2000-03-22 半導体装置の製造方法
US09/941,146 US6528354B1 (en) 2000-03-22 2001-08-28 Method of manufacturing a semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000080753A JP2001267342A (ja) 2000-03-22 2000-03-22 半導体装置の製造方法
US09/941,146 US6528354B1 (en) 2000-03-22 2001-08-28 Method of manufacturing a semiconductor device

Publications (1)

Publication Number Publication Date
JP2001267342A true JP2001267342A (ja) 2001-09-28

Family

ID=29272217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000080753A Pending JP2001267342A (ja) 2000-03-22 2000-03-22 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US6528354B1 (ja)
JP (1) JP2001267342A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006059416A1 (ja) * 2004-12-02 2006-06-08 Murata Manufacturing Co., Ltd. 複合材料振動装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10334576B4 (de) * 2003-07-28 2007-04-05 Infineon Technologies Ag Verfahren zum Herstellen eines Halbleiterbauelements mit einem Kunststoffgehäuse
CN111583795B (zh) * 2020-05-12 2022-03-08 Tcl华星光电技术有限公司 显示面板的制备方法及显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6066514A (en) * 1996-10-18 2000-05-23 Micron Technology, Inc. Adhesion enhanced semiconductor die for mold compound packaging
JP3199963B2 (ja) * 1994-10-06 2001-08-20 株式会社東芝 半導体装置の製造方法
NL1003315C2 (nl) * 1996-06-11 1997-12-17 Europ Semiconductor Assembly E Werkwijze voor het inkapselen van een geïntegreerde halfgeleiderschake- ling.
US6228688B1 (en) * 1997-02-03 2001-05-08 Kabushiki Kaisha Toshiba Flip-chip resin-encapsulated semiconductor device
US5914529A (en) * 1998-02-20 1999-06-22 Micron Technology, Inc. Bus bar structure on lead frame of semiconductor device package
US5933713A (en) * 1998-04-06 1999-08-03 Micron Technology, Inc. Method of forming overmolded chip scale package and resulting product
JP2002074985A (ja) * 2000-08-29 2002-03-15 Mitsubishi Electric Corp メモリモジュールおよびその製造方法ならびにそれに使用するテストコネクタ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006059416A1 (ja) * 2004-12-02 2006-06-08 Murata Manufacturing Co., Ltd. 複合材料振動装置

Also Published As

Publication number Publication date
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US6528354B1 (en) 2003-03-04

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