CN105514038B - 切割半导体晶片的方法 - Google Patents

切割半导体晶片的方法 Download PDF

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CN105514038B
CN105514038B CN201510669938.7A CN201510669938A CN105514038B CN 105514038 B CN105514038 B CN 105514038B CN 201510669938 A CN201510669938 A CN 201510669938A CN 105514038 B CN105514038 B CN 105514038B
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wafer
major surface
dies
passivation layer
film
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CN105514038A (zh
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尼尔逊·威廉·约翰
苏斯王孙逊·奈萨厐
何明永
王宝龙
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UTAC Headquarters Pte Ltd
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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Abstract

本发明公开一种分割晶片的方法。该方法包括提供具有第一主表面和第二主表面的晶片。晶片预备有多个裸片，该裸片位于主设备区域上，并由晶片的第一主表面上的分割通道彼此分开。在晶片的第一主表面或第二主表面上提供膜。该膜至少覆盖对应于主设备区域的区域。该方法还包括利用膜作为蚀刻掩模，通过晶片露出的半导体材料等离子蚀刻晶片，以形成空隙将所述晶片上的多个裸片分隔成多个单独裸片。

Description

切割半导体晶片的方法
相关申请的交叉引用
本申请要求美国临时申请号62062,967，申请日2014年10月13日，名称“切割半导体晶片的方法”的优先权，其公开内容通过引用全部合并于此用于各种目的。
背景技术
切割工艺，亦称作分割，通常用来分隔形成在晶片上的多个芯片。可采用各种各样的切割工艺来将形成在晶片上的多个芯片分隔成单个芯片用于封装。一种常用工艺为机械锯切。在机械锯切过程中，高速转动的金刚石锯沿锯道或分割通道将芯片彼此分隔。然而，由于刀口引起的机械应力，各芯片容易出现裂纹或碎屑。此外，采用机械锯切从整片晶片分隔芯片是非常耗费时间的。
为了缓解上述问题，已提出一种等离子蚀刻工艺用于切割或分割晶片。然而，我们发现，通常的等离子蚀刻工艺不能有效地从晶片分隔裸片，且切割的裸片还可能遭受由等离子蚀刻工艺引起的污染。通常的等离子蚀刻工艺还可导致切割的裸片的粗糙或不均匀的侧表面或侧壁。
有鉴于此，希望提供一种可靠、简单、高效、经济有效的方法，用于从晶片切割半导体芯片或裸片。
发明内容
一般地，实施例涉及半导体裸片的切割方法。在一个方面，公开一种分割晶片的方法。该方法包括提供具有第一主表面和第二主表面的晶片。晶片预备有多个裸片，该多个裸片位于主设备区域上，并被晶片第一主表面上的分割通道彼此分开。在晶片的第一主表面或第二主表面上提供膜。该膜至少覆盖对应于主设备区域的区域。该方法还包括利用膜作为刻蚀掩模，通过晶片露出的半导体材料等离子蚀刻晶片，以形成空隙将所述晶片上的多个裸片分隔成多个单独裸片。
这些实施例以及本文揭露的其他优点和特征，将通过结合下述描述和附图而显而易见。此外，应理解本文描述的各实施例不是互相排斥的，可存在于各种组合排列。
附图说明
附图中，相同的附图标记一般表示不同视图中的相同部件。另外，附图不一定是按比例绘制的，而是一般将重点放在说明本发明的原理上。在下述描述中，参照附图描述本发明的各实施例，其中：
图1示出半导体晶片的简化主视图；
图2a-2e、图3a-3b、图4a-4d和图5a-5d示出切割半导体晶片的工艺的各实施例。
具体实施方式
一般地，实施例涉及切割或分割半导体晶片的方法。本公开所描述的实施例涉及切割工艺中的等离子蚀刻工艺。本公开的实施例可应用于切割任何类型的晶片，包括对机械应力敏感的晶片，诸如其中具有低k和超低k材料的晶片。本公开中将描述的切割方法还可用于晶片级芯片尺寸封装(WLCSP)应用，其中进行晶片级封装之后执行分割。例如，所述芯片/裸片或封装可包括任何类型的集成电路(IC)，诸如存储设备、光电设备、逻辑设备、通信设备、数字信号处理器(DSP)、微控制器、系统集成芯片以及其他类型设备或其组合，其中存储设备包括动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)以及各种类型的非易失性存储器(包括可编程只读存储器(PROM)和闪存)。这些裸片/芯片或封装可并入电子产品或装备，诸如手机、电脑以及移动产品和移动智能产品。裸片也可用于并入其他类型产品。
图1示出半导体晶片110的简化主视图。例如，半导体晶片可为硅片。也可使用其他合适类型的晶片。例如，晶片可为p型或n型掺杂晶片。
参见图1，晶片包括第一表面110a，第一表面110a上形成有多个裸片/芯片115。该多个裸片/芯片可在晶片上并行形成。例如，裸片沿第一方向(x)的行和第二方向(y)的列布置。所示的晶片包括多个主设备区域122和框架(或周界)区域126。主设备区域包括半导体裸片或芯片的特征和互连件。主设备区域包括电路组件(未示出)，诸如晶体管、电阻器、电容器和互联件以形成裸片/芯片。对于周界区域，其围绕主设备区域。例如，周界区域不包含电路组件，并在晶片上用作划刻道或分割通道/道126。相邻的裸片/芯片由划刻道或分割通道彼此间隔或隔开。通过沿这些划刻道或分割通道分割晶片，裸片被彼此隔开。下文描述的各切割方法可用于从晶片分隔裸片。
图2a-2e示出从晶片切割半导体裸片或芯片的方法或工艺200的实施例。例如，晶片可类似于或同于如图1示出和描述的晶片110。照此，为了简洁起见，具有相同参考标记的共同元件或特征不描述或不详细描述。
图2a示出具有第一表面110a和第二表面110b的晶片110。晶片用作形成裸片或芯片的衬底。例如，第一表面110a为有源表面，而第二表面110b为无源表面或被动表面。晶片的有源表面是指其中定义集成电路的表面。晶片的被动表面是指其中定义集成电路的表面的背面。例如，晶片包括半导体晶片，诸如硅片。也可使用其他合适类型的半导体晶片。在一个实施例中，晶片经过处理，包括多个裸片或芯片115。例如，多个裸片在晶片上并行处理。裸片115包括形成在晶片或衬底的有源表面上的电路组件。例如，电路组件包括晶体管、电阻器、电容器和互联件以形成IC集成电路。多个裸片形成在晶片上，并由划刻道或分割通道/道彼此隔开。为了简化和说明的目的，如图2a所示的晶片，包括四个裸片1151-1154。应理解，晶片可包括不同合适数目的裸片位于其上。如所示，每个裸片1151-1154由分割通道/道126彼此隔开。
在晶片的有源表面上执行前端制程(FEOL)工艺以形成电路组件，执行后端制程(BEOL)工艺以形成互连件(如金属线或接触过孔)。如图2a所示，处理晶片110直到其中最终钝化膜或层131在晶片的有源表面上形成的阶段。例如，该最终钝化层包括聚酰亚胺，并可在晶片的有源表面上通过化学气相沉积(CVD)形成。也可采用其它合适的介电材料和技术来形成最终钝化层。在一个实施例中，钝化层132以不在分割通道/道126上延伸的方式形成。例如，这可通过掩模技术或蚀刻技术实现。例如，钝化层可沉积在晶片的有源表面上，分割通道上的钝化层部分可采用掩膜蚀刻技术通过蚀刻去除。可选地，当钝化层沉积在晶片上时，可提供掩模如光刻胶来覆盖分割通道。配置在掩模上的钝化层可与光刻胶一起去除，留下主设备区域的钝化层。也可使用其它适合的技术，使得钝化层设置在主设备区域的周界，而不延伸至对应于分割通道的周界区域。
根据需求，可在晶片的分割通道/道内形成一个或多个监测图案135。例如，该监测图案(monitoring pattern)包括用于在光刻工艺中保证晶片的精确对准的对准标记/图案，用于确认形成层是否实际具有所需厚度和尺寸的工艺控制模块(PCM)，或用于测量形成的电路组件的电学特性的试验元件组(TEG)。也可在分割通道内形成其它适合的监测图案。例如，监测图案包括金属材料，诸如铜。也可使用其他合适类型的金属材料。
在一个实施例中，晶片的有源表面110a上形成的最终钝化层132的开口(未示出)露出裸片接触垫(未示出)，该裸片接触垫上形成一排外部电接触件或裸片接触件170。裸片接触垫提供针对裸片的电路的连接件。例如，裸片接触垫由导电材料构成，诸如铜、铝、金、镍或其合金。其它类型的导电材料也可用于裸片接触垫。
在一个实施例中，晶片带有凸点，其外部接触件170具有在晶片的有源表面上形成的球状结构或球状物，如图2a所示。例如，外部接触件包括焊球。提供其它合适类型的外部接触件，诸如但不限于铜柱、带有焊料盖的铜柱、金柱凸块或其结合也是可行的。外部接触件提供电连接件，用于耦接外部设备(未示出)，诸如电路板。在其他实施例中，在该工艺阶段，晶片可不提供外部接触件。
晶片衬底110的一部分可以去除。在一个实施例中，部分晶片衬底可采用背面研磨工艺去除。这可通过将部分处理的晶片转移到支撑平台140来实现，如图2a所示。例如，支持平台可为背面研磨带。该部分处理的晶片布置在支撑平台上，使得晶片的有源表面110a面向支撑平台。由于背面研磨带的粘附特性，晶片的有源表面粘附到背面研磨带。如所示，外部接触件170附接并内嵌于背面研磨带。在一个实施例中，背面研磨带不延伸至晶片的边缘，使得晶片的有源表面的部分沿晶片的边缘露出。
处理晶片露出的第二表面110b。例如，该工艺从第二表面去除部分晶片衬底，并将晶片的厚度从起初的厚度T1减少至T2。在一个实施例中，晶片衬底的厚度通过机械研磨、化学蚀刻或其组合来减少。其它适合的技术也可用于去除部分晶片衬底，以减少晶片的厚度。在一个实施例中，晶片的厚度减少至厚度T2，约200-300μm。也可使用其他合适厚度尺寸。
参见图2b，提供在晶片的第二表面110a上形成的膜。在一个实施例中，该膜是背面保护层150。例如，背面保护层包括热塑性聚合物基树脂膜，其具有热固型粘性。背面保护层可以带状形式设置，并通过层压工艺施加于晶片的第二(或被动)表面110b。其它适合的材料和技术包括点胶、轧制等也可用于形成背面保护层。例如，背面保护层150包括约25μm的厚度。也可使用其他合适厚度尺寸。
在一个实施例中，该工艺继续到处理背面保护层150。如图2c所示，选择性地去除部分背面保护层，以露出晶片的第二(或被动)表面110b下面的部分。在一个实施例中，背面保护层配置在对应于晶片的有源表面上的分割通道/道的部分被去除。在一个实施例中，这些部分背面保护层可通过化学蚀刻、激光切除、机械锯切等去除。在一个实施例中，利用红外摄像机来识别和记录信息，诸如有源表面上的分割通道的位置、尺寸等，来引导工具(诸如激光束、金刚石切割轮)从被动表面去除部分背面保护层。也可采用其它合适技术，来确保覆盖对应于分割通道的区域的部分背面保护层被去除。
该工艺继续去除未被背面保护层保护而露出的晶片的半导体材料。如图2d所示，晶片放置在等离子蚀刻腔250内。该等离子蚀刻腔可为任何合适类型的等离子蚀刻腔。图2d示出等离子体蚀刻腔的简化视图。该等离子蚀刻腔包括第一(顶部)板和第二(底部)板，或电极252和254。顶部板和底部板均与电源256电耦接。电源可为DC直流电源。也可使用其它合适的电源来电性偏置顶部电极和底部电极。例如，底部电极254包括容纳具有背面研磨带140的晶片110的腔体。在一个实施例中，晶片布置在底部电极上，使得其有源表面110a面向并配置在底部电极254上，而其被动表面110b背向底部电极。如上所述，背面研磨带不延伸至晶片的边缘。这使得背面研磨带配置在底部电极的腔体内，而沿着晶片的边缘露出的晶片的有源表面的端部分配置在底部电极的突出端部分并与之接触，使得在后续的等离子蚀刻工艺中晶片偏置。亦可使用其它适合配置的底部电极以保持和偏置带有背面研磨带的晶片。
等离子蚀刻腔设有能够选择性地去除晶片的半导体材料的反应气体。利用的反应气体对于晶片的半导体材料例如硅具有高度选择性。反应气体通常为氟基气体，诸如SF6、C4F8、CHF3,XeF2或其它合适的对于晶片衬底的硅材料具有高度选择性的反应气体。电磁场(未示出)施加于底部电极。该电场电离反应气体的气体分子，产生蚀刻等离子258。如所示，蚀刻等离子在带有背面保护层150的晶片110上形成。在一个实施例中，等离子蚀刻或去除露出的未被背面保护层保护的晶片的半导体材料，如硅。因此，在等离子蚀刻工艺中，处理的背面保护层保护其下面的半导体材料，并还用作蚀刻掩模。如图2d所示，在一个实施例中，未被背面保护层覆盖而露出的晶片的半导体材料，利用等离子蚀刻工艺通过露出的被动表面110b去除。因此，由于露出的晶片的半导体材料的去除，形成空隙145。由于等离子蚀刻工艺对晶片的硅材料具有高度选择性，当抵达诸如背面研磨带或监测图案(如有的话)的非硅材料时，该等离子蚀刻工艺停止。因此，等离子蚀刻工艺在蚀刻空隙内露出的晶片衬底材料，直至硅材料被完全去除，以形成向下延伸至背面研磨带顶部的空隙或沟槽。例如，该空隙具有与分割通道相同的宽度，以及与晶片厚度T2相同的深度。
在一个实施例中，该工艺继续到提供具有顶部表面230a和底部表面230b的支撑托架230。该支撑托架可以为处理蚀刻的晶片的临时托架。该托架具有足够刚性，以在后续工艺中用作保持背面研磨带的临时支撑件。作为非限制性示例，支撑托架可为硅晶片、金属板等。各种适合类型的材料也可用于作为支撑托架。
在一个实施例中，通过将背面研磨带附接到支撑托架的第一或顶部表面230上，附接有背面研磨带的晶片被转移至临时托架，如图2e所示。背面研磨带由于其粘合特性而附接到临时托架。因此，不需要额外粘合剂将背面研磨带附接到支撑托架。在其它实施例中，可设置粘合层将具有背面研磨带的晶片附接到支撑托架。可使用各种合适类型的粘合剂，提供背面研磨带与支撑托架的临时粘结。
在一个实施例中，执行脱粘处理。该脱粘处理可造成背面研磨带失去或减少其粘合强度，以使得切割的裸片/芯片从背面研磨带分隔。例如，该脱粘处理包括温度或热处理。亦可使用其他类型的脱粘处理。脱粘处理取决于背面研磨带的类型。例如，脱粘处理可包括任何合适的处理，诸如热工艺，UV辐射或其结合。完全由等离子蚀刻工艺切断的各个裸片或芯片可通过拾放工具来拾取。在其它实施例中，背面研磨带可在施加于晶片的有源表面之前附接到晶片环(未示出)。在该情形中，在等离子蚀刻工艺后，晶片环和背面研磨带用作支撑托架。当裸片拾取后，监测图案135，诸如对准标记或图案、PCM或TEG，将留在在背面研磨带140的表面上。
图3a-3b示出从晶片切割或分割半导体裸片或芯片的工艺300的实施例。该工艺300可包括与如图2a-2e的工艺200中描述的类似工艺过程。为了简洁起见，具有相同参考标记的共同元件或特征可不描述或不详细描述。下面的描述主要集中于工艺300和工艺200的不同之处。
如图3a所示，在图2a描述的相同阶段处理晶片110。在一个实施例中，晶片110经过处理，包括多个裸片或芯片115。多个裸片在晶片上形成，并由划刻道或分割通道/道126彼此隔开。根据需求，监测图案135，诸如对准图案或标记、PCM和/或TEG，可在晶片的分割通道/道内形成。处理晶片110直到其中最终钝化层232在晶片的有源表面110a上形成的阶段。在一个实施例中，如图3a所示的钝化层232与如图2a所示的钝化层132的区别在于，钝化层232还以沿分割通道/道126延伸的方式形成。例如，该钝化层232可覆盖分割通道内配置的监测图案。
在一个实施例中，晶片为带有凸点的晶片，其外部接触件170具有球状结构或球状物，在晶片的有源表面上形成，如图3a所示。晶片布置在支撑平台140上，如背面研磨带上。如所示，晶片的有源表面110a面向支撑平台。外部接触件170附接并内嵌于背面研磨内140。与图2a描述类似，背面研磨带不延伸至晶片的边缘，使得晶片的有源表面的端部分沿晶片的边缘露出。
工艺300继续有额外过程，诸如图2b-2d所描述。例如，可执行背面研磨工艺来将晶片的起始厚度T1减少至厚度T2，在晶片的第二(被动)表面上设置背面保护层150并处理该背面保护层，使得设置在对应于晶片的有源表面上的分割通道/道的区域上的背面保护层部分被去除。额外工艺还包括执行等离子蚀刻工艺以去除晶片露出的半导体材料，如硅，其露出的被动表面不被背面保护层保护。这些额外工艺涉及与图2b-2d类似或相同的材料和技术，因而他们相应的描述在此不再赘述。
等离子蚀刻工艺对于晶片的硅材料具有高度选择性。照此，在一个实施例中，处理的背面保护层作为蚀刻掩模用于等离子蚀刻工艺。当抵达诸如钝化层232或监测图案(如有的话)的非硅材料时，该等离子蚀刻工艺停止。因此，等离子蚀刻工艺蚀刻空隙内露出的晶片衬底材料，直至硅材料被去除，以形成向下延伸直至其抵达钝化层和/或监测图案(如有的话)的表面。例如，该空隙具有与分割通道相同的宽度，以及与晶片厚度T2相同的深度。
在一个实施例中，通过将背面研磨带附接到支撑托架的第一或顶部表面230a上，附接有背面研磨带的晶片被转移至临时托架230，如图3b所示。可执行脱粘处理，使得背面研磨带失去其粘合性。完全由等离子蚀刻工艺切断的各个裸片或芯片可通过拾放工具来拾取。在一个实施例中，在裸片的拾取工艺中，钝化层232可被切断。例如，拾取工艺中的拉力造成钝化层232沿裸片的边缘或侧壁断裂，每个裸片芯片彼此切断钝化层。当裸片拾取后，监测图案135，诸如对准标记或图案、PCM或TEG，将留在在背面研磨带140的表面上。在另一实施例中，空气吹流或激光束的射流可通过在等离子蚀刻工艺中形成的空隙145施加于钝化层。例如，空气吹流或激光束的射流去除分割通道/道内露出的钝化层部分，使得每个芯片的钝化层彼此分隔。在其它实施例中，可在背面保护层150上设置额外带(未示出)，且背面研磨带140可通过适合的UV处理或热处理去除。当去除或剥离背面研磨钝化层时，钝化层可切断。这将每个芯片的钝化层彼此分隔。若额外带设置在背面保护层上，临时支架可仍附接在背面研磨带上。例如，该附接到背面研磨带的临时支架将在背面研磨带的剥离中一并去除。额外带可为分割带、金属板、半导体/陶瓷晶片等
图4a-4c示出从晶片切割半导体裸片或芯片的工艺400的另一个实施例。该工艺400可包括与如图2a-2e的工艺200和如图3a-3b的工艺300中描述的类似工艺过程。为了简洁起见，具有相同参考标记的共同元件或特征可不描述或不详细描述。下面的描述主要集中于工艺400和工艺200或工艺300的不同之处。
如图4a所示，在图3a描述的相同阶段处理晶片110。在一个实施例中，晶片110经过处理，包括多个裸片或芯片115。多个裸片在晶片上形成，并由划刻道或分割通道/道126彼此隔开。根据需求，监测图案135，诸如对准图案或标记、PCM和/或TEG，可在晶片的分割通道/道内形成。处理晶片110直到其中最终钝化膜或层在晶片的有源表面110a上形成的阶段。在一个实施例中，钝化层232也以在分割通道/道126上延伸的方式形成，如图3a所示。在其他实施例中，钝化层可以不在分割通道/道126上延伸的方式形成，类似于如图2a所示的钝化层132。
在一个实施例中，晶片为带有凸点的晶片，其外部接触件170在晶片的有源表面上形成，如图4a所示。例如，晶片可布置在诸如背面研磨带(未示出)的支撑平台上，并执行背面研磨工艺以减少晶片的初始厚度，类似于如图2a所描述。背面研磨工艺涉及与如图2a所示的技术，因而其对应描述在此不再赘述。
在支撑托架430上设置带有凸点的晶片110。例如，该支撑托架430由环或框架432固定，并用作处理带有凸点的晶片的临时托架。该托架应具有足够刚性，以用作临时支撑件，并在背面研磨带的去除中保持晶片。作为非限制性示例，支撑托架可为半导体/陶器的晶片、金属板等。各种适合类型的材料也可用于作为支撑托架。支撑托架包括顶部主表面430a和底部主表面430b。晶片110布置在支撑托架的顶部表面430a上。如所示，配置晶片使得晶片的第二(或无源)表面110b接触支撑托架的顶部表面430a，而晶片的第一(或有源)表面110a背离支撑托架，如图4b所示。支撑平台，如背面研磨带(未示出)，利用合适的脱粘处理除去。
在一个实施例中，该工艺继续到去除分割通道上的钝化层和监测图案部分(如有的话)，如图4b所示。在一个实施例中，这些钝化层和监测图案部分可通过非蚀刻技术去除，包括激光切除、低转速机械锯切等。也可使用其他合适类型的技术。这些用于钝化层和监测图案部分(如有的话)的非蚀刻技术可控制或减少后续粗糙/不平坦的侧表面或侧壁的形成。去除这些钝化层和监测图案部分露出下面晶片的半导体材料，如硅。在其他实施例中，这些钝化层和监测图案部分的去除也可去除晶片下面的半导体材料部分。
参见图4c，该工艺继续到布置晶片至离子蚀刻腔内。在一个实施例中，晶片布置在底部电极上，使得其被动表面110b面向并配置在底部电极254上，而其有源表面110a背向底部电极。例如，晶片110和支撑支架430布置在底部电极上。在该情形中，不同于如图2d所示的底部电极254的配置，底部电极254可具有平顶表面，如图4c所示。在一个实施例，执行等离子蚀刻工艺，通过晶片露出的有源表面110a来去除未被钝化层保护的半导体材料。在这种情形，主设备区域上配置的钝化膜或层作为蚀刻掩模，用于去除分割通道内的半导体材料的露出部分。等离子蚀刻工艺类似于图2d所示，因而其相应的描述在此不再赘述。
等离子蚀刻工艺对于晶片的硅材料具有高度选择性。照此，在一个实施例中，当抵达非硅材料如支撑件430时，该等离子蚀刻工艺停止。因此，等离子体蚀刻露出的晶片衬底材料，直至硅材料被去除，以形成向下延伸的直至其抵达支撑托架的表面的空隙或沟槽145。例如，该空隙具有与分割通道相同的宽度。参见图4d，完全由等离子蚀刻工艺切断的各个裸片或芯片配置在支撑托架430上，以待通过拾放工具(未示出)来拾取用于进一步工艺或封装。
图5a-5d示出从晶片切割半导体裸片或芯片的工艺500的一个实施例。该工艺500可包括与图2a-2e的工艺200中描述的类似工艺过程。为了简洁起见，具有相同参考标记的共同元件或特征可不描述或不详细描述。下面的描述主要集中于工艺500和工艺200的不同之处。
如图5a所示，类似于图2a所示来处理晶片110。在一个实施例中，晶片110经过处理，包括多个裸片或芯片115。多个裸片在晶片上形成，并由划刻道或分割通道/道126彼此隔开。根据需求，监测图案135，诸如对准图案或标记、PCM和/或TEG，可在晶片的分割通道/道内形成。处理晶片110直到其中最终钝化层532在晶片的有源表面110a上形成的阶段。在一个实施例中，钝化层532与如图3a所示的钝化层132类似的是，钝化层532以不在分割通道/道126上延伸的方式形成。
在一个实施例中，通过晶片衬底的有源表面110a上配置的最终钝化层形成的开口(未示出)露出裸片接触垫(未示出)。裸片接触垫适用于容纳或接纳接合线。例如，裸片接触垫由导电材料构成，诸如铜、铝、金、镍或其合金。其它类型的导电材料也可用于裸片接触垫。
晶片布置在支撑平台140上，如背面研磨带上。在一个实施例中，晶片位于支撑平台上，使得晶片的有源表面110a面向支撑平台。如图5a所示，由于背面研磨带的粘附特性，晶片的有源表面110a和钝化层532粘附到背面研磨带。与图2a描述类似，背面研磨带不延伸至晶片的边缘，使得晶片的有源表面的端部分沿晶片的边缘露出。
工艺500继续到处理晶片露出的第二表面110b。例如，利用如图2a所示和所描述的技术，该工艺继续去除部分晶片衬底，并将晶片的厚度从起初的厚度T1减少至T2。在一个实施例中，如图5b所示，在晶片的第二表面110b上提供并形成裸片接合膜550。例如，裸片接合膜550包括在后续工艺中，将切割的裸片粘合到引线框或封装衬底的待使用粘合材料。裸片接合膜550可以带状形式设置，并通过层压工艺施加于晶片的第二(或被动)表面110b。其它适合的材料和技术(包括点胶、轧制等)也可用于形成裸片接合膜。例如，裸片接合膜550包括约25μm的厚度。也可使用其他合适厚度尺寸。
在一个实施例中，该工艺继续到处理裸片接合膜550。如图5c所示，选择性地去除部分裸片接合膜，以露出晶片的第二(或被动)表面110b下面的部分。在一个实施例中，部分裸片接合膜配置在对应于去除晶片的有源表面上的分割通道/道的区域上。在一个实施例中，这部分裸片接合膜可通过化学蚀刻、激光切除、机械锯切等去除。在一个实施例中，利用红外摄像机来识别和记录信息，诸如位置、尺寸等。诸如有源表面上的分割通道的位置、尺寸等，来引导工具(诸如激光束、金刚石切割轮)，以从被动表面去除部分裸片接合膜。也可采用其它合适技术，来确保覆盖对应于分割通道的区域的裸片接合膜部分被去除。
在其他实施例中，裸片接合膜550可选择性地在对应于晶片的有源表面上的主设备区域上的晶片的被动表面110b的区域形成，而不延伸至对应于分割通道的晶片的被动表面区域。例如，这可在模板的协助下，通过印刷或喷涂工艺选择性地在主设备区域上形成裸片接合膜来实现。也可采用其他合适技术来选择性形成裸片接合膜。
该工艺继续到去除未被裸片接合膜保护的晶片而露出的半导体材料。在一个实施例中，执行等离子蚀刻工艺以去除晶片露出的半导体材料，诸如硅，其通过露出的被动表面不被裸片接合膜保护，如图5d所示。在这种情形下，等离子蚀刻工艺中，裸片接合膜保护其下面的晶片的半导体材料，并还用作蚀刻掩模。利用与那些如图2d类似的反应气体和技术，在离子蚀刻腔250内执行等离子蚀刻工艺，因而其相应的描述在此不再赘述。
等离子蚀刻工艺对于晶片的硅材料具有高度选择性。照此，在一个实施例中，当抵达非硅材料时，诸如支撑件钝化层或监测图案(如有的话)，该等离子蚀刻工艺停止。因此，等离子体在空隙内蚀刻晶片露出的衬底材料，直至硅材料被去除，以形成向下延伸直至其抵达背面研磨带和/或监测图案(如有的话)的表面。例如，该空隙具有与分割通道相同的宽度。
在一个实施例中，该工艺500继续到处理与图2e描述以及对应描述中的类似额外工艺。例如，利用图2e描述的技术，工艺继续去除背面研磨带。由等离子蚀刻工艺切割的裸片/芯片以待拾放工具来拾取。在其被动表面上具有裸片接合膜的裸片/芯片待被粘合到引线框或封装衬底，以用于后续工艺或封装。
关于图5a-5d描述的工艺500，示出钝化层不延伸至分割通道。在其他实施例中，可修改工艺500，使得钝化层与图3a所示的钝化层232类似，覆盖主设备区域和分割通道/道。在这种情形下，保留类似于或同于图5a-5d描述的晶片的进一步工艺，除了如图3b所描述在裸片拾取过程中钝化层可切断。
上述工艺200、300、400和500产生益处。例如，图2a-2e和图3a-3b所描述，在切割裸片芯片的等离子蚀刻工艺中，电接触件170内嵌于背面研磨带，而钝化层粘合至背面研磨带。因此，避免了芯片的电接触件和钝化层上的氟污染。如所描述，等离子蚀刻工艺对晶片的衬底材料具有高度选择性，并且该等离子蚀刻工艺通过晶片的被动表面执行。因此，等离子蚀刻工艺有效地并完整地从晶片切断裸片，即使监测图案由不与等离子发生化学反应的金属材料制得并在晶片中出现，并避免了被动表面的欠蚀刻。此外，当上述实施例产生的切割裸片的光滑平坦的侧面或侧壁作为一个芯片上的钝化层的轮廓，分割通道上的对准标记、PCM或TEG的残渣在利用等离子蚀刻技术进行的分割过程中不出现问题。
此外，工艺200、300、400或500提供更高吞吐量，这是因为所有的芯片/裸片同时从晶片切割或分隔。由于利用等离子蚀刻技术，而非机械锯切来实现分割，所描述的工艺200、300、400或500能形成更小或更狭窄的分割通道。这容许形成更多电路组件并最大化晶片上的硅利用。由于减少或避免了机械应力导致的缺陷，这些实施例还提供更高的产量。此外，所描述的分割方法可利用现有生产设施，而不需要对于新的或额外设备或光刻装置的投入资本。
本发明可以其他特定形式体现而不脱离其精神或基本特征。因而，上述实施例在本文中应被视为说明性而非限制性本发明。

Claims (13)

1.一种分割晶片的方法，包括：
提供具有第一主表面和第二主表面的晶片，所述第一主表面包括多个主设备区域和设于其上的分割通道，其中所述晶片预备有多个裸片，所述裸片具有位于所述主设备区域内的集成电路，并由所述分割通道彼此分开；其中所述晶片被处理成包括形成在所述晶片的所述第一主表面上的钝化层，所述钝化层延伸到所述主设备区域，其中所述钝化层不延伸至所述分割通道；
在所述晶片的所述第二主表面上提供膜，其中所述膜覆盖所述第二主表面的对应于所述晶片的所述第一主表面上的主设备区域的部分；以及
利用晶片的所述第一主表面上的所述钝化层，通过所述晶片露出的半导体材料等离子蚀刻所述晶片，以形成延伸通过晶片的空隙将所述晶片上的多个裸片分隔成多个单独裸片，在提供所述膜之前，提供支撑平台并附接所述晶片的所述第一主表面至所述支撑平台，所述晶片的所述第一主表面的端部部分通过所述支撑平台暴露。
2.一种分割晶片的方法，包括：
提供具有第一主表面和第二主表面的晶片，所述第一主表面包括多个主设备区域和设于其上的分割通道，其中所述晶片预备有多个裸片，所述裸片具有位于所述主设备区域内的集成电路，并由所述分割通道彼此分开；其中所述晶片被处理成包括形成在所述晶片的所述第一主表面上的钝化层，所述钝化层延伸到所述主设备区域；
在所述晶片的所述第二主表面上提供膜，其中所述膜覆盖所述第二主表面的对应于所述晶片的所述第一主表面上的主设备区域的部分；
在所述晶片的分割通道内形成的一个或多个监测图案，其中，当所述晶片的所述第一主表面附接到支撑平台时，所述一个或多个监测图案接触所述支撑平台；以及
利用所述膜作为蚀刻掩模，通过所述晶片露出的半导体材料等离子蚀刻所述晶片，以形成延伸通过晶片的空隙将所述晶片上的多个裸片分隔成多个单独裸片。
3.如权利要求2所述的方法，其中，所述膜形成为背面保护层，其中所述背面保护层经处理暴露所述第二主表面对应于所述晶片的所述第一主表面上的分割通道的部分，所述背面保护层用作蚀刻掩模，通过由所述背面保护层暴露的部分所述晶片的所述第二主表面的等离子蚀刻工艺去除所述晶片露出的半导体材料。
4.如权利要求3所述的方法，包括从所述支撑平台去除各个裸片，其中当去除所述各个裸片后，所述监测图案留在所述支撑平台的表面上。
5.如权利要求2所述的方法，其中，所述晶片的所述第一主表面为定义集成电路的有源表面，所述晶片的所述第二主表面为被动表面。
6.如权利要求2所述的方法，包括在提供所述膜之前，在所述晶片的所述第二主表面上进行背面研磨工艺。
7.如权利要求2所述的方法，其中，所述钝化层覆盖所述主设备区域，且不覆盖所述晶片的形成在所述分割通道内的所述一个或多个监测图案。
8.如权利要求2所述的方法，其中，提供所述膜包括提供所述晶片的第二主表面上的背面保护层。
9.如权利要求8所述的方法，其中，提供所述膜还包括选择性地去除配置在对应于所述晶片的所述第一主表面上的分割通道的部分所述第二主表面的背面保护层部分，其中所处理的背面保护层用作蚀刻掩模，通过所述晶片的所述第二主表面等离子蚀刻工艺去除所述晶片露出的半导体材料。
10.如权利要求8所述的方法，包括利用裸片拾取工艺去除所述各个裸片，其中当所述裸片由裸片拾取工艺去除时，所述各裸片的所述钝化层被切断且彼此分隔。
11.如权利要求8所述的方法，包括通过在所述等离子蚀刻工艺中形成的所述空隙执行非蚀刻工艺，以切断并将各裸片的钝化层彼此分隔。
12.如权利要求11所述的方法，其中执行所述非蚀刻工艺包括通过所述空隙施加空气吹流或激光束的射流。
13.如权利要求2所述的方法，其中所述支撑平台是背面研磨带。
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Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150147850A1 (en) * 2013-11-25 2015-05-28 Infineon Technologies Ag Methods for processing a semiconductor workpiece
TWI664668B (zh) * 2014-10-13 2019-07-01 新加坡商聯測總部私人有限公司 用於單一化半導體晶圓之方法
JP6467592B2 (ja) * 2016-02-04 2019-02-13 パナソニックＩｐマネジメント株式会社 素子チップの製造方法および電子部品実装構造体の製造方法ならびに電子部品実装構造体
DE102016109693B4 (de) * 2016-05-25 2022-10-27 Infineon Technologies Ag Verfahren zum Trennen von Halbleiterdies von einem Halbleitersubstrat und Halbleitersubstratanordnung
US9905466B2 (en) * 2016-06-28 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer partitioning method and device formed
GB201611652D0 (en) * 2016-07-04 2016-08-17 Spts Technologies Ltd Method of detecting a condition
CN106098535A (zh) * 2016-07-12 2016-11-09 武汉新芯集成电路制造有限公司 键合晶圆制作方法
JP6735653B2 (ja) * 2016-10-24 2020-08-05 株式会社ディスコ ウエーハの分割方法
DE102017212858A1 (de) * 2017-07-26 2019-01-31 Disco Corporation Verfahren zum Bearbeiten eines Substrats
GB2568480A (en) * 2017-11-16 2019-05-22 Owlstone Inc Method of manufacture for a ion mobility filter
JP6994646B2 (ja) * 2018-01-17 2022-01-14 パナソニックＩｐマネジメント株式会社 素子チップの製造方法
CN110634796A (zh) * 2018-06-25 2019-12-31 半导体元件工业有限责任公司 用于处理电子管芯的方法及半导体晶圆和管芯的切单方法
US10916474B2 (en) * 2018-06-25 2021-02-09 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
KR20200034503A (ko) * 2018-09-21 2020-03-31 삼성전자주식회사 기판 쏘잉 방법 및 반도체 칩의 싱귤레이션 방법
JP7210100B2 (ja) * 2018-12-03 2023-01-23 株式会社ディスコ ウェーハの加工方法
JP7139065B2 (ja) * 2018-12-03 2022-09-20 株式会社ディスコ ウェーハの加工方法
TWI689980B (zh) * 2019-03-20 2020-04-01 華邦電子股份有限公司 切割晶圓的方法及晶粒
GB201918333D0 (en) * 2019-12-12 2020-01-29 Spts Technologies Ltd A semiconductor wafer dicing process
CN115280489A (zh) * 2020-07-15 2022-11-01 Pep创新私人有限公司 具有缓冲层的半导体器件

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW559876B (en) * 2001-10-19 2003-11-01 Applied Materials Inc Method and apparatus for dicing a semiconductor wafer
US20130115756A1 (en) * 2011-11-08 2013-05-09 Disco Corporation Processing method for semiconductor wafer having passivation film on the front side thereof
US20130267076A1 (en) * 2012-04-10 2013-10-10 Wei-Sheng Lei Wafer dicing using hybrid multi-step laser scribing process with plasma etch
CN103426721A (zh) * 2012-05-24 2013-12-04 英飞凌科技股份有限公司 用于在未掩蔽区域和预先掩蔽区域处加工晶片的方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4387007B2 (ja) 1999-10-26 2009-12-16 株式会社ディスコ 半導体ウェーハの分割方法
US6686225B2 (en) * 2001-07-27 2004-02-03 Texas Instruments Incorporated Method of separating semiconductor dies from a wafer
JP2003257896A (ja) 2002-02-28 2003-09-12 Disco Abrasive Syst Ltd 半導体ウェーハの分割方法
US7781310B2 (en) 2007-08-07 2010-08-24 Semiconductor Components Industries, Llc Semiconductor die singulation method
US8012857B2 (en) 2007-08-07 2011-09-06 Semiconductor Components Industries, Llc Semiconductor die singulation method
US7989319B2 (en) 2007-08-07 2011-08-02 Semiconductor Components Industries, Llc Semiconductor die singulation method
KR101094450B1 (ko) 2009-06-05 2011-12-15 에스티에스반도체통신 주식회사 플라즈마를 이용한 다이싱 방법
US9252057B2 (en) * 2012-10-17 2016-02-02 Applied Materials, Inc. Laser and plasma etch wafer dicing with partial pre-curing of UV release dicing tape for film frame wafer application
US9041198B2 (en) * 2013-10-22 2015-05-26 Applied Materials, Inc. Maskless hybrid laser scribing and plasma etching wafer dicing process
US8912078B1 (en) * 2014-04-16 2014-12-16 Applied Materials, Inc. Dicing wafers having solder bumps on wafer backside
US9390993B2 (en) * 2014-08-15 2016-07-12 Broadcom Corporation Semiconductor border protection sealant
TWI664668B (zh) * 2014-10-13 2019-07-01 新加坡商聯測總部私人有限公司 用於單一化半導體晶圓之方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW559876B (en) * 2001-10-19 2003-11-01 Applied Materials Inc Method and apparatus for dicing a semiconductor wafer
US20130115756A1 (en) * 2011-11-08 2013-05-09 Disco Corporation Processing method for semiconductor wafer having passivation film on the front side thereof
US20130267076A1 (en) * 2012-04-10 2013-10-10 Wei-Sheng Lei Wafer dicing using hybrid multi-step laser scribing process with plasma etch
CN103426721A (zh) * 2012-05-24 2013-12-04 英飞凌科技股份有限公司 用于在未掩蔽区域和预先掩蔽区域处加工晶片的方法

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