JP6467592B2 - 素子チップの製造方法および電子部品実装構造体の製造方法ならびに電子部品実装構造体 - Google Patents
素子チップの製造方法および電子部品実装構造体の製造方法ならびに電子部品実装構造体 Download PDFInfo
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- JP6467592B2 JP6467592B2 JP2016019866A JP2016019866A JP6467592B2 JP 6467592 B2 JP6467592 B2 JP 6467592B2 JP 2016019866 A JP2016019866 A JP 2016019866A JP 2016019866 A JP2016019866 A JP 2016019866A JP 6467592 B2 JP6467592 B2 JP 6467592B2
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- protective film
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- solder
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
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- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81909—Post-treatment of the bump connector or bonding area
- H01L2224/81948—Thermal treatments, e.g. annealing, controlled cooling
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15323—Connection portion the connection portion being formed on the die mounting surface of the substrate being a land array, e.g. LGA
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Dicing (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
1a 第1の面
1b 第2の面
1c 分割領域
2 素子領域
3 素子電極
4 絶縁膜
5 耐エッチング層
6 キャリア
10 素子チップ
10a 第1の面
10b 第2の面
10c 側面
12a,12b,12c 保護膜
15 プリント基板
16 ランド電極
17 半田
E 角部
C 窪み部
Claims (8)
- 分割領域で画定された複数の素子領域を有し少なくともその一部が絶縁膜で覆われた第1の面と、前記第1の面と反対側の第2の面とを備える基板を、前記分割領域で分割して複数の素子チップを製造する素子チップの製造方法であって、
前記第1の面の側がキャリアに支持されるとともに、前記素子領域と対向する前記第2の面の領域を覆い且つ前記分割領域と対向する前記第2の面の領域を露出させるように耐エッチング層が形成された前記基板を準備する準備工程と、
前記準備工程の後、前記キャリアに支持された前記基板にプラズマ処理を施すプラズマ処理工程とを含み、
前記プラズマ処理工程は、
前記第2の面を第1のプラズマに晒すことにより、前記耐エッチング層に覆われていない領域の前記基板をこの基板の深さ方向に前記第1の面に達するまでエッチングして、前記基板を素子チップに分割し、前記第1の面、前記第2の面および前記第1の面と前記第2の面とを結ぶ側面を備える素子チップが前記キャリア上に互いに間隔をあけて保持されるとともに、前記素子チップの前記側面と前記第1の面とが成す角部に前記絶縁膜を露出させた状態とする分割工程と、
前記分割工程の後、前記キャリア上に互いに間隔をあけて保持された状態で、前記素子チップを第2のプラズマに晒すことにより、前記角部に露出させた前記絶縁膜を後退させて窪み部を形成する窪み部形成工程と、
前記窪み部形成工程の後、前記キャリア上に互いに間隔をあけて保持された状態で、前記素子チップを保護膜形成用ガスを供給しながら発生させた第3のプラズマに晒すことにより、前記素子チップの前記第2の面、前記素子チップの前記側面および前記窪み部に保護膜を形成する保護膜形成工程と、を含む、素子チップの製造方法。 - 前記保護膜形成工程の後、前記キャリア上に互いに間隔をあけて保持された状態で、前記素子チップを第4のプラズマに晒すことにより、前記窪み部に形成された前記保護膜の少なくとも一部は残存させながら、前記素子チップの前記第2の面および前記側面に形成された前記保護膜を除去する保護膜除去工程をさらに含む、請求項1記載の素子チップの製造方法。
- 前記絶縁膜が有機膜である、請求項1または2のいずれかに記載の素子チップの製造方法。
- 前記保護膜がフルオロカーボンを主成分とする膜である、請求項1から3のいずれかに記載の素子チップの製造方法。
- 前記保護膜形成用ガスがフッ化炭素を含む、請求項4に記載の素子チップの製造方法。
- 請求項1から5のいずれかに記載の素子チップの製造方法によって形成された素子チップが前記第1の面に備える素子電極を、前記素子電極と半田により形成された接合部によってプリント基板に形成されたランド電極に接合して成る電子部品実装構造体の製造方法であって、
前記ランド電極にペースト状の半田を供給する半田ペースト供給工程と、
前記素子電極を対応する前記ランド電極に供給された半田ペーストに着地させて前記プリント基板に搭載する搭載工程と、
前記プリント基板を加熱して前記半田を溶融させて前記素子電極とランド電極とを半田接合する接合部を形成する溶融工程と、
前記プリント基板を冷却して溶融した前記半田を固化させる冷却工程とを含み、
前記溶融工程において、前記窪み部に形成された前記保護膜が、溶融した半田の前記側面への這い上がりを抑制する、電子部品実装構造体の製造方法。 - プリント基板に形成されたランド電極に素子チップに形成された素子電極を半田によって接合して成る電子部品実装構造体であって、
前記素子チップは、前記プリント基板と対向する面に形成された前記素子電極と、前記素子チップの側面の前記プリント基板側の角部に形成された窪み部と、前記窪み部を被覆する保護膜とを有し、
前記保護膜によって前記半田の前記側面への這い上がりが阻止されている、電子部品実装構造体。 - 前記保護膜がフルオロカーボンを主成分とする膜である、請求項7に記載の電子部品実装構造体。
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