CN103999203A - 在涂布后研磨前切割 - Google Patents

在涂布后研磨前切割 Download PDF

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CN103999203A
CN103999203A CN201280038320.5A CN201280038320A CN103999203A CN 103999203 A CN103999203 A CN 103999203A CN 201280038320 A CN201280038320 A CN 201280038320A CN 103999203 A CN103999203 A CN 103999203A
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wafer
bottom filler
coating
semiconductor crystal
top surface
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G·黄
Y·金
R·吉诺
Q·黄
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Henkel IP and Holding GmbH
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本发明涉及将半导体晶圆单体化成单个半导体裸片的方法，所述半导体晶圆的顶部表面具有金属预连接凸块，并具有设置在所述金属预连接凸块上及周围的底部填充剂的涂层。所述方法包括：(A)提供半导体晶圆，其顶部表面具有金属预连接凸块的阵列和设置在所述金属预连接凸块上及周围的底部填充剂的涂层；(B)穿过所述金属预连接凸块之间的所述底部填充剂切割并切入所述半导体晶圆的所述顶部表面中至最终所需晶圆厚度，产生切割线；以及(C)从晶圆背侧除去晶圆材料至少至所述切割线的深度，从而由所述晶圆单体化得到的裸片。

Description

在涂布后研磨前切割
相关申请交叉引用
本申请要求2011年7月29日提交的美国专利申请No.61/513,146的优先权，其内容援引并入本申请中。
背景技术
本发明涉及制造施加有底部填充封装剂的半导体晶圆(wafer)的方法。
电气和电子设备的微型化及轻量化已经导致需要更薄的半导体装置和更薄的半导体封装。
制备更薄的半导体裸片(die)的一种方式是从半导体晶圆的背侧去除过量材料，从该半导体晶圆切割单个裸片。过量晶圆的去除通常发生在研磨过程中，通常称作背侧研磨。当在晶圆薄化之前将晶圆切割成单个半导体电路时，该过程称为“研磨之前切割”或DBG。
制备更小且更有效的半导体封装的一种方式是采用具有金属凸块阵列的封装，所述金属凸块阵列连接至封装的有源面。设置所述金属凸块以使其与基板上的焊盘(bonding pad)对齐。当使所述金属凸块回流至熔体时，凸块与焊盘连接，同时形成电连接和机械连接。
在所述晶圆材料、金属凸块和基板之间存在热失配，从而引起金属间连接受到重复热循环的应力。这可潜在地导致故障。为应对该问题，将封装材料(称为底部填充剂)设置在晶圆和基板之间、围绕并支撑金属凸块的间隙中。
半导体封装制造中的目前的趋势优选在晶圆水平完成尽可能多的工艺步骤，从而可同时而非单独处理(如裸片单体化之后进行)多个集成电路。在将晶圆切割成各个半导体裸片之前，将底部填充封装剂施加在金属凸块的阵列和晶圆电路上是在晶圆水平上进行的一个操作。
在典型过程中，具有金属预连接的凸块的半导体晶圆在金属凸块上用底部填充剂材料涂布。将支撑胶带(称为背面研磨胶带)层压于晶圆顶部侧上的底部填充剂材料上。通过研磨或其他方式从晶圆背侧去除晶圆材料。从晶圆顶部侧上的底部填充剂去除背面研磨胶带。在如下切割期间将切割胶带施加在晶圆的背侧以支撑晶圆。切割可通过激光进行，其成本高，或者可以通过切割刀片以机械方式进行。由于薄化晶圆特别易碎，因此尽管使用切割刀片较便宜，但可能对晶圆、电路及底部填充剂造成破坏。
因此，需要一种将半导体晶圆单体化成单个半导体裸片的方法，其中可以预先施加底部填充剂，但其中机械切割操作不会破坏具有凸块的晶圆及底部填充剂。
发明内容
本发明是将半导体晶圆单体化成单个半导体裸片的方法，所述半导体晶圆的顶部表面具有金属预连接凸块且具有设置在所述金属预连接凸块上及周围的底部填充剂的涂层。
所述方法包括(A)提供半导体晶圆，其顶部表面具有金属预连接凸块的阵列及设置在所述金属预连接凸块上及周围的底部填充剂的涂层；(B)穿过所述金属预连接凸块之间的所述底部填充剂切割并切入所述半导体晶圆的顶部表面中至最终所需晶圆厚度，产生切割线；以及(C)从所述晶圆的背侧去除晶圆材料至所述切割线的深度，从而由所述晶圆单体化得到的裸片。
附图说明
图1是将具有预先施加的底部填充剂材料的晶圆单体化的现有技术方法的示意图。
图2是将具有预先施加的底部填充剂材料的晶圆单体化的本发明方法的示意图。
发明详述
由半导体材料，通常是硅、砷化镓、锗或类似的化合物半导体材料制备半导体晶圆。晶圆的顶部侧上的有源电路和金属凸块根据工业文献中大量记载的半导体及金属制造方法制得。
切割胶带通常用于在切割操作期间支撑晶圆。切割胶带可由多个来源购得，并且可以是在载体上的热敏性、压敏性或UV敏感性粘合剂形式。所述载体通常为聚烯烃或聚酰亚胺的柔性基板。当分别施加热、拉伸应力或UV时，粘合性降低。通常，剥离衬垫覆盖粘合剂层并且可在临使用切割胶带之前容易地去除。在DBG工艺中，在晶圆的背侧施加切割胶带，并在晶圆顶部侧上的电路之间切割切割沟槽至满足或超过进行背侧研磨的水平的深度。
使用背面研磨胶带在晶圆薄化过程期间保护并支撑金属凸块及晶圆的顶部表面。背面研磨胶带可由多个来源购得，并且以载体上的热敏性、压敏性或UV敏感性粘合剂形式。所述载体通常为聚烯烃或聚酰亚胺的柔性基板。当分别施加热、拉伸应力或UV时，粘合性降低。通常，剥离衬垫覆盖粘合剂层并且可在临使用切割胶带之前容易地去除。背面研磨操作可通过机械研磨或蚀刻进行。去除晶圆背侧上的材料直至达到或超过切割沟槽，这使裸片单体化。
底部填充封装剂通常以膏或膜形式施加。通过喷雾、旋涂、模版印刷或工业中所用的任何方法施加所述膏。常常优选膜形式的底部填充剂，因为其较不脏乱且更容易以均匀厚度施加。适合用作膜形式的底部填充剂化学物质的粘合剂和封装剂是已知的，制备膜本身的方法也是已知的。可以调节底部填充剂材料的厚度，从而可以在层合后完全或部分覆盖金属凸块。在任一种情形下，供应所述底部填充剂材料，以使其完全填充半导体与目标基板之间的间隔。
在一个实施方案中，将底部填充材料供应在载体上并用剥离衬垫保护。因此，在一个方案中，底部填充材料以三层形式供应，其中第一层是载体，如柔性聚烯烃或聚酰亚胺胶带，第二层是底部填充材料，第三层是剥离衬垫，按照这个顺序。在临使用前，将剥离衬垫去除，并且通常在仍连接至载体时施加底部填充剂。在将底部填充剂施加到晶圆后，去除载体。
下面参照附图作进一步描述本发明。图1显示将在一个表面上具有有源电路12和金属凸块13的阵列的硅晶圆11切割的现有技术方法。首先用底部填充剂材料14封装有源电路和金属凸块。将背面研磨带15层合到底部填充剂14以支撑晶圆并保护底部填充剂，此后，利用研磨刀片16或本领域技术人员选择的任何其他适当的方法减小晶圆的背侧的厚度。
在背面研磨后，将切割胶带18施加到晶圆的背侧，以在切割期间及在切割之后支撑晶圆并使裸片保持在适当位置。从晶圆去除背面研磨胶带15并使用切割刀片19切割切割沟(也称为切割线)，穿过底部填充剂并切入有源电路周围的间隔中的晶圆中，以将电路单体化成各个裸片。元件17表示切割线并最终表示在切割和单体化后单个半导体之间的间隔。在背面研磨期间薄化晶圆时，其变得非常易碎，并且在切割操作期间有源电路可能因切割刀片的机械应力而破坏。为了对此进行补偿，减小切割速度。对有源电路的破坏和切割速度的减小降低了产量并增加了成本。
图2中显示了在底部填充剂封装之后和研磨之前进行切割的本发明方法。提供具有有源电路12和金属凸块13的阵列的硅晶圆11；且有源电路和金属凸块由底部填充剂材料14封装。晶圆安装在切割胶带18上，其中晶圆背侧接触切割胶带。切割刀片19切割穿过底部填充剂并切入有源电路周围的间隔中的晶圆中，产生切割线17。在单体化后，元件17表示单个半导体之间的间隔。将切割线切割入晶圆中至晶圆的最终厚度的所需深度或更深。将背面研磨胶带15层合至晶圆顶部侧上的底部填充剂，并由晶圆背侧去除切割胶带18。然后减小晶圆的背侧的厚度，例如通过研磨刀片19研磨或通过本领域技术人员选择的任何其他适当的方法。减小厚度至少到切割线的深度，并且可以进一步减小厚度至所需的晶圆的最终厚度。通过从晶圆背侧去除厚度至少到切割线的深度，将晶圆单体化成单个裸片。

Claims (1)

1.将半导体晶圆单体化成单个半导体裸片的方法，所述半导体晶圆的顶部表面具有金属预连接凸块，并具有设置在所述金属预连接凸块上及周围的底部填充剂的涂层，所述方法包括：
(A)提供半导体晶圆，该半导体晶圆的顶部表面具有金属预连接凸块的阵列和设置在所述金属预连接凸块上及周围的底部填充剂的涂层；
(B)穿过所述金属预连接凸块之间的所述底部填充剂切割并切入所述半导体晶圆的顶部表面中至最终所需晶圆厚度，产生切割线；以及
(C)从晶圆背侧除去晶圆材料至少至所述切割线的深度，从而由所述晶圆单体化得到的裸片。
CN201280038320.5A 2011-07-29 2012-07-25 在涂布后研磨前切割 Pending CN103999203A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201161513146P 2011-07-29 2011-07-29
US61/513,146 2011-07-29
PCT/US2012/048111 WO2013019499A2 (en) 2011-07-29 2012-07-25 Dicing before grinding after coating

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CN103999203A true CN103999203A (zh) 2014-08-20

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US (1) US20140057411A1 (zh)
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