CN103779241A - 晶片级芯片规模封装（wlcsp）的保护 - Google Patents

晶片级芯片规模封装（wlcsp）的保护 Download PDF

Info

Publication number
CN103779241A
CN103779241A CN201310491772.5A CN201310491772A CN103779241A CN 103779241 A CN103779241 A CN 103779241A CN 201310491772 A CN201310491772 A CN 201310491772A CN 103779241 A CN103779241 A CN 103779241A
Authority
CN
China
Prior art keywords
wafer
protective layer
component pipe
back surface
cut
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310491772.5A
Other languages
English (en)
Other versions
CN103779241B (zh
Inventor
莱奥那德思·安托尼思·伊丽沙白·范吉莫特
哈特莫特·布宁
托尼·坎姆普里思
萨沙·默勒
克里斯蒂安·延斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of CN103779241A publication Critical patent/CN103779241A/zh
Application granted granted Critical
Publication of CN103779241B publication Critical patent/CN103779241B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Dicing (AREA)

Abstract

根据示例实施例，提供了一种用于装配经晶片级芯片规模处理(WLCSP)的晶片的方法。晶片具有前侧表面和背侧表面以及在前侧表面上具有电接触的多个器件管芯。该方法包括：将晶片的背侧表面背侧研磨至一定厚度。将一定厚度的保护层施加至晶片的背侧表面上。将晶片安装到切割箔上。沿多个器件管芯的切割线来切割晶片，该切割利用第一切口的刀片进行且切割至背侧研磨晶片厚度的深度。再次沿多个器件管芯的切割线切割晶片，该切割利用第二切口的刀片进行，第二切口比第一切口窄，且切割至保护层厚度的深度。将多个器件管芯分离为单独的器件管芯。每一个单独的器件管芯在背侧具有保护层，保护层具有相对于单独器件管芯的竖直边缘的偏距。

Description

晶片级芯片规模封装(WLCSP)的保护
相关申请的交叉引用
本申请要求2013年4月26日递交的美国专利申请序列号61／816,609和2012年11月16日递交的美国专利申请序列号No.61／727,204的权益，将其内容合并在此作为参考。
技术领域
本发明的实施例涉及半导体器件封装，更具体地，涉及改进的WLCSP封装，所述改进的WLCSP封装保护半导体管芯免受处理损坏，以便提高产品的可制造性和质量。
背景技术
电子工业继续依赖于半导体技术的进步以在更紧凑的面积上实现高性能器件。对于许多应用，实现高性能器件要求将大量电子器件集成到单一硅晶片中。当每给定面积硅晶片中电子器件的数目增加时，制造工艺变得更加困难。
IC器件的封装在IC器件的最终性能方面日益重要。例如，在移动设备(即，移动电话、平板电脑、膝上型计算机、遥控器等)中，在它们的装配中使用WLCSP部件。WLCSP部件节省了移动设备中宝贵的空间。在装配之后，在一些示例工艺中，客户通过注模(injection mo1ding)或加套(casing)来封装这些WLCSP器件。裸WLCSP的这种手动后处理可能导致器件损坏；通常，应该最小化对WLCSP器件的处理。
需要一种WLCSP装配工艺，可以解决由移动应用的需要而增加的挑战。
发明内容
已经发现本公开在可应用于便携式电子设备的半导体器件的封装中是有用的。具体地，WLCSP产品以未封装管芯的形式供应给移动设备的制造商，而移动设备的制造商又将这些器件直接封装到印刷电路板上(以节省移动设备中宝贵的空间)，从而可能使这些未封装管芯经历粗暴的处理。这种处理可能导致在移动设备到达终端用户之前不会显露出来的破裂或其他潜在损坏。因此，消费者可能更喜欢由非易碎材料包围的WLCSP产品，这在将用于装配的产品装入消费者的移动设备之前防止对于管芯本身的损坏。
用户将保护材料施加至具有器件管芯的晶片的背侧上。通过切割来分离有源器件管芯。通过处理，利用保护材料在背侧表面上保护了未封装的管芯，所述保护材料吸收在移动设备的装配期间手动处理的冲击。该工艺也可以用于具有或不具有焊料球的芯片规模封装(CSP)。
在示例实施例中，提供了一种用于装配经晶片级芯片规模处理(WLCSP)的晶片的方法，晶片具有前侧表面和背侧表面，多个器件管芯在前侧表面上具有电接触。该方法包括将晶片的背侧表面背侧研磨至一定厚度。将一定厚度的保护层施加至晶片的背侧表面上。将晶片在具有保护层的背侧表面上安装到切割箔上。沿前侧表面上多个器件管芯的切割线来切割晶片，该切割利用第一切口的刀片进行，且切割至背侧研磨晶片厚度的第一深度；再次沿多个器件管芯的切割线切割晶片，该切割利用第二切口的刀片进行，第二切口比第一切口窄，并且切割至保护层厚度的深度。将多个器件管芯分离为单独的器件管芯。每一个单独的器件管芯在背侧具有保护层，保护层具有相对于单独器件管芯的竖直边缘的偏距(stand-off distance)。
在另一示例实施例中，提供了一种具有前侧表面和背侧表面以及一定厚度的半导体器件，该半导体器件包括具有在前侧表面上限定的面积的有源器件，前侧表面具有第一面积。保护材料在半导体器件的背侧表面上，保护材料具有大于第一面积的面积。保护材料和层压膜的组合的偏距依赖于半导体器件厚度以及半导体器件的竖直侧表面上工具加工碰撞的角度的正切。该实施例的特征包括面积与保护材料的面积相同的层压材料；层压材料夹在背侧表面和保护材料的下侧表面之间。
在示例实施例中，提供了一种用于装配经晶片级芯片规模处理(WLCSP)的晶片的方法，晶片具有前侧表面和背侧表面，多个器件管芯在前侧表面上具有电接触。该方法包括：将晶片安装到研磨箔上；将晶片的背侧表面背侧研磨至一定厚度；在与多个器件管芯的切割线相对应的区域中对晶片的背侧表面执行半切开切割，形成围绕多个器件管芯中每一个的狭缝，所述狭缝具有半切开刀片切口的宽度以及背侧研磨晶片厚度的约50％的深度。将一定厚度的保护层成型到晶片的背侧，保护层填充在狭缝中，并且覆盖背侧表面。将WLCSP晶片在其背侧表面上安装到切割箔。该方法还包括：沿多个器件管芯的切割线在前侧表面上对WLCSP晶片进行切割，该切割利用第一切口的刀片进行且至少切割至背侧研磨晶片的第一深度，第一切口小于半切开刀片切口；以及再次沿多个器件管芯的切割线在前侧表面上切割WLCSP，该切割利用第二切口的刀片进行，第二切口比第一切口窄，并且至少切割至保护层厚度的深度。将多个器件管芯分离为单独的器件管芯。每一个单独的器件管芯在背侧具有保护层，竖直边缘具有由狭缝形成的凹入，填充凹入的保护层与竖直边缘齐平，并且保护层具有相对于单独器件管芯的竖直边缘的偏距。
在另一示例实施例中，提供了一种用于装配经晶片级芯片规模处理(WLCSP)的晶片的方法，晶片具有前侧表面和背侧表面，多个器件管芯在前侧表面上具有电接触，该方法包括：将晶片安装到研磨箔上；将晶片的背侧表面背侧研磨至一定厚度。该方法还包括：在与多个器件管芯的切割线相对应的区域中，对晶片的背侧表面执行半切开切割，形成围绕多个器件管芯中每一个的狭缝，狭缝具有半切开刀片切口的宽度和背侧研磨晶片厚度的约50％的深度。将一定厚度的保护层成型到晶片的背侧表面上，保护层填充狭缝并且覆盖背侧表面。将WLCSP晶片在其背侧表面上安装到切割箔上。沿多个器件管芯的切割线在前侧表面上对WLCSP晶片进行切割，该切割利用第一切口的刀片进行，并且至少切割到背侧研磨晶片与保护层厚度的总厚度，第一切口小于半切开刀片切口。拉伸切割箔并且分离多个器件管芯得到了单独的器件管芯。每一个单独的器件管芯在背侧具有保护层，竖直边缘具有由狭缝形成的凹入，填充凹入的保护层与竖直边缘齐平，且保护层与单独器件管芯的竖直边缘大致齐平。
在示例实施例中，提供了一种用于装配经晶片级芯片规模处理(WLCSP)的晶片的方法，晶片具有前侧表面和背侧表面，多个器件管芯在前侧表面上具有电接触。该方法包括将晶片安装到研磨箔上。晶片的背侧表面经历背侧研磨至一定厚度。在第一侧表面上，将晶片安装到切割箔上。通过第二侧表面，在与多个器件管芯的切割线相对应的区域中将晶片切割至晶片的背侧研磨后厚度的深度，第二侧表面与第一侧表面相对。为了将器件管芯分隔开，拉伸切割箔。在晶片的前侧表面上将晶片重新安装到成型箔上；去除切割箔。将器件管芯包封在分隔开的器件管芯的背侧表面及竖直面上的成型料中，成型料在背侧表面上具有一定厚度且在竖直面上具有另一厚度。去除成型箔，并且将成型的WLCSP晶片在其背侧表面上重新安装到切割箔上。沿多个器件管芯的切割线在前侧表面上切割成型的WLCSP晶片，以便将成型的晶片分离为其上形成有保护成型件的单独器件管芯。
在另一示例实施例中，提供了一种用于装配经晶片级芯片规模处理(WLCSP)的晶片的方法，晶片具有前侧表面和背侧表面，多个器件管芯在前侧表面上具有电接触，该方法包括：将晶片安装到研磨箔上；将晶片的背侧表面背侧研磨至一定厚度。该方法还包括：将晶片在背侧表面上安装到切割箔上；在前侧表面上沿多个器件管芯的切割线切割WLCSP晶片，该切割利用第一切口的刀片进行且切割至背侧研磨晶片厚度的约50％的第一深度；以及再次沿多个器件管芯的切割线切割WLCSP，该切割利用第二切口的刀片进行，第二切口比第一切口窄，并且切割到背侧研磨晶片厚度的约90％至约95％的深度。在切割之后，拉伸切割箔以便使晶片裂开并且将器件管芯分隔开，现在具有扩展的切割线，导致了具有悬凸体的竖直面。在晶片的前侧上，将晶片重新安装到成型箔上，并且去除切割箔。利用成型料，将器件管芯包封在分隔开的器件管芯的背侧表面和竖直面上的成型料中，成型料在背侧表面上具有一定厚度且在竖直面上具有另一厚度，悬凸体提供成型料的增强锚定。去除成型箔，并且将成型的WLCSP晶片在其背侧重新安装到切割箔上。在前侧表面上沿多个器件管芯的扩展切割线，对成型的WLCSP管芯进行切割以便将成型的晶片分离为其上形成有保护成型件的单独器件管芯。
在示例实施例中，提供了一种半导体器件，包括有源器件，具有前侧表面和背侧表面，该半导体器件具有总厚度。该半导体器件包括：具有在前侧表面上限定的电路的有源器件，前侧表面具有一定面积；其中在有源器件的背侧具有凹入，该凹入具有有源器件厚度的部分深度以及大约该部分深度的宽度，该凹入在竖直边缘处围绕该有源器件。在有源器件的背侧表面上存在一定厚度的保护层，保护材料具有比第一面积大的面积并具有偏距；其中填充凹入的保护层与竖直边缘齐平；以及其中保护材料的偏距根据半导体器件厚度以及半导体器件竖直面上工具加工碰撞的角度的正切确定。
以上概述并非意欲代表本公开的每一个公开实施例或者每一方面。在附图和以下的详细描述中提供了其他方面和示例实施例。
附图说明
结合附图，考虑以下对本发明多种实施例的详细描述，可以更加全面地理解本发明，附图中：
图1示出了针对处理工具碰撞角度的保护材料偏距程度；
图2A-2C示出了根据本公开实施例的具有保护材料的示例器件；
图2A示出了示例器件的处理；
图2B示出了将示例器件放置到印刷电路板上；
图2C示出了将具有可选下填充物的示例器件焊接到印刷电路板上；
图3是根据本公开实施例的装配工艺的流程图；
图4A-4G以截面图示出了通过图3的工艺装配的示例WLCSP器件；
图5是根据本公开另一实施例的装配工艺的流程图；
图6A-6G以截面图示出了通过图5的工艺装配的示例实施例；
图7是根据本公开另一示例实施例的装配工艺的流程图；
图8A-8E以截面图示出了通过图7的工艺装配的示例实施例；
图9是根据本公开的实施例的装配工艺的流程图，该工艺具有用于“阶梯切割”的附加可选步骤；
图10A-10H示出了通过具有可选步骤的图9的工艺装配的示例实施例；
图11A-11H示出了通过没有“阶梯切割”的图9的工艺装配的示例实施例；
图12A是根据没有“阶梯切割”的图9的工艺完成的器件；以及
图12B是根据具有“阶梯切割”的图9的工艺完成的器件。
尽管本发明可修改为多种改型和替代形式，在附图中已经作为示例示出了本发明的细节，并且将对此进行详细描述。然而应该理解的是，并非意欲将本发明局限于所描述的具体实施例。相反，本发明应覆盖落在由所附权利要求限定的本发明的精神和范围内的所有改型、等同物和替代。
具体实施方式
已经发现，所公开的实施例在装配期间保护晶片级芯片规模产品(WLCSP)器件免受损坏方面是有用的。该工艺通过将器件安装到比器件管芯尺度大的保护材料上，来为硅器件提供了机械保护；保护材料形成了器件下侧的边界，防止装配工具直接接触硅器件，从而避免了碎屑和其他损坏。这种工艺可以集成到通常的后端装配中。
参考图1。在示例实施例中，装配100包括厚度T1的硅器件110。保护角度α和硅厚度T1限定了保护材料的偏距(stand-offdistance)T3。例如，为了保护厚度T1=150μm的器件管芯来防止具有20°碰撞角度的工具5的碰撞，约55μm的偏距是合适的。一般而言，偏距是
T3=tanαT1    (1)
保护材料120和胶115的总厚度T4由所使用的材料确定。通过“厚”刀片和“薄”刀片之间的差异来实现偏距的量。例如，8英寸晶片(20.32cm)的研磨前厚度T0是约725μm，对于6英寸晶片(15.24cm)。注意：这种技术可以应用于任意尺寸的晶片衬底，并且对于12英寸(30.48cm)衬底是有用的。另外，使用焊料球(ball)、凸块(bump)、焊盘(pad)等的器件也受益于保护材料。然而为了讨论的目的，以下示例可以使用焊料凸块。然而，所描述的技术不局限于焊料凸块。在示例工艺中，WLCSP研磨为约400μm的厚度，具有高度为约200μm的焊料凸块。希望实现最小晶片厚度T1；然而，可能受限于对具有200μm凸块的晶片减薄的技术能力。示例工艺中的厚度T1可以在约150μm至约250μm的范围内。替代地，薄晶片的包覆成型(over-molding)可以在焊料凸块施加步骤之前进行。在这种情况下，可以将硅晶片减薄到硅厚度小于50μm。T2是保护材料120和胶115(如果使用的话)的厚度T4及硅厚度T1的总厚度。另外，在一些示例工艺中，保护层的厚度(T4)至少是100μm。利用胶115层压到硅110背侧的保护材料120可以是塑料或金属。塑料材料可以由、PTFE(聚四氟乙烯)、成型料(molding compound)等制成，但不限于此。KAPTON是由E.I.du Pont de Nemours and Company制造的聚酰亚胺膜(即，poly-oxydiphenylene-pyromellitimide：聚氧代二苯撑苯均四酸)的商标名。用于层压的保护材料120和胶115必须承受在WLCSP器件装配的回流工艺中经常遇到的约200℃至300℃的温度范围。其他柔性保护材料可以包括但不限于聚四氟乙烯。一些成型料可以包括但不限于Sumitoo(例如：x84194)和Hitachi(例如：cel400ZHF4053C)等制造的成型料。
在示例实施例中，装配的WLCSP器件可以具有范围在约360μm至约400μm(不包括焊料凸块)的总厚度。层压材料越厚，硅器件管芯的侧壁保护越强。如果可以将硅管芯厚度减小到约30μm至约50μm，层压材料将是约350μm至约370μm(如果包括胶，则至少400μm厚)。硅的厚度减小由背侧研磨工艺的能力以及在焊料凸块回流时处理“硅保护层切割”的能力来决定。
参考图2A，在另一示例实施例中，WLCSP结构220可以是薄至约50μm(T1)以及在约10°的角度α下约10μm的凹入偏距。施加至晶片背侧210的厚保护层230(T4，>150μm)提供针对由工具、镊子、真空棒等造成的机械损坏的足够保护。参考图2B-2C，将受保护结构220安装到示例印刷电路基板260的表面250。用于将器件结构220安装到印刷电路基板260上的工具7不再能够损坏器件结构220。通过可选的焊料下填充物280，很好地保护了器件结构270。
参考图4A-4B。硅结构400具有初始厚度T0。有源器件420位于衬底410的顶面上。将衬底410背侧研磨到较薄的厚度Tf。在示例实施例中，Tf是约100μm。虚线415示出了研磨掉的衬底材料的量。电接触区域435将收纳焊料凸块或其他电接触类型。参考图4C-4D。保护涂层430可以通过图2的层压来施加，或者可以包覆成型在减薄的背侧410上。焊料凸块440限定在电接触435中。
可以通过对减薄晶片进行包覆成型来施加保护层。在刚性材料例如金属罩作为保护层的情况下，可以使用利用了粘合剂的结合工艺。更柔性的保护层例如KAPTON箔可以使用箔上预涂覆的粘合剂或者Si晶片上的粘合剂来层压到硅晶片。金属罩可以是不锈钢、铜、银、金或其他合金，但是不限于此；金属的选择由成本限制和工艺参数决定。
参考图3。在根据本公开的示例实施例中，将WLCSP晶片(前侧向下)安装到研磨箔上，310。通过背侧研磨减薄WLCSP晶片，315。将一定厚度的机械保护层施加至减薄晶片的背侧，320。在晶片的前侧上，将焊料凸块附着至有源器件焊盘，325。将准备好的晶片在现在受保护的背侧安装到切割箔上，330。利用第一切口的切割刀片(例如，“厚刀片”)，切割晶片穿过前侧至减薄晶片的深度，335。利用第二切口的切割刀片(例如，“薄刀片”)，将晶片进一步切割到机械保护层的深度，340。分离(例如，“单独化”)成品器件，345。从切割带取下成品器件管芯，并且放置到托盘或者安装在载带上，350。如果需要，可以执行附加的电学测试；将器件封装并且运送给终端用户，355。
参考图4A-4D，已经通过背侧研磨415减薄了具有初始厚度T0的晶片衬底410。已经在该晶片衬底上施加了机械保护层430。晶片衬底410的前侧具有有源器件420。器件焊盘435附着有焊料球440。
参考图4E至4G。将已经施加有保护涂层430的晶片组件470附着到切割膜445。给定“切口”(例如50μm)的第一切割刀片10切穿每一有源器件425之间至减薄的硅衬底的深度Tf。比第一切割刀片10的切口窄的窄切口(例如30μm)的第二切割刀片15切穿保护层430的深度至切割膜445的顶面。晶片组件470现在包括分离的器件管芯480。从切割带445取下分离的器件管芯480用于后续处理。依赖于所要求的偏距程度，可以将第二刀片调整为更大或更小。通过增加切割线的宽度(即晶片上相邻IC之间的距离)来增加第一“切口”的宽度。用于传统切割的刀片可用于大于300μm的厚度；替代地，可以使用在宽度方面没有限制的其他刻蚀工艺。对于第二“切口”，同样可以使用替代的技术，例如消融激光，导致了小于15μm的切口宽度。
参考图5。在根据本公开的示例工艺中，将WLCSP晶片安装到研磨箔上，510。利用背侧研磨来减薄WLCSP晶片，515。在与单独器件管芯之间的切割线相对应的区域中，将晶片的背侧部分地切割(利用第一切口的“厚”刀片)至减薄晶片厚度的约50％的深度，520。将机械保护层应用至晶片的背侧，525；机械保护层还填充切出的切割线。单独器件之间切割线的正确位置可以通过现代成像技术来确定。例如，可以使用红外(IR)摄像机，因为硅衬底对于短波红外光是透明的并且因此可以观察其中的特征。将准备好的晶片在其受保护的背侧表面上安装到切割箔上，530。将焊料凸块附着至晶片前侧上的器件结合焊盘，535。在晶片的前侧，在部分切割540的相应切割位置中利用第二切口的“薄”刀片切割545晶片；第二切割545的深度是薄晶片的深度。分离(即单独化)成品器件，550。从切割带取下成品，并且放置到合适的托盘中或载带上，555。如果终端用户需要，可以在封装和运输之前进行附加的产品测试，560。
参考图6A至6B。在另一示例实施例中，在附着保护层630之前，沿切割线将具有有源器件特征620的硅晶片610从背侧部分地切割至一定深度Thalfcut。可以通过传统的刀片切片或者其他合适的技术例如刻蚀或消融激光技术来实现“半切开”45。根据与图4E-4G讨论的工艺类似的工艺，在图6C-6F中示出了另外的处理。在示例工艺中，在将晶片放置在切割箔645上的情况下，将焊料凸块640附着至有源器件特征620的接触区635。利用厚切口切割刀片65(第一刀片)，将晶片至少切割至晶片厚度及半切开55厚度的深度；生产工艺希望确保薄切口刀片切割得比晶片厚度大而比半切开55厚度小，以便不会让硅的侧面暴露。参考图6E-6F。利用薄切口刀片75(后续或第二刀片)，继续切割至机械保护层630的深度，直到达到切割箔645。在后续切割之后，将器件分离为单独的器件610。
参考图6G。注意：通过保护层635的半切开区655保护了硅615的竖直面；另外，这种半切开区655具有保护层635的附加悬凸体665。进一步减小了不受保护的硅侧面的面积。
如图1所示，图6G进一步示出了器件厚度T10(的相应特征)。器件厚度T10和保护层厚度T40的总和得到整个成型器件厚度T20。通过偏距T30限定了偏距角度θ。器件管芯的侧壁厚度是器件管芯厚度T10与“半切开”深度Thalf-Cut之差。
参考图7。在根据本公开的另一示例实施例中，将WLCSP安装到研磨箔上，710。通过背侧研磨将WLCSP晶片在其背侧减薄，715。在背侧上利用“厚”刀片将晶片部分地切割至减薄晶片的约50％的深度。施加背侧保护涂层以填充切割线，725。将涂覆的晶片在其涂覆侧安装到切割带上，730。在晶片的前侧，将焊料凸块附着至器件结合焊盘，735。从晶片的前侧利用“薄”刀片，在部分切割的相应位置对晶片进行切割，740；切割的深度是减薄晶片厚度加上保护涂层厚度。分离成品器件，745。根据最终用户，器件可以在封装和运输之前进行另外的电学测试，750。
参考图8A-8E。具有有源器件管芯810的背景晶片衬底810在其背侧表面上经受部分切割45(利用具有第一切口的刀片)。施加成型料830并流到部分切口45中。在器件管芯焊盘处的前侧表面上，附着焊料球840。将晶片衬底安装到切割带845上。从晶片衬底810的前侧，利用比用于第一部分切割45切口窄的刀片来进行第二切割65。在切割之后，将晶片分离为单独的器件，如图8E所示。通过成型料835保护了器件管芯815的背侧。
在示例工艺中，依赖于终端用户要求，在施加保护成型料或者阶梯切割工艺(导致了器件管芯的硅边缘上的阶梯轮廓)之前，晶片衬底可以经历单独的切割。
表1示出了工艺的示例实施例的一些参数。
参考图9。在示例工艺中，将晶片衬底在其前侧表面上安装到研磨箔上，910。通过背侧研磨减薄晶片，920。在背侧表面上，将减薄晶片安装到切割／切片箔上，930。将晶片在器件边界(即切割线)处切穿前侧表面至减薄晶片的深度，940。将切割／切片箔拉伸以加宽器件管芯之间的间隔，960。将拉伸的晶片在其前侧表面(有源管芯表面)上重新安装到成型箔上，并去除切割／切片箔，970。将已经拉伸分离的器件管芯嵌入到成型料中，975。成型料包围器件管芯的背侧表面和竖直面。去除成型箔，980。可以将焊料球或凸块附着至有源器件，985。将现在受保护的器件切割开并分离，990。
在示例实施例的变体中，可以将晶片切割到减薄晶片深度的约90％至约99％的深度，950。在示例工艺中，该深度可以在减薄晶片深度的约90％至约95％的范围内。当将器件管芯拉伸开时，器件管芯将沿切割线裂开，产生了在背侧表面处略微突起的竖直面。这种突起提供了器件管芯周围成型料的增强锚定。
在参考图9讨论的示例实施例的另一变体中，在将减薄晶片安装到切割／切片箔上920之后，晶片可以经历“阶梯切割”切割工艺，925。将减薄晶片在背侧表面安装到切片／切割箔上，935。通过晶片前侧的切割线进行“宽”切口切割，至减薄晶片衬底厚度的约50％，945。沿第一切口的中心区域对其余晶片进行“窄”切口切割，至减薄晶片衬底深度的约90％至约95％的深度，955。当拉伸切割／切片箔960时，随着器件管芯之间的间隔加宽，其余未切开的切割线裂开。该工艺如上所述继续。
参考图10A-10H。在截面图中，根据图9的工艺来装配晶片衬底。在装配(图10A)装置1000中，将在前侧上具有有源器件1020的减薄晶片衬底1010附着至切割／切片箔1030。在减薄晶片衬底1010的深度处实现利用预定切口的刀片85的单独切割(图10B)；实现大约刀片切口宽度的间隔。通过拉伸切割／切片箔1030将这种间隔展宽约3倍(图10C)，1030。将拉伸的装配装置1000按照器件管芯前侧面朝下的方式重新安装到耐热箔1040上(图10D)。在重新安装之后(图10E)，使成型料流到拉伸的装配装置1000上，用厚度T4的成型件包封了每一个器件管芯1010。去除耐热箔1040，并且将焊料凸块1025附着至有源器件1020上的管芯焊盘位置。将切割／切片箔1060附着至包封的拉伸组件1000的成型件一侧。切口95的第二刀片切穿厚度T4的成型件，使得可以分离单独的器件管芯1010。
参考图11A-11H。在示例实施例中，将具有减薄晶片(图11A)衬底1100的组件1100安装到切割／切片带1130上，该减薄晶片衬底在前侧具有有源器件1120。利用宽切口95b的刀片，沿有源器件管芯边界周围的切割线，通过第一切割对晶片衬底1110进行切割(至晶片厚度的约50％的深度)。利用窄切口95a的刀片，第二切割从第一切割继续，至晶片厚度的约90％至约95％的深度(图11B)。将切割／切片带1130拉伸，器件管芯如1110和1110a所示裂开(图11C)。将裂开的管芯1110和1110a重新安装到耐热箔1140用于后续的成型。注意，轮廓97a、97b和97c在器件管芯1110和1110a的竖直面上。使成型料1150流动以包封器件管芯1110、1110a(图11E)。参考图11F-11H。去除耐热箔1140。将焊料球、焊料凸块或其等同物1125、1125a施加至有源器件焊盘以提供与有源器件1120、1120a的电连接。在组件1110的成型件一侧，施加切割／切片带1160。通过利用适当切口98的刀片进行切割，分离了成型器件管芯1110、1110a。
参考图12A和12B。示出了成品1200a和1200b，通过厚度T3和T4的成型料1250a、1250b包封了厚度为T1的器件管芯1210a、1210b。通过背侧和竖直面上的成型料包封器件管芯1210a、1210b。通过成型料保护器件管芯的易碎边缘免受后续处理影响。成型料1250b由于已经流到“断裂”硅边缘97a和阶梯切口97b下方而具有附加的机械锚定。成型料和管芯的厚度T2将由具体的参数或者在下游系统装配时有多少垂直空间可用来确定。
在示例工艺中，在拉伸工艺的一个方面，可以通过将具有分离晶片的晶片框在环形物上按压，在设备中拉伸晶片。一示例设备限于将200mm晶片扩展至约235mm。附加的35mm(即35000μm)表现为管芯之间均匀分布的间隔。对于1x1mm2的管芯尺寸，晶片具有沿X和方向的约200个间隔。200mm晶片上的原始切口宽度是由切片刀片产生的约20μm-25μm。扩展35mm将切口间隔增加约175μm；扩展之后的最终切口宽度是约195μm至约200μm。
所讨论的实施例保护了WLCSP器件的背侧和竖直面免受装配期间的后续处理(镊子、吸管、真空棒等)的机械碰撞。材料的厚度T4和偏距T3确定了保护程度。
在不脱离由所附权利要求限定的本发明的精神和范围的情况下，本领域普通技术人员可以想到本发明的各种其他实施例。

Claims (20)

1.一种用于装配经晶片级芯片规模处理WLCSP的晶片的方法，所述晶片具有前侧表面和背侧表面，多个器件管芯在前侧表面上具有电接触，所述方法包括：
将晶片的背侧表面背侧研磨至一定厚度；
将一定厚度的保护层施加至晶片的背侧表面上；
将WLCSP晶片在具有保护层的背侧表面上安装到切割箔上；
沿前侧表面上所述多个器件管芯的切割线来切割WLCSP晶片，该切割利用第一切口的刀片进行，且切割至背侧研磨晶片厚度的第一深度；
再次沿所述多个器件管芯的切割线切割WLCSP晶片，该切割利用第二切口的刀片进行，所述第二切口比第一切口窄，并且切割至保护层厚度的深度；
将所述多个器件管芯分离为单独的器件管芯；
其中每一个单独的器件管芯在背侧具有保护层，所述保护层具有相对于单独器件管芯的竖直边缘的偏距。
2.根据权利要求1所述的方法，其中在对晶片的背侧表面进行背侧研磨之后，所述方法还包括：在与所述多个器件管芯的切割线相对应的区域中对晶片的背侧表面执行半切开切割。
3.根据权利要求1所述的方法，其中保护层的施加包括：将层压胶施加到晶片背侧的中间步骤，以便提供对于保护层的粘附。
4.根据权利要求1所述的方法，其中在施加保护层之后，所述方法还包括将焊料凸块附着至晶片的前侧表面上的电接触。
5.根据权利要求1所述的方法，其中偏距根据侧面碰撞角度和晶片的背侧研磨后厚度来确定。
6.根据权利要求1所述的方法，其中所述保护材料是柔性塑料中的至少一种。
7.根据权利要求6所述的方法，
其中从以下的至少一个中选择柔性塑料：聚氧代二苯撑苯均四酸、聚四氟乙烯、成型料、线上膜FOW。
8.根据权利要求3所述的方法，其中所述保护材料是粘合剂、复合材料、金属、陶瓷、玻璃中的至少一种。
9.根据权利要求6所述的方法，其中所述晶片的厚度和所述保护材料的厚度由所使用的保护材料的类型确定。
10.一种半导体器件，具有前侧表面和背侧表面，所述半导体器件具有一定厚度(T1)，所述半导体器件包括：
具有在前侧表面上限定的面积的有源器件，前侧表面具有第一面积；
半导体器件的背侧表面上的保护材料，所述保护材料的面积大于第一面积；以及
其中所述保护材料的偏距(T3)根据半导体器件厚度(T1)和半导体器件的竖直侧表面上工具加工碰撞的角度(α)的正切来确定。
11.根据权利要求10所述的半导体器件，还包括：
面积与保护材料的面积相同的层压材料，所述层压材料夹在背侧表面和保护材料的下侧表面之间。
12.根据权利要求11所述的半导体器件，其中从以下的至少一个中选择所述保护材料：复合材料、金属、陶瓷、玻璃。
13.根据权利要求12所述的半导体器件，其中从以下的至少一个中选择所述层压材料：胶、管芯附着膜。
14.根据权利要求10所述的半导体器件，
其中所述保护材料是从以下的至少一个中选择的塑料：聚氧代二苯撑苯均四酸、聚四氟乙烯、成型料、线上膜FOW。
15.一种用于装配经晶片级芯片规模处理WLCSP的晶片的方法(500)，所述晶片具有前侧表面和背侧表面，多个器件管芯在前侧表面上具有电接触，所述方法包括：
将晶片安装到研磨箔上；
将晶片的背侧表面背侧研磨至一定厚度；
在与所述多个器件管芯的切割线相对应的区域中，对晶片的背侧表面执行半切开切割，形成围绕所述多个器件管芯中每一个的狭缝，所述狭缝具有半切开刀片切口的宽度及背侧研磨晶片厚度的约50％的深度；
将一定厚度的保护层成型到晶片的背侧，所述保护层填充狭缝并且覆盖背侧表面；
将WLCSP晶片在其背侧表面上安装到切割箔上；
沿所述多个器件管芯的切割线在前侧表面上对WLCSP晶片进行切割，该切割利用第一切口的刀片进行且至少切割到背侧研磨晶片的第一深度，第一切口小于半切开刀片切口；
再次沿所述多个器件管芯的切割线在前侧表面上切割WLCSP晶片，该切割利用第二切口的刀片进行，所述第二切口比第一切口窄，并且至少切割到保护层厚度的深度；
将所述多个器件管芯分离为单独的器件管芯；以及
其中每一个单独的器件管芯在背侧具有保护层，竖直边缘具有由狭缝形成的凹入，填充凹入的保护层与竖直边缘齐平；以及
其中所述保护层具有相对于单独器件管芯的竖直边缘的偏距。
16.根据权利要求15所述的方法，其中所述保护层是从以下的至少一个中选择的塑料：聚氧代二苯撑苯均四酸、聚四氟乙烯、成型料。
17.一种用于装配经晶片级芯片规模处理WLCSP的晶片的方法，所述晶片具有前侧表面和背侧表面，多个器件管芯在前侧表面上具有电接触，所述方法包括：
将晶片安装到研磨箔上；
将晶片的背侧表面背侧研磨至一定厚度；
在与所述多个器件管芯的切割线相对应的区域中，对晶片的背侧表面执行半切开切割，形成围绕所述多个器件管芯中每一个的狭缝，所述狭缝具有半切开刀片切口的宽度及背侧研磨晶片厚度的约50％的深度；
将一定厚度的保护层成型到晶片的背侧表面上，所述保护层填充狭缝并且覆盖背侧表面；
将WLCSP晶片在其背侧表面上安装到切割箔上；
沿所述多个器件管芯的切割线在前侧表面上对WLCSP晶片进行切割，该切割利用第一切口的刀片进行，且至少切割到背侧研磨晶片与保护层厚度的总深度，第一切口小于半切开刀片切口；
拉伸切割箔并且将所述多个器件管芯分离为单独的器件管芯；以及
其中每一个单独的器件管芯在背侧具有保护层，竖直边缘具有由狭缝形成的凹入，填充凹入的保护层与竖直边缘齐平；以及
其中所述保护层与单独器件管芯的竖直边缘大致齐平。
18.根据权利要求17所述的方法，还包括：在将晶片在其背侧表面上安装之后，
将焊料球附着至晶片的前侧表面上的电接触。
19.根据权利要求18所述的方法，其中所述保护层是从以下的至少一个中选择的塑料：聚氧代二苯撑苯均四酸、聚四氟乙烯、成型料、线上膜FOW。
20.根据权利要求19所述的方法，其中背侧表面上保护层的厚度是至少100μm。
CN201310491772.5A 2012-10-23 2013-10-18 晶片级芯片规模封装（wlcsp）的保护 Active CN103779241B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201261717594P 2012-10-23 2012-10-23
US61/717,594 2012-10-23
US201261727204P 2012-11-16 2012-11-16
US61/727,204 2012-11-16
US201361816609P 2013-04-26 2013-04-26
US61/816,609 2013-04-26

Publications (2)

Publication Number Publication Date
CN103779241A true CN103779241A (zh) 2014-05-07
CN103779241B CN103779241B (zh) 2017-01-18

Family

ID=50484621

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201310491772.5A Active CN103779241B (zh) 2012-10-23 2013-10-18 晶片级芯片规模封装（wlcsp）的保护
CN201310495065.3A Active CN103779237B (zh) 2012-10-23 2013-10-21 用于组装wlcsp晶片的方法及半导体器件

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201310495065.3A Active CN103779237B (zh) 2012-10-23 2013-10-21 用于组装wlcsp晶片的方法及半导体器件

Country Status (2)

Country Link
US (2) US9196537B2 (zh)
CN (2) CN103779241B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409699A (zh) * 2015-07-30 2017-02-15 商升特公司 形成小z半导体封装的方法和半导体器件
CN107170690A (zh) * 2016-03-07 2017-09-15 株式会社吉帝伟士 半导体封装件的制造方法及半导体封装件

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10186458B2 (en) * 2012-07-05 2019-01-22 Infineon Technologies Ag Component and method of manufacturing a component using an ultrathin carrier
US9620413B2 (en) 2012-10-02 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
US9496195B2 (en) 2012-10-02 2016-11-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
US20140110826A1 (en) * 2012-10-23 2014-04-24 Nxp B.V. Backside protection for a wafer-level chip scale package (wlcsp)
US9196537B2 (en) 2012-10-23 2015-11-24 Nxp B.V. Protection of a wafer-level chip scale package (WLCSP)
US9704824B2 (en) 2013-01-03 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
US9721862B2 (en) 2013-01-03 2017-08-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
JP6235279B2 (ja) * 2013-09-18 2017-11-22 株式会社ディスコ ウエーハの加工方法
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US10720495B2 (en) * 2014-06-12 2020-07-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US20160005653A1 (en) * 2014-07-02 2016-01-07 Nxp B.V. Flexible wafer-level chip-scale packages with improved board-level reliability
CN104716076B (zh) * 2015-03-20 2017-05-24 上海华力微电子有限公司 芯片压胶装置及芯片压胶方法
US10319639B2 (en) * 2017-08-17 2019-06-11 Semiconductor Components Industries, Llc Thin semiconductor package and related methods
KR101843621B1 (ko) * 2015-12-04 2018-03-29 앰코테크놀로지코리아(주) 반도체 패키지의 제조 방법 및 이를 이용한 반도체 패키지
US9842776B2 (en) * 2016-01-13 2017-12-12 Nxp B.V. Integrated circuits and molding approaches therefor
US10177021B2 (en) 2016-01-13 2019-01-08 Nxp B.V. Integrated circuits and methods therefor
US9799629B2 (en) 2016-02-11 2017-10-24 Nxp B.V. Integrated circuit dies with through-die vias
US20170256432A1 (en) * 2016-03-03 2017-09-07 Nexperia B.V. Overmolded chip scale package
US20170338184A1 (en) * 2016-05-19 2017-11-23 Texas Instruments Incorporated Method of dicing integrated circuit wafers
US10121765B2 (en) 2017-03-01 2018-11-06 Semiconductor Components Industries, Llc Semiconductor device and method of forming WLCSP
JP6955918B2 (ja) * 2017-07-03 2021-10-27 株式会社ディスコ 基板の加工方法
US10522440B2 (en) * 2017-11-07 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of manufacturing the same
US10403506B2 (en) 2018-01-07 2019-09-03 Infineon Technologies Ag Separation of workpiece with three material removal stages
US10319696B1 (en) * 2018-05-10 2019-06-11 Micron Technology, Inc. Methods for fabricating 3D semiconductor device packages, resulting packages and systems incorporating such packages
JP7130323B2 (ja) * 2018-05-14 2022-09-05 株式会社ディスコ ウェーハの加工方法
KR102677777B1 (ko) * 2019-04-01 2024-06-25 삼성전자주식회사 반도체 패키지
JP2021048205A (ja) * 2019-09-17 2021-03-25 キオクシア株式会社 半導体装置の製造方法
CN113053813A (zh) * 2019-12-27 2021-06-29 美光科技公司 形成具有用于堆叠裸片封装的周边轮廓的半导体裸片的方法
US20210202318A1 (en) * 2019-12-27 2021-07-01 Micron Technology, Inc. Methods of forming semiconductor dies with perimeter profiles for stacked die packages
US11605570B2 (en) * 2020-09-10 2023-03-14 Rockwell Collins, Inc. Reconstituted wafer including integrated circuit die mechanically interlocked with mold material
US11908831B2 (en) 2020-10-21 2024-02-20 Stmicroelectronics Pte Ltd Method for manufacturing a wafer level chip scale package (WLCSP)
JP7516230B2 (ja) * 2020-12-03 2024-07-16 新光電気工業株式会社 半導体装置及び半導体装置の製造方法
CN113400380A (zh) * 2021-06-17 2021-09-17 河南卓耐新材料技术有限公司 一种环氧台面快速成型机及其使用方法
US12080601B2 (en) 2021-07-16 2024-09-03 Nxp B.V. Packaged semiconductor devices and methods therefor
US20230098907A1 (en) * 2021-09-30 2023-03-30 Texas Instruments Incorporated Package geometries to enable visual inspection of solder fillets
CN114604615A (zh) * 2022-03-24 2022-06-10 广州金智为电气有限公司 一种一体化加工设备

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722130A (en) * 1984-11-07 1988-02-02 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
JP2001068603A (ja) * 1999-08-24 2001-03-16 Seiko Epson Corp 半導体装置及びその製造方法
JP2001176898A (ja) * 1999-12-20 2001-06-29 Mitsui High Tec Inc 半導体パッケージの製造方法
JP2003124392A (ja) * 2001-10-15 2003-04-25 Sony Corp 半導体装置及びその製造方法
CN1579728A (zh) * 2003-08-12 2005-02-16 株式会社迪斯科 分割盘状工件的方法
CN1967775A (zh) * 2005-11-18 2007-05-23 半导体元件工业有限责任公司 半导体部件及其制造方法
US7354802B1 (en) * 2004-09-07 2008-04-08 National Semiconductor Corporation Thermal release wafer mount tape with B-stage adhesive
CN101589464A (zh) * 2007-01-25 2009-11-25 模拟设备公司 晶片级csp封装设计
JP2010192818A (ja) * 2009-02-20 2010-09-02 Casio Computer Co Ltd 半導体装置の製造方法
JP2011159694A (ja) * 2010-01-29 2011-08-18 Hitachi Chem Co Ltd 半導体装置の製造方法、それにより得られる半導体装置及びそれに用いるダイシングフィルム一体型チップ保護フィルム
CN102420195A (zh) * 2010-09-24 2012-04-18 卡西欧计算机株式会社 设有背面保护膜的半导体装置及其制造方法

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2541624C2 (de) 1975-09-18 1982-09-16 Ibm Deutschland Gmbh, 7000 Stuttgart Wässrige Ätzlösung und Verfahren zum Ätzen von Polymerfilmen oder Folien auf Polyimidbasis
US6338980B1 (en) 1999-08-13 2002-01-15 Citizen Watch Co., Ltd. Method for manufacturing chip-scale package and manufacturing IC chip
TW451436B (en) 2000-02-21 2001-08-21 Advanced Semiconductor Eng Manufacturing method for wafer-scale semiconductor packaging structure
US8076216B2 (en) 2008-11-11 2011-12-13 Advanced Inquiry Systems, Inc. Methods and apparatus for thinning, testing and singulating a semiconductor wafer
US6521485B2 (en) 2001-01-17 2003-02-18 Walsin Advanced Electronics Ltd Method for manufacturing wafer level chip size package
US6964881B2 (en) 2002-08-27 2005-11-15 Micron Technology, Inc. Multi-chip wafer level system packages and methods of forming same
US7378297B2 (en) 2004-07-01 2008-05-27 Interuniversitair Microelektronica Centrum (Imec) Methods of bonding two semiconductor devices
SG130055A1 (en) * 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
JP4764159B2 (ja) * 2005-12-20 2011-08-31 富士通セミコンダクター株式会社 半導体装置
JP4691455B2 (ja) * 2006-02-28 2011-06-01 富士通株式会社 半導体装置
KR100846569B1 (ko) * 2006-06-14 2008-07-15 매그나칩 반도체 유한회사 Ｍｅｍｓ 소자의 패키지 및 그 제조방법
US7682874B2 (en) 2006-07-10 2010-03-23 Shanghai Kaihong Technology Co., Ltd. Chip scale package (CSP) assembly apparatus and method
US7700458B2 (en) 2006-08-04 2010-04-20 Stats Chippac Ltd. Integrated circuit package system employing wafer level chip scale packaging
US7585750B2 (en) 2007-05-04 2009-09-08 Stats Chippac, Ltd. Semiconductor package having through-hole via on saw streets formed with partial saw
US7825010B2 (en) 2007-06-07 2010-11-02 Micron Technology, Inc. Die singulation methods
US7553752B2 (en) * 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
FR2923081B1 (fr) * 2007-10-26 2009-12-11 3D Plus Procede d'interconnexion verticale de modules electroniques 3d par des vias.
US9460951B2 (en) 2007-12-03 2016-10-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of wafer level package integration
US8039303B2 (en) * 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
KR101493872B1 (ko) 2008-08-20 2015-02-17 삼성전자주식회사 백그라인딩-언더필 필름, 그 형성방법, 이를 이용한 반도체패키지 및 그 형성방법
US7888181B2 (en) * 2008-09-22 2011-02-15 Stats Chippac, Ltd. Method of forming a wafer level package with RDL interconnection over encapsulant between bump and semiconductor die
CN102947088B (zh) 2010-06-23 2017-06-13 Asml控股股份有限公司 具有结合的聚合物薄膜磨损表面的气动轴承及其制造方法
US20120049334A1 (en) 2010-08-27 2012-03-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Leadframe as Vertical Interconnect Structure Between Stacked Semiconductor Die
US8659152B2 (en) * 2010-09-15 2014-02-25 Osamu Fujita Semiconductor device
KR101715761B1 (ko) * 2010-12-31 2017-03-14 삼성전자주식회사 반도체 패키지 및 그 제조방법
US9679863B2 (en) 2011-09-23 2017-06-13 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming interconnect substrate for FO-WLCSP
US20140110826A1 (en) 2012-10-23 2014-04-24 Nxp B.V. Backside protection for a wafer-level chip scale package (wlcsp)
US9196537B2 (en) 2012-10-23 2015-11-24 Nxp B.V. Protection of a wafer-level chip scale package (WLCSP)

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4722130A (en) * 1984-11-07 1988-02-02 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device
JP2001068603A (ja) * 1999-08-24 2001-03-16 Seiko Epson Corp 半導体装置及びその製造方法
JP2001176898A (ja) * 1999-12-20 2001-06-29 Mitsui High Tec Inc 半導体パッケージの製造方法
JP2003124392A (ja) * 2001-10-15 2003-04-25 Sony Corp 半導体装置及びその製造方法
CN1579728A (zh) * 2003-08-12 2005-02-16 株式会社迪斯科 分割盘状工件的方法
US7354802B1 (en) * 2004-09-07 2008-04-08 National Semiconductor Corporation Thermal release wafer mount tape with B-stage adhesive
CN1967775A (zh) * 2005-11-18 2007-05-23 半导体元件工业有限责任公司 半导体部件及其制造方法
CN101589464A (zh) * 2007-01-25 2009-11-25 模拟设备公司 晶片级csp封装设计
JP2010192818A (ja) * 2009-02-20 2010-09-02 Casio Computer Co Ltd 半導体装置の製造方法
JP2011159694A (ja) * 2010-01-29 2011-08-18 Hitachi Chem Co Ltd 半導体装置の製造方法、それにより得られる半導体装置及びそれに用いるダイシングフィルム一体型チップ保護フィルム
CN102420195A (zh) * 2010-09-24 2012-04-18 卡西欧计算机株式会社 设有背面保护膜的半导体装置及其制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106409699A (zh) * 2015-07-30 2017-02-15 商升特公司 形成小z半导体封装的方法和半导体器件
CN107170690A (zh) * 2016-03-07 2017-09-15 株式会社吉帝伟士 半导体封装件的制造方法及半导体封装件

Also Published As

Publication number Publication date
CN103779241B (zh) 2017-01-18
US20140138855A1 (en) 2014-05-22
US9196537B2 (en) 2015-11-24
US9245804B2 (en) 2016-01-26
US20140110842A1 (en) 2014-04-24
CN103779237B (zh) 2018-06-19
CN103779237A (zh) 2014-05-07

Similar Documents

Publication Publication Date Title
CN103779241A (zh) 晶片级芯片规模封装（wlcsp）的保护
US8987057B2 (en) Encapsulated wafer-level chip scale (WLSCP) pedestal packaging
US7727875B2 (en) Grooving bumped wafer pre-underfill system
US6444499B1 (en) Method for fabricating a snapable multi-package array substrate, snapable multi-package array and snapable packaged electronic components
KR101504461B1 (ko) 반도체 웨이퍼를 개개의 반도체 다이로 개별화하는 방법
US20160225733A1 (en) Chip Scale Package
KR102643185B1 (ko) 판상물의 가공 방법
US20130119538A1 (en) Wafer level chip size package
US20190057900A1 (en) Thin semiconductor package and related methods
CN109545742B (zh) 半导体装置的制造方法及半导体装置
US20070190688A1 (en) Method for manufacturing semiconductor device with protection layer
TWI549171B (zh) 施加於切割膠帶上之底部填充膜的預切割晶圓
CN103415917A (zh) 施加有底部填料膜的预切割的晶片
KR20180009301A (ko) 반도체 패키지 및 그 제조 방법
US8993412B1 (en) Method for reducing backside die damage during die separation process
TW202008529A (zh) 半導體裝置及其製造方法
US20170011979A1 (en) Chip Scale Package
CN111739805A (zh) 半导体封装方法及半导体封装结构
JP2005191485A (ja) 半導体装置
EP3367430B1 (en) Process of fabrication of a semiconductor device with six-sided protected walls
CN111599694B (zh) 半导体封装方法
US20230386979A1 (en) Die attach film die pad isolation for semiconductor devices
KR102102034B1 (ko) Qfn 반도체 패키지의 제조방법
TW200919565A (en) Method for wafer cutting, die structure and its die package structure
KR20100030500A (ko) 반도체 패키지 및 그의 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant