CN103779237B - 用于组装wlcsp晶片的方法及半导体器件 - Google Patents
用于组装wlcsp晶片的方法及半导体器件 Download PDFInfo
- Publication number
- CN103779237B CN103779237B CN201310495065.3A CN201310495065A CN103779237B CN 103779237 B CN103779237 B CN 103779237B CN 201310495065 A CN201310495065 A CN 201310495065A CN 103779237 B CN103779237 B CN 103779237B
- Authority
- CN
- China
- Prior art keywords
- chip
- thickness
- chips
- foil
- wlcsp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 56
- 239000004065 semiconductor Substances 0.000 title abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 71
- 239000011888 foil Substances 0.000 claims description 62
- 238000000465 moulding Methods 0.000 claims description 53
- 238000000227 grinding Methods 0.000 claims description 31
- 229910000679 solder Inorganic materials 0.000 claims description 22
- 238000004873 anchoring Methods 0.000 claims description 4
- 230000002708 enhancing effect Effects 0.000 claims description 3
- 230000001681 protective effect Effects 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims 1
- 239000011241 protective layer Substances 0.000 abstract description 33
- 230000036961 partial effect Effects 0.000 abstract description 10
- 238000011049 filling Methods 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 42
- 238000005520 cutting process Methods 0.000 description 28
- 239000000758 substrate Substances 0.000 description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 25
- 230000008569 process Effects 0.000 description 25
- 229910052710 silicon Inorganic materials 0.000 description 25
- 239000010703 silicon Substances 0.000 description 25
- 239000010410 layer Substances 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 9
- 239000003292 glue Substances 0.000 description 8
- 238000005538 encapsulation Methods 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000004810 polytetrafluoroethylene Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 4
- 239000002648 laminated material Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- -1 polytetrafluoroethylene Polymers 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/782—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3178—Coating or filling in grooves made in the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
- H01L2221/68336—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding involving stretching of the auxiliary support post dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Dicing (AREA)
Abstract
本发明提出一种半导体器件,该半导体器件具有有源器件、正面表面和背面表面,具有总厚度的半导体器件包括具有电路的有源器件,有源器件的电路限定在正面表面上,正面表面具有第一面积。在有源器件的背面具有凹部,该凹部的部分深度是有源器件的厚度,该凹部的宽度是部分深度,该凹部在垂直边缘围绕有源器件。在有源器件的背面表面上具有某一厚度的保护层,保护材料的面积大于第一面积,并且保护材料具有间隔距离。垂直边缘具有保护层,垂直边缘的保护层填充凹部与垂直边缘齐平。保护材料的间隔距离是半导体器件的厚度与撞击半导体器件的垂直面的工具的角度(θ)的正切值的函数。
Description
技术领域
本发明的实施例涉及半导体器件的封装,更具体地是涉及有修改的晶片级芯片尺寸封装(WLCSP)封装,以保护半导体裸芯片免受损害,从而提高产品的可制造性和质量。
背景技术
电子工业继续依赖于半导体技术的进步,以在更紧凑的区域中实现更高功能的设备。对于许多应用来说,实现较高功能的设备需要将大量的电子器件集成到单个硅晶片中。随着在硅晶片的每个给定区域中电子器件的数量的增加,制造过程变得更加困难。
IC器件的封装对于IC器件最终的性能越来越多地发挥作用。例如,在移动设备(即,移动电话,平板电脑,笔记本电脑,遥控器等)中,WLCSP组件被用于移动设备的组装中。WLCSP组件节省了移动设备中的宝贵空间。组装后,在某些实施例的过程中,客户通过注射成型或外壳封装来封装这些WLCSP器件。对裸WLCSP的手工后处理可能会导致器件损坏,一般应尽量减少对WLCSP器件的处理。
需要一种WLCSP组装过程,能够应对由移动应用需求所提出的挑战。
发明内容
本发明对于半导体器件的封装是有用的。特别是,被配备作为用于制造移动设备的未被封装的裸芯片的WLCSP产品,移动设备将这些设备依次直接封装到印刷电路板上(努力节省移动设备中的宝贵空间),可以使这些未被封装的裸芯片经受住粗暴的处理。该处理会导致破裂或其他潜在的损害,可能直到移动设备到达最终用户才表现出来。因此,用户可能更喜欢由非易碎材料包围的WLCSP产品,以避免在接收用于组 装到用户的移动设备中的产品之前对裸芯片本身造成损害。
用户在具有器件裸芯片的晶片的背面施加保护材料。通过锯切将有源器件裸芯片分离。通过处理,未被封装的裸芯片在其背面表面受到保护材料的保护,保护材料吸收了在组装移动装置期间人工处理的冲击。该工艺还能够被用于带有或不带有焊料球的芯片级封装(CSP)。
在一个示例性实施例中,提出了一种用于组装WLCSP晶片的方法,晶片具有正面表面和背面表面,在正面表面上具有电触点的多个器件裸芯片。该方法包括背面研磨晶片的背面表面至某一厚度。将某一厚度的保护层施加到晶片的背面表面上。将晶片的具有保护层的正面表面安装到锯切箔上。在多个器件裸芯片的锯线中,用具有第一切口的刀片锯切晶片的正面表面,锯切至经背面研磨的晶片厚度的第一深度;再次沿着多个器件裸芯片的锯线,用具有第二切口的刀片锯切晶片,第二切口比第一切口窄,锯切至保护层的厚度的深度。多个器件裸芯片被分离成单个的器件裸芯片。每个单个的器件裸芯片在背面具有保护层,保护层具有距离单个的器件裸芯片的垂直边缘的间隔距离。
在另一个示例性实施例中,提出了一种半导体器件,半导体器件具有正面表面和背面表面,半导体器件具有厚度,半导体器件包括限定在正面表面上的具有某一面积的有源器件,正面表面具有第一面积。保护材料位于半导体器件的背面表面上,保护材料的面积大于第一面积。保护材料和层压膜的组合的间隔距离是半导体器件的厚度与撞击半导体器件的垂直面的工具的角度(θ)的正切值的函数。该实施例的一个特征包括面积与保护材料相同的层压材料;层压材料被夹在背面表面和保护材料的下表面之间。
在一个示例性实施例中,提出了一种用于组装WLCSP晶片的方法,晶片具有正面表面和背面表面,在正面表面上具有电触点的多个器件裸芯片。该方法包括,将晶片安装到研磨箔上;背面研磨晶片的背面表面至某一厚度;在与多个器件裸芯片的锯线相对应的区域中,对晶片的背面表面进行半切割;形成围绕多个器件裸芯片中每一个器件裸芯片的槽,这些槽的宽度是半切割刀片切口的宽度,这些槽的深度是经背面研磨的晶片的厚度的大约50%。在晶片的背面上形成某一厚度的保护层,保护 层填充在槽中并覆盖背面表面。将WLCSP晶片的背面表面安装到锯切箔上。该方法还包括,在多个器件裸芯片的锯线中,用具有第一切口的刀片锯切WLCSP晶片的正面表面,至少锯切至经背面研磨的晶片的第一深度,第一切口小于半切割刀片的切口;再在多个器件裸芯片的锯线中,用具有第二切口的刀片锯切WLCSP晶片的正面表面,第二切口比第一切口窄,并且锯切的深度至少是保护层的厚度。多个器件裸芯片被分离成单个的器件裸芯片。每个单个的器件裸芯片在背面具有保护层,垂直边缘具有由槽形成的凹部,填充凹部的保护层与垂直边缘齐平,并且保护层具有距离单个的器件裸芯片的垂直边缘的间隔距离。
在另一个示例性实施例中,提出一种用于组装WLCSP晶片的方法,晶片具有正面表面和背面表面,在正面表面上具有电触点的多个器件裸芯片。该方法包括,将晶片安装到研磨箔上;背面研磨晶片的背面表面至某一厚度。该方法还包括,在与多个器件裸芯片的锯线相对应的区域中,对晶片的背面表面进行半切割,形成围绕多个器件裸芯片中每一个器件裸芯片的槽,这些槽的宽度是半切割刀片切口的宽度,这些槽的深度是经背面研磨的晶片的厚度的大约50%。在晶片的背面上形成某一厚度的保护层,保护层填充在槽中并覆盖背面表面。将WLCSP晶片的背面表面安装到锯切箔上。在多个器件裸芯片的锯线中,用具有第一切口的刀片锯切WLCSP晶片的正面表面,锯切的深度至少为经背面研磨的厚度和保护层的厚度之和,第一切口小于半切割刀片的切口。拉伸锯切箔并分离多个器件裸芯片得到单个的器件裸芯片。每个单个的器件裸芯片在背面都具有保护层,垂直边缘具有由槽形成的凹部,填充凹部的保护层与垂直边缘齐平,并且保护层与单个的器件裸芯片的垂直边缘大致齐平。
在一个示例性实施例中,提出了一种用于组装WLCSP晶片的方法,晶片具有正面表面和背面表面,在正面表面上具有电触点的多个器件裸芯片。该方法包括将晶片安装到研磨箔上。背面研磨晶片的背面表面至某一厚度。将晶片的第一侧表面安装到锯切箔上。在与多个器件裸芯片的锯线相对应的区域中锯切第二侧表面,第二侧表面与第一侧表面相对,锯切至晶片的经背面研磨的厚度的深度。拉伸锯切箔,以使器件裸芯片 分开。将晶片的正面表面再安装到成型箔上,并去除锯切箔。在被分开的器件裸芯片的背面表面和垂直面上,将器件裸芯片封装在成型材料中,在背面表面上具有某一厚度的成型材料,在垂直面上具有另一厚度的成型材料。去除成型箔,再将WLCSP晶片的背面表面安装到锯切箔上。在多个器件裸芯片的锯线中,锯切成型的WLCSP晶片的正面表面,以使成型的晶片分离成单个的器件裸芯片,在每个单个的器件裸芯片上都具有保护性成型材料。
在另一个示例性实施例中,提出了一种用于组装WLCSP晶片的方法,晶片具有正面表面和背面表面,在正面表面上具有电触点的多个器件裸芯片,该方法包括:将晶片安装到研磨箔上;背面研磨晶片的背面表面至某一厚度。该方法还包括,将晶片的背面表面安装到锯切箔上。在多个器件裸芯片的锯线中,用具有第一切口的刀片锯切WLCSP晶片的正面表面,锯切至经背面研磨的晶片厚度的大约50%的第一深度;再沿着多个器件裸芯片的锯线,用具有第二切口的刀片锯切WLCSP晶片,第二切口比第一切口窄,并且锯切至经背面研磨的晶片厚度的大约90%至大约95%的深度。在锯切之后,拉伸锯切箔,以使晶片分开并且使器件裸芯片分开,现在具有扩张的锯线,导致垂直面上具有突出部分。将晶片的正面表面再安装到成型箔上,并去除锯切箔。在被分开的器件裸芯片的背面表面和垂直面上,用成型材料将器件裸芯片封装在成型材料中,在背面表面上具有某一厚度的成型材料,在垂直面上具有另一厚度的成型材料,突出部分提供成型材料的增强锚定;去除成型箔,再将WLCSP晶片的背面表面安装到锯切箔上。在多个器件裸芯片的扩张的锯线中,锯切成型的WLCSP晶片的正面表面,以使成型的晶片分离成单个的器件裸芯片,在每个单个的器件裸芯片上都具有保护性成型材料。
在一个示例性实施例中,提出了一种半导体器件,半导体器件具有有源器件,正面表面和背面表面,半导体器件具有总厚度。半导体器件包括具有电路的有源器件,有源器件的电路限定在正面表面上,正面表面具有第一面积。在有源器件的背面具有凹部,该凹部的部分深度是有源器件的厚度,该凹部的宽度是部分深度,该凹部在垂直边缘围绕有源器件。在有源器件的背面表面上具有某一厚度的保护层,保护材料的面 积大于第一面积,并且保护材料具有间隔距离;垂直边缘具有保护层,垂直边缘的保护层填充凹部与垂直边缘齐平;以及保护材料的间隔距离是半导体器件的厚度与撞击半导体器件的垂直面的工具的角度的正切值的函数。
上述内容并不代表本文中公开的每一个实施例或每一个方面。在附图以及下面的具体实施方式中提供了对其它方面和示例性实施例的描述。
附图说明
图1示出的是相对于处理工具撞击的角度,保护材料的间隔的程度;
图2A-2C示出的是根据本发明的实施例的具有保护材料的示例器件;
图2A示出的是对示例器件的处理;
图2B示出的是将示例器件放置在印刷电路板上;
图2C示出的是将可选地具有底部填充材料的示例器件焊接到印刷电路板上;
图3是根据本发明的一个实施例的组装过程的流程图;
图4A-4G示出的是通过图3所示的过程进行组装的示例WLCSP器件的横截面;
图5是根据本发明的另一个实施例的组装过程的流程图;
图6A-6G示出的是通过图5所示的过程进行组装的示例性实施例的横截面;
图7是根据本发明的又一个实施例的组装过程的流程图;
图8A-8E示出的是通过图7所示的过程进行组装的示例性实施例的横截面;
图9是根据本发明的一个实施例的组装过程的流程图,该过程具有附加的可选步骤“阶段切割”;
图10A-10H示出的是通过图9所示的具有可选步骤的过程进行组装的示例性实施例;
图11A-11H示出的是通过图9所示的但不具有“阶段切割”的过程进 行组装的示例性实施例;
图12A是根据图9所示的但不具有“阶段切割”的过程组装完成的器件;以及
图12B是根据图9所示的具有“阶段切割”的过程组装完成的器件。
本发明适用于各种修改和替代形式,本发明的细节具体是通过示例的方式呈现在附图中的,下面将进行详细的说明。应当理解,本文中描述的具体实施例并不是用来限制本发明。与此相反,意在覆盖落在由所附权利要求限定的本发明的精神和范围内的所有修改方案、等同方案和替代方案。
具体实施方式
本文中公开的实施例能够避免晶片级芯片尺寸封装(WLCSP)器件在组装时受到损坏。该过程通过将器件安装到比器件裸芯片尺寸大的保护材料上,以此来对硅器件提供机械保护,保护材料在器件的底面上形成边界,这样可以防止组装工具直接接触硅器件,从而避免破碎和其他损坏。这样的过程可以被集成到常规的后端组装当中。
请参阅图1。在一个示例性实施例中,组件100包括厚度为T1的硅器件110。保护角α和厚度T1限定了保护材料的间隔距离T3。例如,为了保护厚度为T1=150μm的器件裸芯片免受工具5以20度的撞击角造成的撞击,大约55μm的间隔是比较合适的。一般,间隔距离为:
T3=tanαT1 (1)
保护材料120和胶115的总厚度T4是由所使用的材料来确定的。间隔量在“厚”刀片和“薄”刀片之间是存在差异的。例如,八英寸晶片(20.32cm)预先研磨掉的厚度T0大约为725μm,而六英寸晶片(15.24cm)预先研磨掉的厚度T0大约为675μm。请注意,这种技术可以被应用到任何尺寸的晶片衬底,并且能够用于十二英寸(30.48cm)的衬底。此外,使用焊料球、焊料凸块、焊盘等的器件受益于保护材料。然而,出于讨论的目的,下面的例子使用焊料凸块。然而,所描述的技术不限于焊料凸块。在示例过程中,WLCSP被研磨成厚度大约为400μm, 焊料凸块的高度大约为200μm。理想的是达到最小的晶片厚度T1,但是这可能会受限于使具有200μm的凸块的晶片变薄的技术能力。在示例过程中,厚度T1可以在大约150μm至大约250μm的范围内。或者,可以在施加焊料凸块的步骤之前对薄晶片进行二次成型。在这种情况下,可以使硅晶片减薄到硅器件110的厚度T1在50μm以下。T2是保护材料120、胶115和硅器件110的总厚度,即T2是T4和T1之和。如果不使用胶115,则厚度T4表示的是保护材料120的厚度;如果使用胶115,则厚度T4表示的是保护材料120和胶115的总厚度。另外,在某些示例过程中,厚度T4至少是100μm。通过胶115层压在硅器件110背面的保护材料120可以是塑料的或者是金属的。塑料材料可以但不必限于 PTFE(聚四氟乙烯),成型材料等。KAPTON是由杜邦公司制造的聚酰亚胺膜(即poly-oxydiphenylene-pyromellitimide:聚氧代二苯撑苯均四酸)的商标名称。保护材料120和用于层压的胶115必须能够承受大约200℃到300℃的温度范围,这在WLCSP器件组装的再流焊过程中是经常遇到的。其他柔性保护材料可以包括但不必限于聚四氟乙烯。某些成型材料可以包括但不必限于住友(例如:x84194)和日立(例如:cel400ZHF4053C)等公司制造的产品。
在一个示例性实施例中,组装的WLCSP器件的总厚度可以在大约360μm至大约400μm的范围内(不包括焊料凸块)。层压材料越厚,对硅器件裸芯片的侧壁保护越大。如果硅裸芯片的厚度可以被减少到大约30μm至大约50μm,则层压的材料将会是大约350μm至大约370μm(如果包括胶在内的话,则是400μm的厚度)。硅厚度的减少是受背面研磨过程的能力以及处理焊料凸块流中的“硅保护层锯切”的能力控制的。
请参阅图2A。在另一个示例性实施例中,WLCSP结构220可以薄至厚度T1大约为50μm,凹部间隔距离T3大约为10μm,角度α大约为10度。施加到晶片背面210的厚保护层230(厚保护层230的厚度T4>150μm)提供了充分的保护,防止了由于工具、镊子、真空棒等造成机械损坏。参阅图2B-2C。受保护的器件结构220被安装到示例的印刷电路衬底260的表面250上。用于将器件结构220安装到印刷电路衬底260上的工具7不再能够损坏器件结构220。通过可选的焊料底部填充材料 280,器件结构270被很好地保护起来。
请参阅图4A-4B。硅衬底400具有初始厚度T0。有源器件420位于衬底410的上表面上。通过背面研磨,使衬底410变薄成厚度Tf。在示例性实施例中,Tf大约为100μm。虚线415表示被研磨掉的衬底材料的量。电触点的区域435将接收焊料凸块或其他电触点类型。请参阅图4C-4D。可以通过图2所示的层压来施加保护层430,或者可以将保护层430二次成型到变薄的背面410上。焊料凸块440被限定在电触点的区域435中。
可以通过对变薄的晶片进行二次成型来施加保护层。在使用坚硬的材料例如金属屏作为保护层的情况下,在接合过程中可以使用粘接剂来接合。更多的柔性保护层例如KAPTON箔片可以使用预先涂敷在箔片上的粘合剂或者预先涂覆在硅晶片上的粘合剂被层压到硅晶片上。金属屏可以是不锈钢,铜,银,金,或其它合金,但并不必限定于这些金属,对金属的选择受成本约束和工艺参数支配。
请参阅图3。在根据本发明的一个示例性实施例中,将WLCSP晶片(正面朝下)安装到研磨箔上310。通过背面研磨使WLCSP晶片变薄315。将具有某一厚度的机械保护层施加到变薄的晶片的背面320。在晶片的正面上,将焊料凸块附接到有源器件焊盘上325。将制备的晶片现在受保护的背面安装到锯切箔上330。用具有第一切口的锯片(例如“厚刀片”),通过正面锯切晶片至变薄的晶片的深度335。用具有第二切口的锯片(例如“薄刀片”),进一步锯切晶片至机械保护层的深度340。使所得到的器件分开(例如,“单一化”)345。从锯带上去除所得到的器件的裸芯片,并将其放置在托盘上或安装到传送带上350。可以根据需要进行额外的电测试,然后器件被打包并运输到最终用户355。
请参阅图4A-4D。具有初始厚度T0的晶片衬底410已经通过背面研磨415变薄。在其上已经施加了机械保护层430。晶片衬底410的正面具有有源器件420。焊料球440附着在器件的焊盘435上。
请参阅图4E至4G。已经施加有保护层430的晶片组件470被附接到锯切膜445上。具有给定“切口”(例如50μm)的第一锯片10在每个有源器件420之间切割至变薄的硅衬底的厚度Tf的深度。具有比第一锯 片10更窄的切口(例如30μm)的第二锯片15切割穿过保护层430的深度至锯切膜445的上表面。现在晶片组件470由分离的器件裸芯片480构成。将分离的器件裸芯片480从锯带445上去除以用于后续加工。取决于所需的间隔的程度,可以将第二刀片调整得更高或更低。可以通过增大锯线的宽度(即,晶片上的相邻IC之间的距离)来增大第一“切口”的宽度。传统的锯的刀片可用于厚度大于300μm的情况,或者可以使用对宽度没有限制的其他蚀刻工艺。对于第二“切口”,也可以使用替代技术,例如导致切口宽度小于15μm的激光烧蚀技术。
请阅图5。在根据本发明的示例过程中,WLCSP晶片被安装到研磨箔上510。通过背面研磨使WLCSP晶片变薄515。在与各个器件裸芯片之间的锯线相对应的区域中,(用具有第一切口的“厚”刀片)部分锯切晶片的背面部分,锯切至变薄的晶片厚度的大约50%的深度520。将机械保护层施加到晶片的背面525;锯线中也填满了机械保护层。可以通过现代影像学技术确定锯线在各个器件之间的正确位置。例如,可以在硅衬底中使用红外(IR)相机,硅衬底对短波红外光是透明的,因此可以观察到其中的特征。将所制备的晶片受保护的背面表面安装到锯切箔上530。将焊料凸块附着到晶片正面的器件焊盘上535。在晶片的正面上,在与部分锯切540相对应的锯切位置中,用具有第二切口的“薄”刀片来锯切晶片545;第二次锯切545的深度为变薄的晶片的深度。所得到的器件是分开的(即“单个的”)550。从锯带上去除所得到的器件裸芯片555,并将其放置在适当的托盘中或传送带上。如果最终用户希望的话,在包装和运输之前可以进行额外的产品测试560。
请参阅图6A至6B。在另一个示例性实施例中,具有有源器件620的硅晶片610,在附着保护层630之前,沿着锯线从背面部分切割至一定深度THALF-CUT。可以通过传统的刀片切割和任何其他适当的技术,如蚀刻或激光烧蚀技术来实现“半切割”45。在图6C-6F中显示了与根据图4E-4G讨论的过程相似的过程。在示例过程中,对于放置在锯切箔645上的晶片,焊料凸块640被附着到有源器件620的接触区域635。用厚切口的锯片65(第一刀片),晶片被锯切到至少晶片厚度的深度和半切割55的厚度的深度;生产过程中要保证薄切口的刀片切割得大于晶片的 厚度小于半切割55的厚度,以致不会留下硅的暴露的侧面。请参阅图6E-6F。用薄切口的锯片75(随后的刀片或第二刀片),继续切割到机械保护层630的深度,直到到达锯切箔645。经过随后的锯切之后,器件被分离成单个的器件610。
请参阅图6G。请注意,硅615的垂直表面受到保护层635的半切割区域655的保护;而且该半切割区域655具有保护层635的额外的突出部分665。进一步减少了未受保护的硅的侧面的面积。
如图1中所示的那样,图6G进一步描绘了厚度T10的器件的对应特征。器件的厚度T10和保护层的厚度T40之和为整个成型器件的厚度T20。间隔角度θ由间隔距离T30来限定。器件裸芯片的侧壁厚度在器件裸芯片的厚度T10和“半切割”的深度THALF-CUT之间是不同的。
请参阅图7。在根据本发明的另一个示例性实施例中,WLCSP被安装到研磨箔上710。在WLCSP晶片的背面通过背面研磨715使WLCSP晶片变薄。用“厚”刀片在背面对晶片进行部分锯切,锯切至变薄的晶片厚度的大约50%的深度。施加背面的保护层,以便填充锯线725。将经涂覆的晶片的涂覆侧安装到锯带上730。在晶片的正面上,焊料凸块被附着到器件的焊盘上735。用“薄”刀片从晶片的正面,在与部分锯切740相对应的位置中锯切晶片,锯切的深度为变薄的晶片的厚度加上保护层的厚度。所得到的器件是分开的745。根据每个最终用户的需要,可以在包装和运输之前进行另外的电测试750。
请参阅图8A-8E。(用具有第一切口的刀片)对具有有源器件裸芯片的经背面研磨的晶片衬底810的背面表面进行部分锯切45。施加成型材料830,并且成型材料830流入部分锯切的切口45中。在正面表面上器件裸芯片焊盘处,附着焊球840。晶片衬底被安装到锯带845上。对晶片衬底810的正面进行第二次锯切65,第二次锯切65所使用的刀片的切口比第一次部分锯切45所使用的刀片的切口窄。在锯切之后,晶片被分离成单个的器件,如图8E所示。器件裸芯片815的背面受到成型材料830的保护。
在示例过程中,根据最终用户的要求,可以在施加保护性成型材料之前对晶片衬底进行单次切割,或者可以对晶片衬底进行台阶切割,台 阶切割在器件裸芯片的硅边缘上形成台阶断面。
表1示出了示例过程的一些参数。
请参阅图9。在示例过程中,晶片衬底的正面被安装到研磨箔上910。通过背面研磨使晶片变薄920。将变薄的晶片的背面表面安装到锯切箔/切割箔上930。在器件的边界(即锯线)处,从晶片衬底的正面将晶片衬底锯切至变薄的晶片的深度940。拉伸锯切箔/切割箔以使器件裸芯片之间的空间变宽960。再将被拉伸的晶片的正面(有源裸芯片表面)安装到成型箔上,并去除锯切箔/切割箔970。将经拉伸分开的器件裸芯片嵌入到成型材料中975。成型材料围绕器件裸芯片的背面表面和垂直面。去除成型箔980。可以将焊球或焊块附着到有源器件上980。将成型的晶片安装到锯切箔/切割箔上985。通过锯切将现在受保护的器件分开990。
在变型的示例性实施例中,晶片可以被切割至变薄的晶片的深度的大约90%至大约99%的深度950。在示例过程中,该深度可以在变薄的晶片的深度的大约90%至大约95%的范围内。当器件裸芯片被拉伸分开时,器件裸芯片将在锯线上分开,这导致在背面表面具有轻微突出的垂直面。该突出部分提供了围绕器件裸芯片的成型材料的增强的锚定。
在参照图9讨论的示例性实施例的另一个变型例中,在将变薄的晶片安装到锯切箔/切割箔920之后,可以对晶片进行“台阶切割”锯切过程925。将变薄的晶片的背面表面安装到切割箔/锯切箔上935。通过晶片正面的锯线进行“宽”切口锯切,锯切至变薄的晶片衬底厚度的大约50%(见图9中的945)。通过第一次切割的中心区域中晶片的剩余区域进行“窄”切口锯切,锯切至变薄的晶片衬底的深度的大约90%至大于95%的深度955。当锯切箔/切割箔被拉伸时960,随着器件裸芯片之间的空间变宽,剩余的未切割的锯线分割开来。该过程如上所述继续进行。
请参阅图10A-10H。在截面图中,根据图9的过程组装晶片衬底。在组装(图10A)设备1000中,在正面1020上具有有源器件的变薄的晶片衬底1010被附接到锯切箔/切割箔1030上。用预定切口的刀片85进行一次切割(图10B),切割深度为变薄的晶片衬底1010的深度;形成了大约刀片切口的宽度的空间。通过拉伸锯切箔/切割箔1030,使该空间增宽了大约3倍(图10C)。被拉伸的组装设备1000的器件裸芯片正面向下再被安装(图10D)到耐高温箔1040上。在被再安装(图10E)之后,成型材料流到被拉伸的组装设备1000上,用厚度为T4的成型材料封装每个器件裸芯片1010。耐高温箔1040被去除,焊料凸块1025被附着到有源器件1020上的裸芯片焊盘位置上。锯切箔/切割箔1060被连接到被封装、拉伸的组件1000的成型侧。第二切口的刀片90切割穿过厚度为T4的成型,以便能够使各个裸芯片1010分开。
请参阅图11A-11H。在示例性实施例中,组件1100被安装到锯切/切割带1130上,其中组件1100具有变薄的晶片(图11A)衬底1110,晶片衬底1110的正面具有有源器件1120。用宽切口的刀片95b,在围绕有源器件裸芯片边界的锯线上,对晶片衬底1110进行第一次切割(切割深度为晶片厚度的大约50%的深度)。用窄切口的刀片95a,接着第一次切割继续进行第二次切割,切割深度为晶片厚度的大约90%至大约95%的深度(图11B)。拉伸锯切带/切割带1130,如图11C所示,器件裸芯片1110和1110a分开(图11C)。分开的裸芯片1110和1110a再被安装到耐高温箔1140上用于后续成型。请注意在器件裸芯片1110和1110a的垂直面上标识的97a,97b,97c。成型材料1150流进来以封装器件裸芯片1110和1110a(图11E)。请参阅图11F-11H。去除耐高温箔1140。焊料球、焊料凸块或者它们的等同物1125、1125a被施加到有源器件的焊盘上,以提供到有源器件1120、1120a的电连接。在组件1100的成型侧,安装锯切带/切割带1160。用具有适当切口的刀片98将成型的器件裸芯片1110、1110a分离开来。
请参阅图12A和12B。图中描绘出了成品1200a和1200b,厚度为T1的器件裸芯片1210a和1210b被厚度为T3和T4的成型材料1250a和1250b封装。成型材料包围器件裸芯片1210a、1210b的背面和垂直面。后续通过成型材料的处理来保护器件裸芯片易碎的边缘。成型材料1250b由于已经流到“断裂的”硅边缘97a和台阶切割97b下面,因此具有额外的机械锚固。通过特定的参数将会确定成型材料和裸芯片的厚度T2,或者在下游系统的组件中可以获得多大垂直空间。
在一个示例的拉伸过程中,可以通过在一个环上推动具有分离的晶片的晶片框架来拉伸设备中的晶片。一个示例的设备被限于将200mm的晶片扩张至大约235mm。另外的35mm(即35000μm)表现为在裸芯片之间平均分布的间隔。当裸芯片的尺寸为1×1mm2时,晶片在X方向和Y方向上具有大约200个间隔。切割刀片在200mm的晶片上造成的原始切口的宽度大约为20μm至25μm。扩张35mm将会使切口间隔增加大约175μm;扩张后最终的切口宽度大约为195μm至大约200μm。
在上面讨论的实施例中,WLCSP器件的背面和垂直面得到了保护,使其免受组装过程中来自后续处理的机械撞击(即镊子,移液器,真空棒等)。材料的厚度T4和间隔距离T3决定了保护程度。
对于本领域技术人员来说,在不脱离所附权利要求中限定的本发明的精神和范围的情况下,可以得到许多其他的实施例。
Claims (5)
1.一种用于组装WLCSP晶片的方法,其特征在于,晶片具有正面表面和背面表面,在正面表面上具有电触点的多个器件裸芯片,该方法包括:
将晶片安装到研磨箔上;
背面研磨晶片的背面表面至某一厚度;
将晶片的背面表面安装到锯切箔上;
在多个器件裸芯片的锯线中,用具有第一切口的刀片锯切WLCSP晶片的正面表面,正面表面与背面表面相对,锯切至经背面研磨的晶片厚度的50%的第一深度;
再沿着多个器件裸芯片的锯线,用具有第二切口的刀片锯切WLCSP晶片,第二切口比第一切口窄,并且锯切至经背面研磨的晶片厚度的90%至95%的深度,使所述晶片的垂直面形成为台阶;
通过拉伸锯切箔来使留在锯线中的剩余晶片材料破裂,以使经背面研磨的晶片分开,导致垂直面上具有突出部分,突出部分提供成型材料的增强锚定;
将晶片的正面表面再安装到成型箔上,并去除锯切箔;
在被分开的器件裸芯片的背面表面和垂直面上,将器件裸芯片封装在成型材料中,在背面表面上具有某一厚度的成型材料,在垂直面上具有另一厚度的成型材料,
去除成型箔;
再将成型的WLCSP晶片的背面表面安装到锯切箔上;以及
在多个器件裸芯片的锯线中,锯切成型的WLCSP晶片的正面表面,以使成型的晶片分离成单个的器件裸芯片,在每个单个的器件裸芯片上都具有保护性成型材料。
2.根据权利要求1所述的方法,其特征在于,去除成型箔后还包括:在器件裸芯片的电触点上安装焊料球或焊料凸块。
3.根据权利要求2所述的方法,其特征在于,成型材料包括柔性保护材料。
4.根据权利要求1所述的方法,其特征在于,背面表面上的成型材料的厚度至少为100μm。
5.根据权利要求4所述的方法,其特征在于,垂直面上的成型材料的厚度至少为50μm。
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201261717594P | 2012-10-23 | 2012-10-23 | |
US61/717,594 | 2012-10-23 | ||
US201261727204P | 2012-11-16 | 2012-11-16 | |
US61/727,204 | 2012-11-16 | ||
US201361816609P | 2013-04-26 | 2013-04-26 | |
US61/816,609 | 2013-04-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103779237A CN103779237A (zh) | 2014-05-07 |
CN103779237B true CN103779237B (zh) | 2018-06-19 |
Family
ID=50484621
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310491772.5A Active CN103779241B (zh) | 2012-10-23 | 2013-10-18 | 晶片级芯片规模封装(wlcsp)的保护 |
CN201310495065.3A Active CN103779237B (zh) | 2012-10-23 | 2013-10-21 | 用于组装wlcsp晶片的方法及半导体器件 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310491772.5A Active CN103779241B (zh) | 2012-10-23 | 2013-10-18 | 晶片级芯片规模封装(wlcsp)的保护 |
Country Status (2)
Country | Link |
---|---|
US (2) | US9245804B2 (zh) |
CN (2) | CN103779241B (zh) |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10186458B2 (en) * | 2012-07-05 | 2019-01-22 | Infineon Technologies Ag | Component and method of manufacturing a component using an ultrathin carrier |
US9620413B2 (en) | 2012-10-02 | 2017-04-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier in semiconductor packaging |
US9496195B2 (en) | 2012-10-02 | 2016-11-15 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP |
US20140110826A1 (en) * | 2012-10-23 | 2014-04-24 | Nxp B.V. | Backside protection for a wafer-level chip scale package (wlcsp) |
US9245804B2 (en) | 2012-10-23 | 2016-01-26 | Nxp B.V. | Using a double-cut for mechanical protection of a wafer-level chip scale package (WLCSP) |
US9704824B2 (en) * | 2013-01-03 | 2017-07-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming embedded wafer level chip scale packages |
US9721862B2 (en) | 2013-01-03 | 2017-08-01 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages |
JP6235279B2 (ja) * | 2013-09-18 | 2017-11-22 | 株式会社ディスコ | ウエーハの加工方法 |
US10720495B2 (en) * | 2014-06-12 | 2020-07-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing method thereof |
US20160005653A1 (en) * | 2014-07-02 | 2016-01-07 | Nxp B.V. | Flexible wafer-level chip-scale packages with improved board-level reliability |
CN104716076B (zh) * | 2015-03-20 | 2017-05-24 | 上海华力微电子有限公司 | 芯片压胶装置及芯片压胶方法 |
US9899285B2 (en) * | 2015-07-30 | 2018-02-20 | Semtech Corporation | Semiconductor device and method of forming small Z semiconductor package |
US10319639B2 (en) * | 2017-08-17 | 2019-06-11 | Semiconductor Components Industries, Llc | Thin semiconductor package and related methods |
KR101843621B1 (ko) * | 2015-12-04 | 2018-03-29 | 앰코테크놀로지코리아(주) | 반도체 패키지의 제조 방법 및 이를 이용한 반도체 패키지 |
US9842776B2 (en) | 2016-01-13 | 2017-12-12 | Nxp B.V. | Integrated circuits and molding approaches therefor |
US10177021B2 (en) | 2016-01-13 | 2019-01-08 | Nxp B.V. | Integrated circuits and methods therefor |
US9799629B2 (en) | 2016-02-11 | 2017-10-24 | Nxp B.V. | Integrated circuit dies with through-die vias |
US20170256432A1 (en) * | 2016-03-03 | 2017-09-07 | Nexperia B.V. | Overmolded chip scale package |
JP2017162876A (ja) * | 2016-03-07 | 2017-09-14 | 株式会社ジェイデバイス | 半導体パッケージの製造方法 |
US20170338184A1 (en) * | 2016-05-19 | 2017-11-23 | Texas Instruments Incorporated | Method of dicing integrated circuit wafers |
US10121765B2 (en) | 2017-03-01 | 2018-11-06 | Semiconductor Components Industries, Llc | Semiconductor device and method of forming WLCSP |
JP6955918B2 (ja) * | 2017-07-03 | 2021-10-27 | 株式会社ディスコ | 基板の加工方法 |
US10522440B2 (en) * | 2017-11-07 | 2019-12-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of manufacturing the same |
US10403506B2 (en) | 2018-01-07 | 2019-09-03 | Infineon Technologies Ag | Separation of workpiece with three material removal stages |
US10319696B1 (en) * | 2018-05-10 | 2019-06-11 | Micron Technology, Inc. | Methods for fabricating 3D semiconductor device packages, resulting packages and systems incorporating such packages |
JP7130323B2 (ja) * | 2018-05-14 | 2022-09-05 | 株式会社ディスコ | ウェーハの加工方法 |
KR102677777B1 (ko) * | 2019-04-01 | 2024-06-25 | 삼성전자주식회사 | 반도체 패키지 |
JP2021048205A (ja) * | 2019-09-17 | 2021-03-25 | キオクシア株式会社 | 半導体装置の製造方法 |
CN113053813A (zh) * | 2019-12-27 | 2021-06-29 | 美光科技公司 | 形成具有用于堆叠裸片封装的周边轮廓的半导体裸片的方法 |
US20210202318A1 (en) * | 2019-12-27 | 2021-07-01 | Micron Technology, Inc. | Methods of forming semiconductor dies with perimeter profiles for stacked die packages |
US11605570B2 (en) * | 2020-09-10 | 2023-03-14 | Rockwell Collins, Inc. | Reconstituted wafer including integrated circuit die mechanically interlocked with mold material |
US11908831B2 (en) | 2020-10-21 | 2024-02-20 | Stmicroelectronics Pte Ltd | Method for manufacturing a wafer level chip scale package (WLCSP) |
US11869863B2 (en) * | 2020-12-03 | 2024-01-09 | Shinko Electric Industries Co., Ltd. | Semiconductor device |
CN113400380A (zh) * | 2021-06-17 | 2021-09-17 | 河南卓耐新材料技术有限公司 | 一种环氧台面快速成型机及其使用方法 |
US20230098907A1 (en) * | 2021-09-30 | 2023-03-30 | Texas Instruments Incorporated | Package geometries to enable visual inspection of solder fillets |
CN114604615A (zh) * | 2022-03-24 | 2022-06-10 | 广州金智为电气有限公司 | 一种一体化加工设备 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4722130A (en) * | 1984-11-07 | 1988-02-02 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
CN1967775A (zh) * | 2005-11-18 | 2007-05-23 | 半导体元件工业有限责任公司 | 半导体部件及其制造方法 |
TW200941686A (en) * | 2007-10-26 | 2009-10-01 | 3D Plus | Process for the vertical interconnection of 3D electronic modules by vias |
Family Cites Families (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2541624C2 (de) | 1975-09-18 | 1982-09-16 | Ibm Deutschland Gmbh, 7000 Stuttgart | Wässrige Ätzlösung und Verfahren zum Ätzen von Polymerfilmen oder Folien auf Polyimidbasis |
US6338980B1 (en) | 1999-08-13 | 2002-01-15 | Citizen Watch Co., Ltd. | Method for manufacturing chip-scale package and manufacturing IC chip |
JP3339472B2 (ja) * | 1999-08-24 | 2002-10-28 | セイコーエプソン株式会社 | 半導体装置及びその製造方法 |
JP2001176898A (ja) * | 1999-12-20 | 2001-06-29 | Mitsui High Tec Inc | 半導体パッケージの製造方法 |
TW451436B (en) | 2000-02-21 | 2001-08-21 | Advanced Semiconductor Eng | Manufacturing method for wafer-scale semiconductor packaging structure |
US8076216B2 (en) | 2008-11-11 | 2011-12-13 | Advanced Inquiry Systems, Inc. | Methods and apparatus for thinning, testing and singulating a semiconductor wafer |
US6521485B2 (en) | 2001-01-17 | 2003-02-18 | Walsin Advanced Electronics Ltd | Method for manufacturing wafer level chip size package |
JP2003124392A (ja) * | 2001-10-15 | 2003-04-25 | Sony Corp | 半導体装置及びその製造方法 |
US6964881B2 (en) | 2002-08-27 | 2005-11-15 | Micron Technology, Inc. | Multi-chip wafer level system packages and methods of forming same |
JP2005064231A (ja) * | 2003-08-12 | 2005-03-10 | Disco Abrasive Syst Ltd | 板状物の分割方法 |
US7378297B2 (en) * | 2004-07-01 | 2008-05-27 | Interuniversitair Microelektronica Centrum (Imec) | Methods of bonding two semiconductor devices |
US7101620B1 (en) * | 2004-09-07 | 2006-09-05 | National Semiconductor Corporation | Thermal release wafer mount tape with B-stage adhesive |
SG130055A1 (en) * | 2005-08-19 | 2007-03-20 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices |
JP4764159B2 (ja) | 2005-12-20 | 2011-08-31 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP4691455B2 (ja) | 2006-02-28 | 2011-06-01 | 富士通株式会社 | 半導体装置 |
KR100846569B1 (ko) | 2006-06-14 | 2008-07-15 | 매그나칩 반도체 유한회사 | Mems 소자의 패키지 및 그 제조방법 |
US7682874B2 (en) | 2006-07-10 | 2010-03-23 | Shanghai Kaihong Technology Co., Ltd. | Chip scale package (CSP) assembly apparatus and method |
US7700458B2 (en) | 2006-08-04 | 2010-04-20 | Stats Chippac Ltd. | Integrated circuit package system employing wafer level chip scale packaging |
US7939916B2 (en) | 2007-01-25 | 2011-05-10 | Analog Devices, Inc. | Wafer level CSP packaging concept |
US7585750B2 (en) * | 2007-05-04 | 2009-09-08 | Stats Chippac, Ltd. | Semiconductor package having through-hole via on saw streets formed with partial saw |
US7825010B2 (en) | 2007-06-07 | 2010-11-02 | Micron Technology, Inc. | Die singulation methods |
US7553752B2 (en) * | 2007-06-20 | 2009-06-30 | Stats Chippac, Ltd. | Method of making a wafer level integration package |
US9460951B2 (en) | 2007-12-03 | 2016-10-04 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of wafer level package integration |
US8039303B2 (en) | 2008-06-11 | 2011-10-18 | Stats Chippac, Ltd. | Method of forming stress relief layer between die and interconnect structure |
KR101493872B1 (ko) * | 2008-08-20 | 2015-02-17 | 삼성전자주식회사 | 백그라인딩-언더필 필름, 그 형성방법, 이를 이용한 반도체패키지 및 그 형성방법 |
US7888181B2 (en) | 2008-09-22 | 2011-02-15 | Stats Chippac, Ltd. | Method of forming a wafer level package with RDL interconnection over encapsulant between bump and semiconductor die |
JP2010192818A (ja) * | 2009-02-20 | 2010-09-02 | Casio Computer Co Ltd | 半導体装置の製造方法 |
JP2011159694A (ja) * | 2010-01-29 | 2011-08-18 | Hitachi Chem Co Ltd | 半導体装置の製造方法、それにより得られる半導体装置及びそれに用いるダイシングフィルム一体型チップ保護フィルム |
WO2011160867A1 (en) | 2010-06-23 | 2011-12-29 | Asml Holding N.V. | Pneumatic bearing with bonded polymer film wear surface and production method thereof |
US20120049334A1 (en) * | 2010-08-27 | 2012-03-01 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Leadframe as Vertical Interconnect Structure Between Stacked Semiconductor Die |
US8659152B2 (en) * | 2010-09-15 | 2014-02-25 | Osamu Fujita | Semiconductor device |
JP2012069747A (ja) * | 2010-09-24 | 2012-04-05 | Teramikros Inc | 半導体装置およびその製造方法 |
KR101715761B1 (ko) | 2010-12-31 | 2017-03-14 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
US9679863B2 (en) | 2011-09-23 | 2017-06-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming interconnect substrate for FO-WLCSP |
US20140110826A1 (en) | 2012-10-23 | 2014-04-24 | Nxp B.V. | Backside protection for a wafer-level chip scale package (wlcsp) |
US9245804B2 (en) | 2012-10-23 | 2016-01-26 | Nxp B.V. | Using a double-cut for mechanical protection of a wafer-level chip scale package (WLCSP) |
-
2013
- 2013-08-14 US US13/967,084 patent/US9245804B2/en active Active
- 2013-08-14 US US13/967,164 patent/US9196537B2/en active Active
- 2013-10-18 CN CN201310491772.5A patent/CN103779241B/zh active Active
- 2013-10-21 CN CN201310495065.3A patent/CN103779237B/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4722130A (en) * | 1984-11-07 | 1988-02-02 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
CN1967775A (zh) * | 2005-11-18 | 2007-05-23 | 半导体元件工业有限责任公司 | 半导体部件及其制造方法 |
TW200941686A (en) * | 2007-10-26 | 2009-10-01 | 3D Plus | Process for the vertical interconnection of 3D electronic modules by vias |
Also Published As
Publication number | Publication date |
---|---|
CN103779241B (zh) | 2017-01-18 |
CN103779241A (zh) | 2014-05-07 |
US20140138855A1 (en) | 2014-05-22 |
US9245804B2 (en) | 2016-01-26 |
CN103779237A (zh) | 2014-05-07 |
US9196537B2 (en) | 2015-11-24 |
US20140110842A1 (en) | 2014-04-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103779237B (zh) | 用于组装wlcsp晶片的方法及半导体器件 | |
CN101339910B (zh) | 晶片级芯片尺寸封装的制造方法 | |
US7745261B2 (en) | Chip scale package fabrication methods | |
US7727875B2 (en) | Grooving bumped wafer pre-underfill system | |
CN105374783B (zh) | 半导体边界保护密封剂 | |
US20160225733A1 (en) | Chip Scale Package | |
US9240398B2 (en) | Method for producing image pickup apparatus and method for producing semiconductor apparatus | |
WO2008109457A1 (en) | Methods for fabricating packaged semiconductor components | |
US8173488B2 (en) | Electronic device and method of manufacturing same | |
US6750082B2 (en) | Method of assembling a package with an exposed die backside with and without a heatsink for flip-chip | |
KR100679684B1 (ko) | 외곽에 보호층이 형성된 웨이퍼 레벨 반도체 소자 제조방법 | |
JP2006261299A (ja) | 半導体装置の製造方法および半導体装置 | |
TWI308781B (en) | Semiconductor package structure and method for separating package of wafer level package | |
KR102631710B1 (ko) | 웨이퍼의 가공 방법 | |
JP2022123045A (ja) | 半導体装置の製造方法 | |
JP2007116141A (ja) | Wlpのパッケージ分離方法 | |
KR102631711B1 (ko) | 웨이퍼의 가공 방법 | |
TW201911477A (zh) | 半導體製程及半導體結構 | |
TW200805521A (en) | A packaging structure with protective layers and manufacture method thereof | |
JP2008016606A (ja) | 半導体装置及びその製造方法 | |
US7972904B2 (en) | Wafer level packaging method | |
US20170011979A1 (en) | Chip Scale Package | |
CN106783642A (zh) | 一种芯片及其封装方法 | |
JP2005191485A (ja) | 半導体装置 | |
KR102627412B1 (ko) | 웨이퍼의 가공 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |