CN101339910B - 晶片级芯片尺寸封装的制造方法 - Google Patents

晶片级芯片尺寸封装的制造方法 Download PDF

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CN101339910B
CN101339910B CN2008100962400A CN200810096240A CN101339910B CN 101339910 B CN101339910 B CN 101339910B CN 2008100962400 A CN2008100962400 A CN 2008100962400A CN 200810096240 A CN200810096240 A CN 200810096240A CN 101339910 B CN101339910 B CN 101339910B
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level chip
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郭祖宽
许国经
李建勋
吴俊毅
梁裕民
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开一种晶片级芯片尺寸封装(wafer-level chip-scale package)的制造方法，包括：形成多个导电柱于一半导体晶片的一第一表面上，该半导体晶片中具有多个裸片；以干蚀刻形成至少一沟槽于该半导体晶片的该第一表面中，其中该沟槽定义至少一分界线于所述多个裸片间；沉积一包覆材料于该第一表面上；穿过该包覆材料切割一凹陷于该沟槽中，其中该切割留下一部分半导体材料于该半导体晶片的一第二面上；以及研磨该第二面以移除该部分半导体材料，并分离所述多个裸片。本发明的优点为借由使用干蚀刻在沟槽中产生较平坦的侧壁，减低了破裂或形成缺口的风险。

Description

晶片级芯片尺寸封装的制造方法
技术领域
本发明涉及一种晶片级芯片尺寸封装，且特别涉及借由干蚀刻来增加在晶片级芯片尺寸封装晶片中分离的裸片的可靠度。
背景技术
过去数十年间电子技术与半导体封装的发展影响了整个电子产业。表面黏着技术(surface mount technology，SMT)、球格阵列(ball grid array，BGA)、基板栅格阵列(land grid array，LGA)为集成电路高产能装配的重要步骤，且同时允许减少印刷电路板上的连接垫间距。一般经封装的集成电路是借由细金线来连结在裸片上的金属垫与分布在铸模树脂封装体外的电极。双列直插式封装(dual inline package，DIP)或四面扁平封装(quad flat package，QFP)为现今集成电路封装的基本结构。然而增加封装体外围的针脚数通常会导致铅线间距太短，而限制了封装芯片的基板架设。
芯片级或芯片尺寸封装(chip-size packaging，CSP)、球格阵列、基板栅格阵列等正好是使电极密集而不需大幅增加封装尺寸的方法。芯片级封装提供了于芯片尺寸上的晶片封装。芯片级封装通常产生1.2倍裸片尺寸内的封装体，其大幅减低了元件潜在的尺寸。虽然这些发展已使电子元件缩小化，但永远要求朝向更小、更轻与更薄的消费者产品促使封装需要更加缩小化。
为了满足朝向缩小化与功能性的市场需求，近几年引进晶片级芯片尺寸封装以增加密度、性能与成本效益，而减少了电子封装产业中元件的重量与尺寸。在晶片级芯片尺寸封装中，一般直接在裸片上产生封装，并由球格阵列、凸块电极(bump electrode)、基板栅格阵列与上述的类似提供接点。近来所发展的电子元件，例如移动电话、便携电脑、摄录影机、个人数字助理(personal digital assistants，PDAs)等使用小型、轻、薄与非常密集的封装集成电路。使用晶片级芯片尺寸封装可封装针脚数目较少的较小裸片，可增加同一晶片上的芯片数目，因此通常较具有优势与经济效益。
在传统制造工艺中，同一晶片上会形成许多独自的裸片。一旦完成了电路与封装结构，即进行裸片切割以分离各裸片。在此工艺中，将具有最多可达上千个电路的晶片切割成许多独立的小块，各称为裸片。沿着晶片上的切割线可安全的进行裸片切割而不会损伤到电路。切割线的宽度一般非常的小，通常约为100μm。一般以高准度水冷圆锯执行切割，其具有钻石尖端锯齿。
而上述技术的缺点为裸片边缘有时可能会破裂或形成缺口而减低了集成电路芯片的完整度与可靠度。有缺陷的裸片提高了单一集成电路裸片的成本。在一些应用中，常借由激光在晶片界线区域中形成裸片切割沟槽，以使切割线区域在切割工艺中较不易破裂或产生缺口。虽然激光裸片切割沟槽减少了破裂或产生缺口的机会，但此种损害仍然偶尔会发生。
Kinsman等人于U.S.Patent No.6,717,245中提到一种分离或颗粒切割在晶片上的裸片的方法。Kinsman提出以一裸片锯或湿蚀刻在单独裸片之间切割出一通道穿过位于下方的晶片的有源层。之后以一包覆材料填满这些通道以将各裸片的有源区周围密封包覆起来。之后使用其他裸片锯切穿各通道以分离或颗粒切割各裸片。包覆材料帮助避免晶片产生缺口或破裂，但由于在操作上仍使用裸片锯，此种损害通常仍持续发生。
在芯片尺寸封装(Chip-Scale-Package，CSP)中，通常使用树脂或聚合物的包覆层将晶片密封，包括裸片切割沟槽。其他切割芯片尺寸封装晶片的方法于Ohuchi的U.S.Patent No.6,107,164中有叙述。Ohuchi教示沟槽的深度为约2/3晶片的深度是优选的。之后涂上包覆层将沟槽填满。在另外的工艺中，Ohuchi提出研磨晶片背面以移除硅且露出填满包覆材料的沟槽。在将晶背薄化之后以一窄刀在露出的沟槽切割晶片。同样地在切割沟槽加入保护层帮助避免因晶片切割对裸片的一些损害。然而，损害仍然持续发生，因为仍然以裸片锯切割裸片。
发明内容
借由本发明优选实施例可解决或克服上述问题，其利用于蚀刻在晶片中形成平滑侧壁沟槽以定义多个裸片界线。一包覆层沉积于半导体晶片的正面上。包覆层密封并保护裸片的有源元件以及导电柱或杆。
在研磨包覆层以露出导电柱或杆之后，以一裸片锯切穿在沟槽中的包覆层，并在晶片背面上留下一小部分半导体基底。借由研磨或抛光晶背露出在沟槽底部的半导体基底材料以分离单独的裸片。
本发明提供一种晶片级芯片尺寸封装的制造方法，包括：形成多个导电柱于一半导体晶片的一第一表面上，该半导体晶片中具有多个裸片；以干蚀刻形成至少一沟槽于该半导体晶片的该第一表面中，其中该沟槽定义至少一分界线于所述多个裸片间；沉积一包覆材料于该第一表面上；穿过该包覆材料切割一凹陷于该沟槽中，其中该切割留下一部分半导体材料于该半导体晶片的一第二面上；以及研磨该第二面以移除该部分半导体材料，并分离所述多个裸片。
本发明提供另一种晶片级芯片尺寸封装的制造方法，包括：形成多个导电柱于一半导体晶片的正面上；以干蚀刻法形成多个沟槽于该正面中；涂布一包覆层包覆该正面；在所述多个沟槽中切割多个凹陷至一预定深度；以及研磨该半导体晶片的背面至所述多个凹陷以分离该半导体晶片上的多个裸片。
本发明提供又一种晶片级芯片尺寸封装的制造方法，包括：形成多个晶片级接点于一半导体晶片的一正面表面上，该半导体晶片中具有多个裸片；干蚀刻多个沟槽于该正面上，所述多个沟槽定义一或多个分界线于所述多个裸片间；以一包覆材料密封该正面；在所述多个沟槽中锯穿该包覆材料，以留下一部分基底材料于该半导体晶片的背面上；以及借由研磨该背面以移除该部分基底材料，并分离所述多个裸片。
本发明优选实施例的一优点为借由使用干蚀刻在沟槽中产生较平坦的侧壁。相较于借由湿蚀刻、切割或激光形成沟槽造成较粗糙的侧壁而言，较平坦的表面减低了破裂或形成缺口的风险。
本发明优选实施例更进一步的优点为在研磨或抛光晶背以分离单独的裸片前借由切割一凹陷进入晶片来改善分离的裸片的品质。当直接从切割工艺分离或颗粒切割裸片时，破裂或形成缺口的机会减少，特别是具有不超过60μm的切割道时。
附图说明
为了让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举优选实施例，并配合所附图示，作详细说明如下：
图1A显示根据本发明一实施例晶片部分执行一晶片级芯片尺寸封装工艺的早期阶段的剖面图。
图1B显示根据本发明一实施例晶片部分在晶片级芯片尺寸封装工艺中的剖面图。
图1C显示根据本发明一实施例晶片部分在晶片级芯片尺寸封装工艺中的剖面图。
图1D显示根据本发明一实施例晶片部分在晶片级芯片尺寸封装工艺中的剖面图。
图1E显示根据本发明一实施例晶片部分在晶片级芯片尺寸封装工艺中的剖面图。
图1F显示根据本发明一实施例在晶片级芯片尺寸封装工艺后形成经颗粒切割的裸片。
图2显示本发明一实施例的晶片级芯片尺寸封装工艺步骤的流程图。
并且，上述附图中的附图标记说明如下：
10      晶片部分
100     硅基底
101     绝缘层
102     铜柱
103     裸片沟槽
104     包覆层
105     焊球
106     凹陷
11、12  裸片
107     晶背
200多个导电柱形成在一半导体晶片的一第一面上，而半导体晶片中具有多个裸片。
201干蚀刻至少一沟槽(约100-150μm深与60μm宽)，进入半导体晶片的第一表面，其中上述沟槽定义至少一分界线于多个裸片间。
202  沉积一包覆材料层于第一表面上。
203  平坦化包覆层以露出导电柱的接点。
204  穿过包覆层在每个沟槽切割一凹陷(宽度最大60μm)，其中该切割在半导体晶片的第二面上留下一部分半导体材料(约100μm厚)。
205  研磨半导体晶片的第二面以移除剩余的部分半导体材料，而此研磨将各裸片分开。
具体实施方式
本发明的优选实施例将以铜柱实施晶片级芯片尺寸封装的硅晶片来举例说明。然而本发明也可应用于其他晶片或工艺材料。
图1A显示根据本发明一实施例晶片部分10在进行一晶片级芯片尺寸封装工艺的早期阶段的剖面图。晶片部分10只为使用于制造半导体集成电路元件的较大晶片的一小部分。晶片部分10包括硅基底100与绝缘层101，其作为集成电路元件的保护层。在晶片部分10的顶部形成铜柱102作为晶片级芯片尺寸封装的一部分。铜柱102提供电连接至晶片部分10中的集成电路元件的有源区。
需注意的是，在本发明的额外及/或替代实施例中，晶片级接点包括导电柱或杆(例如铜柱102)可以其他材料来形成，例如铝、金、导电合金或上述的类似物。在实施例中使用铜并不代表特别限制材料的使用。
图1B为根据本发明一实施例晶片部分10在晶片级芯片尺寸封装工艺中的剖面图。使用一干蚀刻剂在晶片部分10中形成具有平滑侧壁的裸片沟槽103。与切割或激光所形成的沟槽相比，较平滑的侧壁减少了裸片切割时破裂或形成缺口的风险。
可使用各种方法与化学药品/气体来干蚀刻裸片沟槽103，例如离子研磨蚀刻(ion mill etching)、等离子体溅击、等离子体蚀刻、反应性离子蚀刻等。可使用的气体例如CF4、SF6、CHF3+O2、CF4+H2、Cl2、Cl2+BCl3。
在本发明一优选实施例中，将裸片沟槽，例如裸片沟槽103蚀刻至约100-150μm的深度，而宽度为约60μm。
图1C为根据本发明一实施例晶片部分10在晶片级芯片尺寸封装工艺中的剖面图。在晶片部分10之上沉积包覆层104。包覆层104在铜柱102、绝缘层101与基底100之上。包覆层104可有效密封最后自晶片产生的任何集成电路元件。为了露出铜柱102的接触点，借由例如化学机械研磨等工艺来平坦化包覆层104。此平坦化移除包覆层104的部分以露出铜柱的末端且也使晶片部分10形成一平坦的表面。
需注意的是，在本发明中可使用不同形式的材料来作为包覆层104。可使用材料例如环氧树脂或其他树脂以涂布方式、印刷或压印形成在晶片的正面上。此外，包覆层材料可为有机材料。
图1D为根据本发明一实施例晶片部分10在晶片级芯片尺寸封装工艺中的剖面图。晶片级芯片尺寸封装可以各种接点形式提供外部接点，例如焊球、焊接凸块等。图1D显示在露出的铜柱102的接点上形成焊球105。焊球105可因此借由铜柱102在集成电路元件外部与集成电路之间提供电连接。
需注意的是，可使用各种导电方法借由铜柱102提供至集成电路的外部连接。可制造连接元件例如柱、杆、凸块等来取代焊球105以提供晶片级芯片尺寸封装。本发明不限于只使用如图1D中所示的焊球。
图1E为根据本发明一实施例晶片部分10在晶片级芯片尺寸封装工艺中的剖面图。当开始进行裸片分离时，裸片锯在裸片沟槽103中切割出一50μm宽的凹陷106。裸片锯切穿包覆层104且进入晶片部分10的圆部分10基底100。裸片锯并未切穿晶片部分10，而是留下一小部分的小量的基底材料与晶片相连。剩余的基底材料优选能足够维持与晶片在一起，而可借由传统晶片制造运送机具来移动的单一单元。基底剩余部分的厚度如100μm。
需注意的是，可根据裸片尺寸的不同，以不同宽度的凹陷或通道来切穿晶片沟槽。本发明的实施例特别适用于宽度小于60μm的凹陷或通道。
图1F为根据本发明一实施例在晶片级芯片尺寸封装工艺后形成的单颗裸片11与12。在裸片锯切割一凹陷106(图1E)进入晶片后，在晶背107实施一研磨工艺，例如化学机械研磨等。研磨工艺移除剩余的基底材料，其分离晶片中的各裸片。借由在晶片部分10切割一特定深度且之后从晶背107研磨剩余的基底，所形成的裸片11与12具有较少的破裂或缺口，因此产生一更可靠的半导体集成电路元件。
图2为本发明一实施例的晶片级芯片尺寸封装工艺步骤的流程图。在步骤200中，多个导电柱形成在一半导体晶片的一第一面上，而半导体晶片中具有多个裸片。于步骤201中，干蚀刻至少一沟槽(约100-150μm深与60μm宽)，进入半导体晶片的第一表面，其中上述沟槽定义至少一分界线于多个裸片间。在步骤202中，沉积一包覆材料层于第一表面上，在步骤203中，平坦化包覆层以露出导电柱的接点。在步骤204中，穿过包覆层在每个沟槽切割一凹陷(宽度最大60μm)，其中该切割在半导体晶片的第二面上留下一部分半导体材料(约100μm厚)。在步骤205中，研磨半导体晶片的第二面以移除剩余的部分半导体材料，借此研磨将各裸片分开。
虽然本发明已以优选实施例公开如上，然而其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作些许的更动与润饰，因此本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (15)

1.一种晶片级芯片尺寸封装的制造方法，包括：
形成多个导电柱于一半导体晶片的一第一表面上，该半导体晶片中具有多个裸片；
以干蚀刻形成至少一沟槽于该半导体晶片的该第一表面中，其中该沟槽定义至少一分界线于所述多个裸片间；
沉积一包覆材料于该第一表面上；
穿过该包覆材料切割一凹陷于该沟槽中，其中该切割使该凹陷切穿该沟槽并留下一部分半导体材料于该半导体晶片的一第二面上；以及
研磨该第二面以移除该部分半导体材料，并分离所述多个裸片。
2.如权利要求1所述的晶片级芯片尺寸封装的制造方法，还包括平坦化该包覆材料层以露出所述多个导电柱。
3.如权利要求1所述的晶片级芯片尺寸封装的制造方法，其中该沟槽的深度为100-150μm。
4.如权利要求1所述的晶片级芯片尺寸封装的制造方法，其中该沟槽的宽度为60μm。
5.如权利要求1所述的晶片级芯片尺寸封装的制造方法，其中该部分半导体材料的厚度为100μm。
6.如权利要求1所述的晶片级芯片尺寸封装的制造方法，其中该凹陷的宽度不超过60μm。
7.如权利要求1所述的晶片级芯片尺寸封装的制造方法，其中该包覆材料包括一有机材料。
8.如权利要求1所述的晶片级芯片尺寸封装的制造方法，其中该干蚀刻包括：离子研磨蚀刻、等离子体溅击、等离子体蚀刻或反应性离子蚀刻。
9.一种晶片级芯片尺寸封装的制造方法，包括：
形成多个导电柱于一半导体晶片的正面上；
以干蚀刻法形成多个沟槽于该正面中，其中该沟槽定义至少一分界线于该半导体晶片的多个裸片间；
涂布一包覆层包覆该正面；
在所述多个沟槽中切割多个凹陷至一预定深度，其中该预定深度大于沟槽深度；以及
研磨该半导体晶片的背面至所述多个凹陷以分离该半导体晶片上的该多个裸片。
10.如权利要求9所述的晶片级芯片尺寸封装的制造方法，还包括平坦化该包覆层以露出所述多个导电柱。
11.如权利要求9所述的晶片级芯片尺寸封装的制造方法，其中所述多个沟槽的深度为100-150μm，而宽度为60μm。
12.如权利要求9所述的晶片级芯片尺寸封装的制造方法，其中从所述多个凹陷的底部至该背面的距离为60μm。
13.如权利要求9所述的晶片级芯片尺寸封装的制造方法，其中所述多个凹陷的宽度不超过60μm。
14.如权利要求9所述的晶片级芯片尺寸封装的制造方法，其中该包覆层由一有机材料形成。
15.如权利要求9所述的晶片级芯片尺寸封装的制造方法，其中形成所述多个沟槽的方法包括：离子研磨蚀刻、等离子体溅击、等离子体蚀刻或反应性离子蚀刻。
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