JP4764159B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4764159B2 JP4764159B2 JP2005367211A JP2005367211A JP4764159B2 JP 4764159 B2 JP4764159 B2 JP 4764159B2 JP 2005367211 A JP2005367211 A JP 2005367211A JP 2005367211 A JP2005367211 A JP 2005367211A JP 4764159 B2 JP4764159 B2 JP 4764159B2
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/12—All metal or with adjacent metals
- Y10T428/12389—All metal or with adjacent metals having variation in thickness
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24926—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including ceramic, glass, porcelain or quartz layer
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
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Description
前記放熱板の前記熱伝導材料と接する面において、前記熱伝導材料が接する箇所の表面粗さは、前記熱伝導材料が接しない箇所の表面粗さよりも小さく、前記熱伝導材料が接しない箇所の表面は、アルミニウムシリコンカーバイド粉末の焼成体であり、前記熱伝導材料が接する箇所の表面は、アルミニウムシリコンカーバイド粉末の焼成体上にアルミ箔を配設したものであることを特徴とする半導体装置が提供される。
先ず、図1乃至図4を参照して本発明に係る半導体装置の第1の実施の形態について説明する。
次に、図5を参照して本発明に係る半導体装置の第1の実施の形態について説明する。
(付記1) 基板と、
前記基板の一方の主面に搭載された半導体素子と、
前記半導体素子近傍周辺に搭載された複数の受動素子と、
前記半導体素子の背面に熱伝導材料を介して接続され、前記基板上に搭載されて放熱板とを有する半導体装置であって、
前記放熱板の前記熱伝導材料と接する面における表面粗さは、当該面の全面において均一ではないことを特徴とする半導体装置。
(付記2) 付記1記載の半導体装置であって、
前記熱伝導材料が接する前記放熱板の前記面において、前記熱伝導材料が接する箇所の表面粗さは、他の箇所の表面粗さよりも小さいことを特徴とする半導体装置。
(付記3) 付記2記載の半導体装置であって、
前記他の箇所では前記熱伝導材料が流れないことを特徴とする半導体装置。
(付記4) 付記2又は3記載の半導体装置であって、
前記熱伝導材料が接する前記放熱板の前記面において、前記熱伝導材料が接する箇所は、前記配線基板に搭載された前記半導体素子の前記背面に面し、
当該箇所の大きさは前記半導体素子の前記背面の大きさと略同一以上であり、
当該箇所の外側に前記他の箇所が設けられていることを特徴とする半導体装置。
(付記5) 付記4記載の半導体装置であって、
前記熱伝導材料が接する前記放熱板の前記面において、前記熱伝導材料が接する箇所の最外部は、前記配線基板上において前記半導体素子の周囲に設けられた受動素子の搭載位置よりも内側に位置していることを特徴とする半導体装置。
(付記6) 付記1乃至5いずれか一項記載の半導体装置であって、
前記熱伝導材料は半田合金であることを特徴とする半導体装置。
(付記7) 付記2乃至6いずれか一項記載の半導体装置であって、
前記熱伝導材料が接する前記放熱板の前記面において、前記熱伝導材料が接する箇所を構成する材料は、前記他の箇所を構成する材料と異なることを特徴とする半導体装置。
(付記8) 付記7記載の半導体装置であって、
前記他の箇所は、前記熱伝導材料が接する箇所を構成する材料を含む材料の粉末焼成により形成されていることを特徴とする半導体装置。
(付記9) 付記8記載の半導体装置であって、
前記熱伝導材料が接する箇所は、アルミニウムを含む材料から構成され
前記他の箇所は、アルミニウム・シリコン・カーバイドの粉末焼成により形成されていることを特徴とする半導体装置。
(付記10) 付記2乃至6いずれか一項記載の半導体装置であって、
前記放熱板は金属から構成され、
前記熱伝導材料が接する前記放熱板の前記面の一部にブラスト処理が施され、
前記熱伝導材料が接する箇所の表面粗さは、前記他の箇所の表面粗さよりも小さく設定されていることを特徴とする半導体装置。
(付記11) 付記10記載の半導体装置であって、
前記放熱板を構成する前記金属は、アルミニウム又は銅であることを特徴とする半導体装置。
(付記12) 付記2乃至11いずれか一項記載の半導体装置であって、
前記熱伝導材料が接する前記放熱板の前記面において、前記熱伝導材料が接する箇所の前記表面粗さと前記他の箇所の前記表面粗さとの差は約0.5μm以上であることを特徴とする半導体装置。
(付記13) 付記2乃至12いずれか一項記載の半導体装置であって、
少なくとも前記熱伝導材料が接する前記放熱板の前記面に金属メッキが施されていることを特徴とする半導体装置。
(付記14) 付記13記載の半導体装置であって、
少なくとも前記熱伝導材料が接する前記放熱板の前記面に施されている前記金属メッキは、ニッケル金メッキ又はニッケルメッキであることを特徴とする半導体装置。
(付記15) 付記2乃至14いずれか一項記載の半導体装置であって、
前記熱伝導材料が設けられる前記半導体素子の前記背面に金属メッキが施されていることを特徴とする半導体装置。
(付記16) 付記15記載の半導体装置であって、
前記熱伝導材料が設けられる前記半導体素子の前記背面に施されている前記金属メッキは、金メッキであることを特徴とする半導体装置。
(付記17) 付記2乃至16いずれか一項記載の半導体装置であって、
前記熱伝導材料が接する前記放熱板の前記面の前記熱伝導材料が接する箇所に、当該箇所から外方に広がった張出し部が形成されていることを特徴とする半導体装置。
2 プリント基板
5 背面
6 半導体合金
8 受動素子
10、30 半導体装置
20、40 ヒートスプレッダ
22 空間部形成面
23 半田接合部
24 ニッケル金メッキ
27−1、27−2、27−3、27−4 張出し部
Claims (6)
- 基板と、
前記基板の一方の主面に搭載された半導体素子と、
前記半導体素子近傍周辺に搭載された複数の受動素子と、
前記半導体素子の背面に熱伝導材料を介して接続され、前記基板上に搭載された放熱板と、を有する半導体装置であって、
前記放熱板の前記熱伝導材料と接する面において、前記熱伝導材料が接する箇所の表面粗さは、前記熱伝導材料が接しない箇所の表面粗さよりも小さく、
前記熱伝導材料が接しない箇所の表面は、アルミニウムシリコンカーバイド粉末の焼成体であり、前記熱伝導材料が接する箇所の表面は、アルミニウムシリコンカーバイド粉末の焼成体上にアルミ箔を配設したものであることを特徴とする半導体装置。 - 請求項1記載の半導体装置であって、
前記熱伝導材料が接する前記放熱板の前記面において、前記熱伝導材料が接する箇所は、前記基板に搭載された前記半導体素子の前記背面に面し、
当該熱伝導材料が接する箇所の大きさは前記半導体素子の前記背面の大きさと略同一以上であり、
当該熱伝導材料が接する箇所の外側に前記熱伝導材料が接しない箇所が設けられていることを特徴とする半導体装置。 - 請求項2記載の半導体装置であって、
前記熱伝導材料が接する前記放熱板の前記面において、前記熱伝導材料が接する箇所の最外部は、前記基板上において前記半導体素子の周囲に設けられた受動素子の搭載位置よりも内側に位置していることを特徴とする半導体装置。 - 請求項1乃至3いずれか一項記載の半導体装置であって、
前記熱伝導材料は半田合金であることを特徴とする半導体装置。 - 請求項1乃至4いずれか一項記載の半導体装置であって、
前記熱伝導材料が接する前記放熱板の前記面において、前記熱伝導材料が接する箇所の前記表面粗さと前記熱伝導材料が接しない箇所の前記表面粗さとの差は約0.5μm以上であることを特徴とする半導体装置。 - 請求項1乃至5いずれか一項記載の半導体装置であって、
少なくとも前記熱伝導材料が接する前記放熱板の前記面に金属メッキが施されていることを特徴とする半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005367211A JP4764159B2 (ja) | 2005-12-20 | 2005-12-20 | 半導体装置 |
US11/359,996 US7813133B2 (en) | 2005-12-20 | 2006-02-23 | Semiconductor device |
TW095106344A TWI320596B (en) | 2005-12-20 | 2006-02-24 | Semiconductor device |
KR1020060023270A KR100824518B1 (ko) | 2005-12-20 | 2006-03-13 | 반도체 장치 |
CNB2006100718031A CN100470794C (zh) | 2005-12-20 | 2006-03-16 | 半导体器件 |
Applications Claiming Priority (1)
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JP2005367211A JP4764159B2 (ja) | 2005-12-20 | 2005-12-20 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2007173416A JP2007173416A (ja) | 2007-07-05 |
JP4764159B2 true JP4764159B2 (ja) | 2011-08-31 |
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JP2005367211A Expired - Fee Related JP4764159B2 (ja) | 2005-12-20 | 2005-12-20 | 半導体装置 |
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US (1) | US7813133B2 (ja) |
JP (1) | JP4764159B2 (ja) |
KR (1) | KR100824518B1 (ja) |
CN (1) | CN100470794C (ja) |
TW (1) | TWI320596B (ja) |
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US7915081B2 (en) * | 2006-03-31 | 2011-03-29 | Intel Corporation | Flexible interconnect pattern on semiconductor package |
TW200830488A (en) * | 2007-01-10 | 2008-07-16 | Siliconware Precision Industries Co Ltd | Heat-dissipating semiconductor package |
US8362607B2 (en) * | 2009-06-03 | 2013-01-29 | Honeywell International Inc. | Integrated circuit package including a thermally and electrically conductive package lid |
JP5447175B2 (ja) | 2010-05-17 | 2014-03-19 | 富士通セミコンダクター株式会社 | 半導体装置 |
US8617926B2 (en) * | 2010-09-09 | 2013-12-31 | Advanced Micro Devices, Inc. | Semiconductor chip device with polymeric filler trench |
JP5573645B2 (ja) * | 2010-12-15 | 2014-08-20 | 富士通セミコンダクター株式会社 | 半導体装置及び半導体装置の製造方法 |
DE102011004171A1 (de) * | 2011-02-15 | 2012-08-16 | Brose Fahrzeugteile GmbH & Co. Kommanditgesellschaft, Würzburg | Temperierelement und Verfahren zur Befestigung eines Elektrobauteils an dem Temperierelement |
JP2013115083A (ja) * | 2011-11-25 | 2013-06-10 | Fujitsu Semiconductor Ltd | 半導体装置及びその製造方法 |
JP6036083B2 (ja) * | 2012-09-21 | 2016-11-30 | 株式会社ソシオネクスト | 半導体装置及びその製造方法並びに電子装置及びその製造方法 |
US9196537B2 (en) | 2012-10-23 | 2015-11-24 | Nxp B.V. | Protection of a wafer-level chip scale package (WLCSP) |
JP5708613B2 (ja) * | 2012-11-01 | 2015-04-30 | 株式会社豊田自動織機 | モジュール |
KR20140115668A (ko) | 2013-03-21 | 2014-10-01 | 삼성전자주식회사 | 방열판과 수동 소자를 갖는 반도체 패키지 |
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US9560737B2 (en) * | 2015-03-04 | 2017-01-31 | International Business Machines Corporation | Electronic package with heat transfer element(s) |
US10175064B2 (en) | 2015-09-25 | 2019-01-08 | International Business Machines Corporation | Circuit boards and electronic packages with embedded tamper-respondent sensor |
US9911012B2 (en) | 2015-09-25 | 2018-03-06 | International Business Machines Corporation | Overlapping, discrete tamper-respondent sensors |
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CN1988149A (zh) | 2007-06-27 |
JP2007173416A (ja) | 2007-07-05 |
TWI320596B (en) | 2010-02-11 |
KR20070065763A (ko) | 2007-06-25 |
US7813133B2 (en) | 2010-10-12 |
US20070139892A1 (en) | 2007-06-21 |
CN100470794C (zh) | 2009-03-18 |
KR100824518B1 (ko) | 2008-04-22 |
TW200725870A (en) | 2007-07-01 |
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