JP5447175B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5447175B2 JP5447175B2 JP2010113498A JP2010113498A JP5447175B2 JP 5447175 B2 JP5447175 B2 JP 5447175B2 JP 2010113498 A JP2010113498 A JP 2010113498A JP 2010113498 A JP2010113498 A JP 2010113498A JP 5447175 B2 JP5447175 B2 JP 5447175B2
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- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Condensed Matter Physics & Semiconductors (AREA)
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Description
図13〜図19は、本実施形態に係る半導体装置の製造途中の断面図である。
第1実施形態では、図20を参照して説明したように、面積の異なるハンダペレットをそれらの自重で積み重ねて接続部材16を作製した。
図24(a)は、第1例に係る接続部材16の作製方法について説明するための上面図であり、図24(b)は図24(a)のX2−X2線に沿う断面図である。
図27(a)は、第2例に係る接続部材16の作製方法について説明するための上面図であり、図27(b)は図27(a)のX4−X4線に沿う断面図である。なお、これらの図において第1例で説明したのと同じ要素には第1例と同じ符号を付し、以下ではその説明を省略する。
第2実施形態では、三層のハンダシートからなるクラッド材を利用して接続部材16を製造した。
Claims (10)
- 基板と、
前記基板上に配設された半導体素子と、
前記基板上に配設され、前記半導体素子を覆う放熱部材と、
前記半導体素子の上面と前記放熱部材の下面とを接続する接続部材とを有し、
前記接続部材は、
前記半導体素子の前記上面に接し、第1の融点を有する第1の部材と、
前記第1の部材に接し、前記第1の部材よりも広い面積を有し、前記第1の融点よりも高い第2の融点を有する第2の部材と、
前記第2の部材と前記放熱部材とに挟まれ、前記第2の部材よりも狭い面積を有し、前記第2の融点よりも低い第3の融点を有する第3の部材と、
を含むことを特徴とする半導体装置。 - 前記第1の部材及び前記第3の部材は低融点ハンダからなり、
前記第2の部材は高融点ハンダからなることを特徴とする請求項1に記載の半導体装置。 - 前記第1の部材及び前記第3の部材はSn-37Pbハンダからなり、
前記第2の部材はSn-95Pbハンダからなることを特徴とする請求項1又は請求項2に記載の半導体装置。 - 前記半導体素子の前記上面にはAuメタライズ層が形成され、前記放熱部材の前記接続部材と接する面にはAuメッキが施されていることを特徴とする請求項1〜3のいずれか1項に記載の半導体装置。
- 前記第1の部材、前記第2の部材、及び前記第3の各々の平面形状は矩形であることを特徴とする請求項1〜4のいずれか1項に記載の半導体装置。
- 前記矩形の少なくとも一辺において、前記第3の部材の側面が前記第2の部材の側面から後退しており、
前記第3の部材の後退した前記側面の横であって、前記基板の上に、電子部品が配設されたことを特徴とする請求項5に記載の半導体装置。 - 前記矩形の四辺のうち対向する二辺のみにおいて、前記第3の部材の前記側面が前記第2の部材の前記側面から後退していることを特徴とする請求項6に記載の半導体装置。
- 前記矩形の一辺のみにおいて、前記第3の部材の前記側面が前記第2の部材の前記側面から後退していることを特徴とする請求項6に記載の半導体装置。
- 前記第2の部材の前記側面は、前記電子部品の上方に位置することを特徴とする請求項6に記載の半導体装置。
- 前記第2の部材は、前記電子部品を覆うことを特徴とする請求項6に記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010113498A JP5447175B2 (ja) | 2010-05-17 | 2010-05-17 | 半導体装置 |
US13/034,092 US8299607B2 (en) | 2010-05-17 | 2011-02-24 | Semiconductor device |
US13/628,329 US8933560B2 (en) | 2010-05-17 | 2012-09-27 | Semiconductor device |
US14/185,030 US9472482B2 (en) | 2010-05-17 | 2014-02-20 | Semiconductor device |
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JP2010113498A JP5447175B2 (ja) | 2010-05-17 | 2010-05-17 | 半導体装置 |
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JP2013272601A Division JP5796627B2 (ja) | 2013-12-27 | 2013-12-27 | 半導体装置とその製造方法 |
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JP2011243702A JP2011243702A (ja) | 2011-12-01 |
JP5447175B2 true JP5447175B2 (ja) | 2014-03-19 |
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Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5573645B2 (ja) * | 2010-12-15 | 2014-08-20 | 富士通セミコンダクター株式会社 | 半導体装置及び半導体装置の製造方法 |
JP5983032B2 (ja) * | 2012-05-28 | 2016-08-31 | 富士通株式会社 | 半導体パッケージ及び配線基板ユニット |
JP6036083B2 (ja) * | 2012-09-21 | 2016-11-30 | 株式会社ソシオネクスト | 半導体装置及びその製造方法並びに電子装置及びその製造方法 |
JP6314731B2 (ja) * | 2014-08-01 | 2018-04-25 | 株式会社ソシオネクスト | 半導体装置及び半導体装置の製造方法 |
US9947634B1 (en) * | 2017-06-13 | 2018-04-17 | Northrop Grumman Systems Corporation | Robust mezzanine BGA connector |
US11791237B2 (en) | 2018-06-27 | 2023-10-17 | Intel Corporation | Microelectronic assemblies including a thermal interface material |
US11107747B2 (en) * | 2018-09-19 | 2021-08-31 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package with composite thermal interface material structure and method of forming the same |
US11594463B2 (en) * | 2018-10-11 | 2023-02-28 | Intel Corporation | Substrate thermal layer for heat spreader connection |
US11682605B2 (en) * | 2019-05-28 | 2023-06-20 | Intel Corporation | Integrated circuit packages with asymmetric adhesion material regions |
US11705381B2 (en) | 2021-06-04 | 2023-07-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | High efficiency heat dissipation using thermal interface material film |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4034469A (en) * | 1976-09-03 | 1977-07-12 | Ibm Corporation | Method of making conduction-cooled circuit package |
JP2984068B2 (ja) | 1991-01-31 | 1999-11-29 | 株式会社日立製作所 | 半導体装置の製造方法 |
US5323294A (en) | 1993-03-31 | 1994-06-21 | Unisys Corporation | Liquid metal heat conducting member and integrated circuit package incorporating same |
US6387732B1 (en) * | 1999-06-18 | 2002-05-14 | Micron Technology, Inc. | Methods of attaching a semiconductor chip to a leadframe with a footprint of about the same size as the chip and packages formed thereby |
JP2001230351A (ja) | 2000-02-14 | 2001-08-24 | Shibafu Engineering Corp | 電子モジュール用接合材料、モジュール型半導体装置及びその製造方法 |
WO2006016479A1 (ja) * | 2004-08-10 | 2006-02-16 | Neomax Materials Co., Ltd. | ヒートシンク部材およびその製造方法 |
US7239517B2 (en) * | 2005-04-11 | 2007-07-03 | Intel Corporation | Integrated heat spreader and method for using |
JP2007005670A (ja) | 2005-06-27 | 2007-01-11 | Fujitsu Ltd | 電子部品パッケージおよび接合組立体 |
JP4764159B2 (ja) | 2005-12-20 | 2011-08-31 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP4691455B2 (ja) | 2006-02-28 | 2011-06-01 | 富士通株式会社 | 半導体装置 |
JP2007258448A (ja) | 2006-03-23 | 2007-10-04 | Fujitsu Ltd | 半導体装置 |
US8063482B2 (en) * | 2006-06-30 | 2011-11-22 | Intel Corporation | Heat spreader as mechanical reinforcement for ultra-thin die |
JP4920401B2 (ja) * | 2006-12-27 | 2012-04-18 | 昭和電工株式会社 | 導電性回路基板の製造方法 |
DE102008048005B3 (de) * | 2008-09-19 | 2010-04-08 | Infineon Technologies Ag | Leistungshalbleitermodulanordnung und Verfahren zur Herstellung einer Leistungshalbleitermodulanordnung |
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2010
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2011
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US8299607B2 (en) | 2012-10-30 |
JP2011243702A (ja) | 2011-12-01 |
US20110278715A1 (en) | 2011-11-17 |
US20130020696A1 (en) | 2013-01-24 |
US9472482B2 (en) | 2016-10-18 |
US20140167246A1 (en) | 2014-06-19 |
US8933560B2 (en) | 2015-01-13 |
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