JP6036083B2 - 半導体装置及びその製造方法並びに電子装置及びその製造方法 - Google Patents
半導体装置及びその製造方法並びに電子装置及びその製造方法 Download PDFInfo
- Publication number
- JP6036083B2 JP6036083B2 JP2012208747A JP2012208747A JP6036083B2 JP 6036083 B2 JP6036083 B2 JP 6036083B2 JP 2012208747 A JP2012208747 A JP 2012208747A JP 2012208747 A JP2012208747 A JP 2012208747A JP 6036083 B2 JP6036083 B2 JP 6036083B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- adhesive
- plate
- semiconductor device
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 154
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 238000000034 method Methods 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims description 226
- 239000000853 adhesive Substances 0.000 claims description 193
- 230000001070 adhesive effect Effects 0.000 claims description 177
- 229910000679 solder Inorganic materials 0.000 description 32
- 239000003795 chemical substances by application Substances 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 238000002844 melting Methods 0.000 description 10
- 230000008018 melting Effects 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- YPHMISFOHDHNIV-FSZOTQKASA-N cycloheximide Chemical compound C1[C@@H](C)C[C@H](C)C(=O)[C@@H]1[C@H](O)CC1CC(=O)NC(=O)C1 YPHMISFOHDHNIV-FSZOTQKASA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920001296 polysiloxane Polymers 0.000 description 2
- 239000012779 reinforcing material Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910020816 Sn Pb Inorganic materials 0.000 description 1
- 229910020830 Sn-Bi Inorganic materials 0.000 description 1
- 229910020922 Sn-Pb Inorganic materials 0.000 description 1
- 229910018728 Sn—Bi Inorganic materials 0.000 description 1
- 229910008783 Sn—Pb Inorganic materials 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011346 highly viscous material Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Wire Bonding (AREA)
Description
(付記1)基板と、前記基板上に搭載された半導体素子と、前記半導体素子上に固定され、前記基板と異なる熱膨張係数を有する板状部材と、前記基板と前記板状部材との間に設けられて前記基板と前記板状部材とを接合させていて、所定の条件によって前記基板又は前記板状部材から剥離する第1接着剤と、を備えることを特徴とする半導体装置。
(付記2)前記所定の条件は、前記第1接着剤が前記基板又は前記板状部材から剥離する温度となることを特徴とする付記1記載の半導体装置。
(付記3)前記基板の下面に、前記剥離する温度よりも低い融点を持つ半田ボールを備えることを特徴とする付記2記載の半導体装置。
(付記4)前記第1接着剤は、前記所定の条件として電流が流れることによって剥離することを特徴とする付記1記載の半導体装置。
(付記5)前記第1接着剤は、前記基板への接着面積と前記板状部材への接着面積とが異なることを特徴とする付記1から4のいずれか一項記載の半導体装置。
(付記6)前記第1接着剤は、前記基板及び前記板状部材のいずれか一方に形成された凹凸面と、前記基板及び前記板状部材の他方に形成された平坦面と、に接着していることを特徴とする付記5記載の半導体装置。
(付記7)前記板状部材の前記第1接着剤と接着する部分は、凹凸面を有することを特徴とする付記5または6記載の半導体装置。
(付記8)前記第1接着剤は、前記基板及び前記板状部材のいずれか一方から他方に向かって横幅が狭まる形状をしていることを特徴とする付記5記載の半導体装置。
(付記9)前記基板と前記板状部材との間に設けられて前記基板と前記板状部材とを接合させていて、前記所定の条件でも前記基板と前記板状部材とを接合させ続ける第2接着剤を備えることを特徴とする付記1から8のいずれか一項記載の半導体装置。
(付記10)前記第2接着剤は、前記第1接着剤よりも前記基板及び前記板状部材への接着面積が小さいことを特徴とする付記9記載の半導体装置。
(付記11)前記第2接着剤は、前記第1接着剤よりも前記基板の中心側に設けられていることを特徴とする付記9又は10記載の半導体装置。
(付記12)前記第1接着剤は、前記半導体装置が実装基板に実装された後、前記基板及び前記板状部材のいずれか一方から剥離し、他方とは接着したままであることを特徴とする付記1から11のいずれか一項記載の半導体装置。
(付記13)付記1から12のいずれか一項記載の半導体装置と、前記半導体装置が実装された実装基板と、を備え、前記第1接着剤は、前記基板及び前記板状部材のいずれか一方とは剥離し、他方とは接着していることを特徴とする電子装置。
(付記14)基板上に半導体素子を搭載する工程と、前記基板上に、所定の条件によって剥離する接着剤を形成する工程と、前記接着剤の接着性が維持される条件で、前記半導体素子上に固定されると共に、前記接着剤によって前記基板に接合される、前記基板と異なる熱膨張係数を有する板状部材を形成する工程と、を備えることを特徴とする半導体装置の製造方法。
(付記15)付記14に記載の製造方法によって製造された半導体装置を実装基板に実装する工程と、前記半導体装置を前記実装基板に実装した後、前記接着剤に前記所定の条件を与えて、前記基板及び前記板状部材のいずれか一方から前記接着剤を剥離する工程と、を備えることを特徴とする電子装置の製造方法。
12 半導体素子
14 素子側電極パッド
16 バンプ
18 基板側電極パッド
20 配線
22 アンダーフィル剤
24 熱伝導性接着剤
26 板状部材
28、28a、28b、50 第1接着剤
30 凹凸面
32 平坦面
34 開口
36 ボールパッド
38 半田ボール
40 実装基板
42 剥離箇所
60 第2接着剤
100、150、300 半導体装置
200 電子装置
Claims (8)
- 基板と、
前記基板上に搭載された半導体素子と、
前記半導体素子上に固定され、前記基板と異なる熱膨張係数を有する板状部材と、
前記基板と前記板状部材との間に設けられ、前記基板に接着しつつ前記板状部材からは離れているか、又は前記板状部材に接着しつつ前記基板からは離れた第1接着剤と、
を備えることを特徴とする半導体装置。 - 前記基板の下面に、半田ボールを備えることを特徴とする請求項1記載の半導体装置。
- 前記基板の前記第1接着剤の下面に対向する部分の表面積と、前記板状部材の前記第1接着剤の上面に対向する部分の表面積とが異なることを特徴とする請求項1又は2記載の半導体装置。
- 前記板状部材の前記部分は、凹凸面を有することを特徴とする請求項3記載の半導体装置。
- 前記基板と前記板状部材との間に設けられ、前記基板と前記板状部材とを接着する第2接着剤を備えることを特徴とする請求項1から4のいずれか一項記載の半導体装置。
- 請求項1から5のいずれか一項記載の半導体装置と、
前記半導体装置が実装された実装基板と、
を有することを特徴とする電子装置。 - 基板上に半導体素子を搭載する工程と、
前記基板上に、所定の条件によって剥離する接着剤を形成する工程と、
前記接着剤の接着性が維持される条件で、前記半導体素子上に固定されると共に、前記接着剤によって前記基板に接着される、前記基板と異なる熱膨張係数を有する板状部材を形成する工程と、
を備えることを特徴とする半導体装置の製造方法。 - 請求項7に記載の製造方法によって製造された半導体装置を実装基板に実装する工程と、
前記半導体装置を前記実装基板に実装した後、前記接着剤に前記所定の条件を与えて、前記基板及び前記板状部材のいずれか一方から前記接着剤を剥離する工程と、を備えることを特徴とする電子装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012208747A JP6036083B2 (ja) | 2012-09-21 | 2012-09-21 | 半導体装置及びその製造方法並びに電子装置及びその製造方法 |
US13/972,480 US9385092B2 (en) | 2012-09-21 | 2013-08-21 | Semiconductor device, electronic device and method for fabricating the semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012208747A JP6036083B2 (ja) | 2012-09-21 | 2012-09-21 | 半導体装置及びその製造方法並びに電子装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014063921A JP2014063921A (ja) | 2014-04-10 |
JP6036083B2 true JP6036083B2 (ja) | 2016-11-30 |
Family
ID=50338060
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012208747A Active JP6036083B2 (ja) | 2012-09-21 | 2012-09-21 | 半導体装置及びその製造方法並びに電子装置及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US9385092B2 (ja) |
JP (1) | JP6036083B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20170287838A1 (en) * | 2016-04-02 | 2017-10-05 | Intel Corporation | Electrical interconnect bridge |
KR102269743B1 (ko) * | 2019-03-05 | 2021-06-25 | 매그나칩 반도체 유한회사 | 이너 리드 패턴 그룹을 포함하는 반도체 패키지 및 그 방법 |
US20230187379A1 (en) * | 2021-12-10 | 2023-06-15 | Ati Technologies Ulc | Electronic device including a substrate, a structure, and an adhesive and a process of forming the same |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2984068B2 (ja) * | 1991-01-31 | 1999-11-29 | 株式会社日立製作所 | 半導体装置の製造方法 |
US6344234B1 (en) * | 1995-06-07 | 2002-02-05 | International Business Machines Corportion | Method for forming reflowed solder ball with low melting point metal cap |
US6204454B1 (en) * | 1997-12-27 | 2001-03-20 | Tdk Corporation | Wiring board and process for the production thereof |
JP2000114413A (ja) * | 1998-09-29 | 2000-04-21 | Sony Corp | 半導体装置、その製造方法および部品の実装方法 |
JP2000349178A (ja) * | 1999-06-08 | 2000-12-15 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
AU2001292338A1 (en) * | 2000-10-02 | 2002-04-15 | Asahi Kasei Kabushiki Kaisha | Functional alloy particles |
KR100394809B1 (ko) * | 2001-08-09 | 2003-08-14 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
EP1915041A1 (en) * | 2001-09-28 | 2008-04-23 | Ibiden Co., Ltd. | Printed wiring board and printed wiring board manufacturing method |
KR100446290B1 (ko) * | 2001-11-03 | 2004-09-01 | 삼성전자주식회사 | 댐을 포함하는 반도체 패키지 및 그 제조방법 |
US6665187B1 (en) * | 2002-07-16 | 2003-12-16 | International Business Machines Corporation | Thermally enhanced lid for multichip modules |
WO2004068581A1 (ja) * | 2003-01-30 | 2004-08-12 | Fujitsu Limited | 半導体装置及び支持板 |
JP4390541B2 (ja) | 2003-02-03 | 2009-12-24 | Necエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US6906413B2 (en) * | 2003-05-30 | 2005-06-14 | Honeywell International Inc. | Integrated heat spreader lid |
JP2005011838A (ja) * | 2003-06-16 | 2005-01-13 | Toshiba Corp | 半導体装置及びその組立方法 |
WO2005024940A1 (ja) | 2003-08-28 | 2005-03-17 | Fujitsu Limited | パッケージ構造、それを搭載したプリント基板、並びに、かかるプリント基板を有する電子機器 |
JP2005332970A (ja) | 2004-05-20 | 2005-12-02 | Hitachi Ltd | 半導体装置の実装構造体および実装方法 |
JP4247193B2 (ja) | 2005-03-18 | 2009-04-02 | 株式会社東芝 | 電子部品のアンダーフィル剤保持装置、半導体パッケージの実装装置及び実装方法 |
JP2007005670A (ja) * | 2005-06-27 | 2007-01-11 | Fujitsu Ltd | 電子部品パッケージおよび接合組立体 |
JP4779619B2 (ja) | 2005-12-12 | 2011-09-28 | 凸版印刷株式会社 | 支持板、多層回路配線基板及びそれを用いた半導体パッケージ |
JP4764159B2 (ja) * | 2005-12-20 | 2011-08-31 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP4691455B2 (ja) * | 2006-02-28 | 2011-06-01 | 富士通株式会社 | 半導体装置 |
US7915081B2 (en) * | 2006-03-31 | 2011-03-29 | Intel Corporation | Flexible interconnect pattern on semiconductor package |
JP2007335423A (ja) * | 2006-06-12 | 2007-12-27 | Matsushita Electric Ind Co Ltd | 半導体装置 |
US20080164300A1 (en) * | 2007-01-08 | 2008-07-10 | Endicott Interconnect Technologies, Inc. | Method of making circuitized substrate with solder balls having roughened surfaces, method of making electrical assembly including said circuitized substrate, and method of making multiple circuitized substrate assembly |
KR100999918B1 (ko) * | 2008-09-08 | 2010-12-13 | 삼성전기주식회사 | 인쇄회로기판 및 그 제조 방법 |
WO2010047006A1 (ja) * | 2008-10-23 | 2010-04-29 | パナソニック株式会社 | 半導体装置およびその製造方法 |
JP5133204B2 (ja) * | 2008-11-06 | 2013-01-30 | 株式会社ジャパンディスプレイイースト | タッチパネル |
CN102379037B (zh) * | 2009-03-30 | 2015-08-19 | 高通股份有限公司 | 使用顶部后钝化技术和底部结构技术的集成电路芯片 |
US8362607B2 (en) * | 2009-06-03 | 2013-01-29 | Honeywell International Inc. | Integrated circuit package including a thermally and electrically conductive package lid |
JP5263895B2 (ja) * | 2010-01-12 | 2013-08-14 | ルネサスエレクトロニクス株式会社 | 半導体装置、及び半導体装置の製造方法 |
JP5447175B2 (ja) * | 2010-05-17 | 2014-03-19 | 富士通セミコンダクター株式会社 | 半導体装置 |
JP5573645B2 (ja) * | 2010-12-15 | 2014-08-20 | 富士通セミコンダクター株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2013012720A (ja) * | 2011-05-28 | 2013-01-17 | Kyocera Corp | 電子装置 |
JP2012054597A (ja) * | 2011-11-07 | 2012-03-15 | Renesas Electronics Corp | 半導体装置 |
-
2012
- 2012-09-21 JP JP2012208747A patent/JP6036083B2/ja active Active
-
2013
- 2013-08-21 US US13/972,480 patent/US9385092B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US9385092B2 (en) | 2016-07-05 |
US20140084439A1 (en) | 2014-03-27 |
JP2014063921A (ja) | 2014-04-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI529878B (zh) | 集成電路封裝件及其裝配方法 | |
JP5066529B2 (ja) | 半導体素子の実装構造体及び半導体素子の実装方法 | |
JP5325736B2 (ja) | 半導体装置及びその製造方法 | |
JP5387685B2 (ja) | 半導体装置の製造方法 | |
JP5250524B2 (ja) | 半導体装置及びその製造方法 | |
US20030127747A1 (en) | Semiconductor device and manufacturing method thereof | |
JP4899406B2 (ja) | フリップチップ型半導体装置 | |
JP2001313314A (ja) | バンプを用いた半導体装置、その製造方法、および、バンプの形成方法 | |
JP5186741B2 (ja) | 回路基板及び半導体装置 | |
JPWO2008136419A1 (ja) | 半導体装置及び製造方法並びにリペア方法 | |
JP2012009655A (ja) | 半導体パッケージおよび半導体パッケージの製造方法 | |
JP6036083B2 (ja) | 半導体装置及びその製造方法並びに電子装置及びその製造方法 | |
JP3813540B2 (ja) | 半導体装置の製造方法及び半導体装置及び半導体装置ユニット | |
JP5919641B2 (ja) | 半導体装置およびその製造方法並びに電子装置 | |
US20070196952A1 (en) | Manufacturing method of semiconductor device | |
KR20090122514A (ko) | 플립 칩 패키지 및 그 제조방법 | |
US20070114672A1 (en) | Semiconductor device and method of manufacturing the same | |
JP2009076839A (ja) | 半導体装置およびその製造方法 | |
JP3419398B2 (ja) | 半導体装置の製造方法 | |
JP2013012570A (ja) | 半導体装置および半導体装置の製造方法 | |
JP7473156B2 (ja) | 半導体パッケージ | |
JP2003037210A (ja) | 半導体装置およびその製造方法 | |
KR20100020771A (ko) | 반도체 패키지의 제조 방법 | |
JP5576528B2 (ja) | 半導体装置 | |
JP4863861B2 (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20150526 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20150611 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20160509 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20160511 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20160523 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160531 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160606 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160705 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160801 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20161004 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20161017 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6036083 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |