JP5186741B2 - 回路基板及び半導体装置 - Google Patents
回路基板及び半導体装置 Download PDFInfo
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- JP5186741B2 JP5186741B2 JP2006222825A JP2006222825A JP5186741B2 JP 5186741 B2 JP5186741 B2 JP 5186741B2 JP 2006222825 A JP2006222825 A JP 2006222825A JP 2006222825 A JP2006222825 A JP 2006222825A JP 5186741 B2 JP5186741 B2 JP 5186741B2
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- circuit board
- semiconductor element
- conductive layer
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Description
これにより、半導体装置の内部で発生する配線層などの剥離、或いは半導体素子の外部接続電極と配線基板に於ける電極接続部との間の接続不良などが防止され、信頼性の高い回路基板並びに当該回路基板を用いた半導体装置の実現が可能となる。
(第1の実施の形態)
本発明の第1の実施の形態に於ける、回路基板と当該回路基板上に半導体素子が実装された形態について説明する。
尚、図1(B)は、図1(A)に於ける線A−Aに於ける断面を示す。
また、当該素子搭載領域S内に於いては、その領域Sの外周近傍に於ける前記配線層11に、幅広の電極接続部12が設けられている。当該幅広の電極接続部12へは、半導体素子の電極が接続される。
当該絶縁性樹脂層15は、前記ソルダーレジスト層16を構成する材料と同一の材料を適用することができる。即ち、これらの樹脂層は、現像型レジスト材、熱硬化型レジスト材、或いは紫外線硬化型レジスト材を用いて形成することができ、具体的には、エポキシ系、アクリル系、またはポリイミド系等の樹脂、またはこれらの樹脂の混合物から構成することができる。勿論、絶縁性樹脂層15とソルダーレジスト層16を、異なる材料から構成してもよい。
当該半導体素子が実装された状態の半導体装置200にあっては、半導体素子21が、回路基板100と当該半導体素子21との間に充填された接着部材(接着剤)31によって当該回路基板100上に固着されている。当該接着部材31は、アンダーフィル材とも称される。
このような構成を有する半導体装置200にあっては、前述の如く、回路基板100の素子搭載領域S内に、配線層11及び島状の導電層14が選択的に配設されている。
従って、素子搭載領域S内に於ける絶縁性樹脂層15の占有面積は実質的に少であり、半導体素子21を回路基板100に実装する際に生ずるところの当該絶縁性樹脂層15の弾性回復力は小である。
図2は、回路基板100上方に半導体素子21を位置せしめた状態を示している。
かかる半導体素子21の実装に先んじて、回路基板100の素子搭載領域S内に、ペースト状またはシート状の接着部材31を供給・配置する。供給方法としては、ディスペンス法、印刷法或いは貼付け法を用いることができる。
そして、当該回路基板100の両主面に配設された配線層、電極パッド等は、当該回路基板100の内部に形成された配線層、層間接続部を介して選択的に接続されている。
一方、電極パッド22に外部接続用電極23が配設された半導体素子21は、予め加熱されたボンディングツール70に吸着・保持される。当該加熱温度は、約150乃至250℃に設定される。
そして、更に当該半導体素子21をボンディングツール70により押圧し、回路基板100の電極接続部12に接触させた半導体素子21の外部接続用電極23に荷重を与える。荷重は、例えば5〜50gf/bumpとされる。
次いで、ボンディングツールの吸引を解除し、ボンディングツール70から半導体素子21を開放して後、当該ボンディングツール70を上昇させる(図示せず)。
この工程では、加熱温度を、例えば120乃至180℃に設定し、また加熱時間を、例えば約30乃至90分に設定する。
しかる後、前記回路基板100の裏面に配設されている前記電極パッド17上に、外部接続端子18を構成する半田ボールをリフロー法により形成し、BGA(Ball Grid Array)パッケージ構造を有する半導体装置200を形成する。
尚、前記半田ボールの配設を省略し、電極パッド17を外部接続端子としたLGA(Land Grid Array)パッケージ構造としてもよく、また外部接続端子の形状を、リード型、ピン型など他の形状としてもよい。
(第2の実施の形態)
本発明の第2の実施の形態に於ける、回路基板と当該回路基板上に半導体素子が実装された形態について説明する。
尚、図6(B)は、図6(A)に於ける線A−Aに於ける断面を示す。
かかる島状の導電層14の選択的な配設により、配線層11の配置密度の粗密度が改善され、且つ回路基板100の剛性が向上して当該回路基板の反り或いはうねりが低減する。
即ち、当該島状の導電層14と接着部材31は、絶縁性樹脂層15を介して強固に接続され、当該島状の導電層14と接着部材31との間に剥離を生じない。
次に、本発明の第3の実施の形態について説明する。
(第3の実施の形態)
本発明の第3の実施の形態に於ける、回路基板と当該回路基板上に半導体素子が実装された形態について説明する。
尚、図7(B)は、図7(A)に於ける線A−Aに於ける断面を示す。
かかる島状の導電層14の選択的な配設により、配線層11の配置密度の粗密度が改善され、且つ回路基板100の剛性が向上して当該回路基板の反り或いはうねりが低減する。
更に、この様な構成を有する半導体装置202にあっては、一つの島状の導電層14上に配設される絶縁性樹脂層15が複数個に分割されて配設されることにより、当該分割された樹脂層間には段差(凹凸)が存在する。
尚、絶縁性樹脂層15に複数の段差等を形成する表面拡大処理は、前記格子状に分割することに限られず、ライン・スペース形状、或いは複数個の凹部(窪み)を並設するなど、必要に応じて他の形状を適用することができる。
また、かかる構成によれば、絶縁性樹脂層15は複数個に分割されていることから、半導体素子21を回路基板102に実装をする際に、当該絶縁性樹脂層15の弾性回復力が抑えられる。
(第4の実施の形態)
本発明の第4の実施の形態に於ける、回路基板と当該回路基板上に半導体素子が実装された形態について説明する。
尚、図8(B)は、図8(A)に於ける線A−Aに於ける断面を示す。
かかる島状の導電層14の選択的な配設により、配線層11の配置密度の粗密度が改善され、且つ回路基板100の剛性が向上して当該回路基板の反り或いはうねりが低減する。
(第5の実施の形態)
本発明の第5の実施の形態に於ける、回路基板と当該回路基板上に半導体素子が実装された形態について説明する。
尚、図9(B)は、図9(A)に於ける線A−Aに於ける断面を示す。
本実施の形態5に於ける半導体装置204にあっては、回路基板103の絶縁性基材10上に選択的に配設される島状の導電層14上には、その厚さが前記実施の形態1に於ける厚さよりも薄い厚さを有する絶縁性樹脂層15が配設される。
前記絶縁性基材10の表面10aから当該絶縁性樹脂層15の表面15aまでの高さは、素子搭載領域12の外周部に配設されたソルダーレジスト16の高さよりも低くされる。
尚、本実施の形態5にあっても、当該島状の導電層14表面への絶縁性樹脂層15の配設構成以外の構成、即ち配線基板の構成並びに半導体素子の構成は、前記第1の実施の形態に於ける構成と同一の構成を有することから、詳細な説明を省略する。
かかる島状の導電層14の選択的な配設により、配線層11の配置密度の粗密度が改善され、且つ回路基板100の剛性が向上して当該回路基板の反り或いはうねりが低減する。
(従来技術との比較)
次に、本発明の効果について、従来技術と比較した事例を用いて説明する。
一方、島状の導電層14は、接地電位とした。そして、接着部材31として、ペースト状の熱硬化型の絶縁性エポキシ樹脂を適用した。
実装条件は、荷重を17gf/bumpとし、半導体素子の加熱温度を280℃、回路基板の加熱温度を70℃とした。また、ボンディング時間は5秒とした。
最初に、吸湿リフロー試験結果について説明する。
そして、調査サンプルの内部外観検査を行い、更に電気特性調査を行った。
電気特性調査については、所定の試験プログラムに基づいて、集積回路素子を電気的に動作させて、半導体装置の電気特性を測定することにより、所定の特性が得られるか否かの確認を行った。
次に、吸湿リフロー試験後の調査サンプルに高温加湿試験を施した結果についいて説明する。当該高温加湿試験は、温度121℃、相対湿度99.8%の環境で、所定の時間まで、それぞれの調査サンプルを放置することにより行った。
電気特性調査及び内部外観検査の方法は、上記吸湿リフロー試験と同様の方法で行った。
また、半導体装置Aでは672時間で10個中5個の調査サンプルに、半導体装置Bでは1008時間で10個中2個の調査サンプルに、それぞれ電気特性の不良を生じた。
剥離した箇所については、半導体装置Aでは、半導体素子21の外周部近傍で、半導体素子21と接着部材31の界面に於いて剥離が生じ、更に島状の導電層14上及び島状の導電層14近傍に於いて接着部材31との界面に於いて剥離が発生していた。
即ち、島状の導電層14上では、接着部材31の剥離は生じていなかった。
なお、本発明に於ける前記第1〜5の実施の形態は、いずれか一つの実施の形態に限るものではなく、これらの実施の形態を選択し、組み合わせて適用することもできる。
(付記1) 半導体素子が実装される回路基板であって、
前記回路基板表面の前記半導体素子に対向する領域に配設された配線層と、
前記回路基板表面の前記半導体素子に対向する領域に於いて、前記配線層と離間して配設された導電層と、
前記導電層上に配設された樹脂層と、
を含むことを特徴とする回路基板。
(付記3) 前記導電層は銅(Cu)からなり、その表面には下層からニッケル(Ni)及び金(Au)の2層の金属層が形成されていることを特徴とする付記1または2記載の回路基板。
(付記5) 前記導電層上に配設された前記樹脂層は複数個に分割されて配設されていることを特徴とする付記1乃至3のいずれか一項に記載の回路基板。
(付記8) 前記回路基板を構成する基材の表面から前記樹脂膜の表面までの高さが前記領域の外周部に配設されたソルダーレジストの高さより低いことを特徴とする付記1乃至7のいずれか一項に記載の回路基板。
前記半導体素子を実装し、前記半導体素子に対向する領域に配設された配線層、前記半導体素子に対向する領域に於いて前記配線層と離間して配設された導電層、及び前記導電層上に配設された樹脂層を有する回路基板と、
前記回路基板と前記半導体素子との間に配設された接着部材と、
を含むことを特徴とする半導体装置。
(付記11) 前記導電層は銅(Cu)からなり、その表面には下層からニッケル(Ni)及び金(Au)の2層の金属層が形成されていることを特徴とする付記9または10記載の半導体装置。
(付記13) 前記導電層上に配設された前記樹脂層は複数個に分割されて配設されていることを特徴とする付記9乃至11のいずれか一項に記載の半導体装置。
(付記16) 前記回路基板を構成する基材の表面から前記樹脂膜の表面までの高さが前記領域の外周部に配設されたソルダーレジストの高さより低いことを特徴とする付記9乃至15のいずれか一項に記載の半導体装置。
10a 表面
11、11a、11b、11c 配線層
12 電極接続部
13 層間接続用ビア部
14 島状の導電層
14a 表出部
15 絶縁性樹脂層
15a 表面
16 ソルダーレジスト
18 外部接続用端子
21 半導体素子
22 電極パッド
23 外部接続用電極
31 接着部材
32 フィレット部
S 素子搭載領域
100、101、102、103、104 回路基板
200、201、202、203、204 半導体装置
Claims (10)
- 半導体素子が実装される回路基板であって、
前記回路基板表面の前記半導体素子に対向する領域に配設された配線層と、
前記回路基板表面の前記半導体素子に対向する領域に於いて、前記配線層と離間して配設された導電層と、
前記導電層上に配設された樹脂層と、
を含み、
前記回路基板表面の前記半導体素子に対向する領域に於いては、前記導電層上のみに前記樹脂層が配設されていることを特徴とする回路基板。 - 前記導電層は銅(Cu)からなり、その表面には下層からニッケル(Ni)及び金(Au)の2層の金属層が形成されていることを特徴とする請求項1に記載の回路基板。
- 前記導電層上に配設された前記樹脂層は複数個に分割されて配設されていることを特徴とする請求項1又は2に記載の回路基板。
- 半導体素子が実装される回路基板であって、
前記回路基板の表面に設けられた接続用ビアと、
前記回路基板の前記表面の前記半導体素子に対向する領域に配設され、前記接続用ビアに電気的に接続された配線層と、
前記回路基板の前記表面の前記半導体素子に対向する領域に於いて前記配線層と離間して配設され、前記接続用ビアとは絶縁された少なくとも一つ以上の導電層と、
前記導電層毎に前記導電層の上面及び側面に配設された樹脂層と、
を含むことを特徴とする回路基板。 - 前記導電層は銅(Cu)からなり、その表面には下層からニッケル(Ni)及び金(Au)の2層の金属層が形成されていることを特徴とする請求項4に記載の回路基板。
- 半導体素子と、
前記半導体素子を実装し、前記半導体素子に対向する領域に配設された配線層、前記半導体素子に対向する領域に於いて前記配線層と離間して配設された導電層、及び前記導電層上に配設された樹脂層を有する回路基板と、
前記回路基板と前記半導体素子との間に配設された接着部材と、
を含み、
前記回路基板表面の前記半導体素子に対向する領域に於いては、前記導電層上のみに前記樹脂層が配設されていることを特徴とする半導体装置。 - 前記導電層は銅(Cu)からなり、その表面には下層からニッケル(Ni)及び金(Au)の2層の金属層が形成されていることを特徴とする請求項6に記載の半導体装置。
- 前記導電層上に配設された前記樹脂層は複数個に分割されて配設されていることを特徴とする請求項6又は7に記載の半導体装置。
- 半導体素子と、
前記半導体素子を実装する回路基板と、
前記回路基板と前記半導体素子との間に配設された接着部材と、
を含み、
前記回路基板は、前記回路基板の表面に設けられた接続用ビアと、前記回路基板の前記表面の前記半導体素子に対向する領域に配設され、前記接続用ビアに電気的に接続された配線層と、前記回路基板の前記表面の前記半導体素子に対向する領域に於いて前記配線層と離間して配設され、前記接続用ビアとは絶縁された少なくとも一つ以上の導電層と、前記導電層毎に前記導電層の上面及び側面に配設された樹脂層とを有することを特徴とする半導体装置。
- 前記導電層は銅(Cu)からなり、その表面には下層からニッケル(Ni)及び金(Au)の2層の金属層が形成されていることを特徴とする請求項9に記載の半導体装置。
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TW201025462A (en) * | 2008-12-17 | 2010-07-01 | United Test Ct Inc | Semiconductor device and method for fabricating the same |
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US20120085575A1 (en) * | 2010-10-08 | 2012-04-12 | Nobuhiro Yamamoto | Electronic Apparatus Manufacturing Method, Electronic Component, and Electronic Apparatus |
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Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS60262430A (ja) | 1984-06-08 | 1985-12-25 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP3452678B2 (ja) * | 1995-03-03 | 2003-09-29 | 三菱電機株式会社 | 配線構成体の製造方法 |
JP2770821B2 (ja) | 1995-07-27 | 1998-07-02 | 日本電気株式会社 | 半導体装置の実装方法および実装構造 |
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JP2001313314A (ja) * | 2000-04-28 | 2001-11-09 | Sony Corp | バンプを用いた半導体装置、その製造方法、および、バンプの形成方法 |
JP2003124387A (ja) * | 2001-10-10 | 2003-04-25 | Sony Corp | 半導体装置及び該半導体装置に使用されるプリント基板 |
JP2003188210A (ja) * | 2001-12-18 | 2003-07-04 | Mitsubishi Electric Corp | 半導体装置 |
JP3889311B2 (ja) * | 2002-05-17 | 2007-03-07 | 三菱電機株式会社 | プリント配線板 |
US6919642B2 (en) * | 2002-07-05 | 2005-07-19 | Industrial Technology Research Institute | Method for bonding IC chips to substrates incorporating dummy bumps and non-conductive adhesive and structures formed |
JP3908689B2 (ja) * | 2003-04-23 | 2007-04-25 | 株式会社日立製作所 | 半導体装置 |
WO2004097916A1 (ja) * | 2003-04-30 | 2004-11-11 | Fujitsu Limited | 半導体装置の製造方法、半導体ウエハおよび半導体装置 |
JP2004342988A (ja) * | 2003-05-19 | 2004-12-02 | Shinko Electric Ind Co Ltd | 半導体パッケージの製造方法、及び半導体装置の製造方法 |
JP3916593B2 (ja) | 2003-07-11 | 2007-05-16 | シャープ株式会社 | Icモジュールの製造方法、icモジュール、及びicカード |
US7008820B2 (en) * | 2004-06-10 | 2006-03-07 | St Assembly Test Services Ltd. | Chip scale package with open substrate |
JP2006032872A (ja) | 2004-07-22 | 2006-02-02 | Sony Corp | 回路基板及び半導体装置 |
JP4058642B2 (ja) * | 2004-08-23 | 2008-03-12 | セイコーエプソン株式会社 | 半導体装置 |
JP2006253315A (ja) * | 2005-03-09 | 2006-09-21 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP2008263234A (ja) * | 2008-07-17 | 2008-10-30 | Hitachi Chem Co Ltd | 半導体チップ搭載基板及び半導体パッケージ、並びにそれらの製造方法 |
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