CN101128087A - 电路衬底和半导体器件 - Google Patents

电路衬底和半导体器件 Download PDF

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Publication number
CN101128087A
CN101128087A CNA2007100847126A CN200710084712A CN101128087A CN 101128087 A CN101128087 A CN 101128087A CN A2007100847126 A CNA2007100847126 A CN A2007100847126A CN 200710084712 A CN200710084712 A CN 200710084712A CN 101128087 A CN101128087 A CN 101128087A
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circuitry substrate
conductive layer
semiconductor element
semiconductor device
layer
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CNA2007100847126A
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CN101128087B (zh
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西村隆雄
合叶和之
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Socionext Inc
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Fujitsu Ltd
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Abstract

本发明提供一种用于提高半导体器件的可靠性和效率的半导体衬底和半导体器件。在要以倒装芯片方法安装半导体元件的半导体衬底中，至少一个岛形导电层和布线层选择性地设置在要安装半导体元件的元件安装区上，并且在岛形导电层上设置绝缘树脂层。在元件安装区，通过粘附材料将半导体元件固定到电路衬底以制造半导体器件。这样，抑制了半导体器件内部的布线层的分层，并抑制了电极的损坏。从而实现了具有高可靠性的电路衬底和具有该电路衬底的半导体器件。

Description

电路衬底和半导体器件
技术领域
本发明涉及电路衬底和半导体器件，尤其涉及这样一种电路衬底和半导体器件，其中半导体元件以面朝下结构的倒装芯片方法连接至该电路衬底，以及在该半导体器件中半导体元件以面朝下结构的倒装芯片方法连接至该电路衬底。
背景技术
当将半导体元件安装到电路衬底，制造半导体器件时，半导体元件可以以面朝下结构的倒装芯片方法安装至电路衬底，其中作为一种半导体元件安装结构，半导体元件的主表面面向电路衬底。
为了实现这种结构，使用这样一种方法(例如，在日本未审查的专利申请公开No.9-97816中所公开的)：向半导体元件施加载荷，该半导体元件具有朝向电路衬底的凸块，该电路衬底具有安装焊盘，用设置在凸块与安装焊盘之间的粘合剂使凸块与安装焊盘对准从而使凸块与安装焊盘接触；在凸块与安装焊盘接触时，通过加热使粘合剂固化，将半导体元件固定至电路衬底，以制造半导体器件。
在通过这种方法制造的半导体器件中，通过在半导体元件与电路衬底之间提供粘合剂将半导体元件固定到电路衬底，并且保持半导体元件的凸块紧压着电路衬底的安装焊盘的状态。因此，保持了凸块与安装焊盘的机械接触，同时也实现并保持了凸块与安装焊盘的电接触。
在一些情况下，除了布线图案和安装焊盘之外，在要安装半导体元件的电路衬底的区域(以下称为元件安装区)还设置有固体图案(例如，参见日本未审查的专利申请公开No.2003-338666)。
已经公开设置这种固体图案能增加电路衬底的硬度，并提高半导体器件的可靠性；另外，将固体图案的表面镀镍(Ni)、金(Au)能增加固体图案的硬度，从而进一步提高电路衬底的可靠性。
也已经提出，在电路衬底的元件安装区设置布线图案和虚拟图案来消除图案密度的不均匀性，以防止由于热膨胀系数不同导致的电路衬底的翘曲(例如，在日本未审查的专利申请公开No.2006-32872中)。
在上述现有技术的情况下，将布线图案和虚拟图案镀金(Au)以提高抗腐蚀性。然而，由于镀金(Au)层与粘合剂具有低接触性能，不能获得足够的触点压力。因此，难以保持布线图案与半导体元件的连接端子之间的接触。在现有技术的情况下，为了解决该问题，虚拟图案具有分支形状以形成小突出物、即多个凹陷和凸起，以通过固着效果增加触点压力。
如上所述，通常在如金(Au)这样的金属和粘合剂之间提供低的触点压力。因此，在安装之后，有可能在粘合剂与设置在虚拟图案和固体图案表面上的镀金(Au)层之间的界面处发生分层。
因此，难以保持半导体元件的凸块紧压着电路衬底的安装焊盘的状态，也不能保持凸块与安装焊盘之间的满意的电连接。尤其是当把半导体器件放在高温和高湿度的环境中时，分层进一步发展，因此不能获得预期的可靠性。
可以考虑一种将绝缘树脂层设置在虚拟图案(固体图案)上的方法，其中绝缘树脂层与粘合剂具有高接触性能。当虚拟图案(固体图案)在元件安装区具有大的面积时，绝缘树脂层也具有大的面积。
绝缘树脂层具有大的面积，因此具有大的弹性恢复力。所以，当把半导体元件安装到电路衬底时，如果在元件安装区存在具有大面积的绝缘树脂层，即使向半导体元件施加连接载荷，绝缘树脂层的弹性恢复力超过连接载荷，使得半导体元件的凸块与电路衬底的安装焊盘之间的连接不牢固。
如果将增大的载荷施加到半导体元件以使连接过程可靠，则可能损坏在半导体元件中形成凸块的部分处的内部布线或电路元件。
发明内容
为了解决上述问题，本发明的目的是提供一种具有高可靠性的电路衬底的结构以及包括该电路衬底的半导体器件，以防止电极之间的分层和半导体元件的损坏。
为了实现上述目的，根据本发明，提供一种电路衬底，其中半导体元件被安装至该电路衬底。该电路衬底包括：布线层，设置在该电路衬底表面上与该半导体元件相对的区域；导电层，设置在该电路衬底表面上与该半导体元件相对的区域且远离该布线层；以及树脂层，设置在该导电层上。
为了实现上述目的，根据本发明，提供一种半导体器件。该半导体器件包括：半导体元件；电路衬底，在该电路衬底上安装该半导体元件，该电路衬底包括设置在与该半导体元件相对的区域的布线层、设置在与该半导体元件相对的区域且远离该布线层的导电层、以及设置在该导电层上的树脂层；以及粘附材料，设置在该电路衬底与该半导体元件之间。
从以下描述中，通过结合以示例方式示出的本发明的优选实施例的附图，本发明的上述和其它目的、特征以及优点将变得显而易见。
附图说明
图1A示出了根据本发明第一实施例的电路衬底的平面图；图1B示出当将半导体元件安装到电路衬底时得到的主要部分的横截面图。
图2示出在用于将半导体元件安装到电路衬底的过程的第一阶段中使用的主要部分的横截面图。
图3示出在用于将半导体元件安装到电路衬底的过程的第二阶段中使用的主要部分的横截面图。
图4示出在用于将半导体元件安装到电路衬底的过程的第三阶段中使用的主要部分的横截面图。
图5示出根据本发明的半导体器件的主要部分的横截面图。
图6A示出根据本发明第二实施例的电路衬底的平面图；图6B示出当将半导体元件安装到电路衬底时得到的主要部分的横截面图。
图7A示出根据本发明第三实施例的电路衬底的平面图；图7B示出当将半导体元件安装到电路衬底时得到的主要部分的横截面图。
图8A示出根据本发明第四实施例的电路衬底的平面图；图8B示出当将半导体元件安装到电路衬底时得到的主要部分的横截面图。
图9A示出根据本发明第五实施例的电路衬底的平面图；图9B示出当将半导体元件安装到电路衬底时得到的主要部分的横截面图。
具体实施方式
下面参照附图详细描述本发明的各实施例。
第一实施例
下面描述根据本发明第一实施例的电路衬底和结构，其中在该电路衬底上安装半导体元件以制造半导体器件。
图1A示出根据第一实施例的电路衬底100的结构，图1B示出在电路衬底100上以倒装芯片方法(面朝下)安装半导体元件21来制造半导体器件200的情形。图1B是对应于沿图1A中的线A-A取得的横截面图。
在图1A中，在电路衬底100中由虚线圈起的矩形区域S表示当安装半导体元件21时，由半导体元件21占据的平面位置。以下，将矩形区域S称为元件安装区S。
在组成电路衬底100的绝缘基底部件10的表面上，将多个布线层11选择性地设置在元件安装区S的四边。
在元件安装区S中，在区域S的周界附近为多个布线层11提供宽电极连接部分12。半导体元件21的电极连接至宽电极连接部分12。
为了增加电路衬底100的布线密度，布线11的部分11a延伸至元件安装区S的中心附近，并通过用于层间连接的通孔13与形成于后表面或绝缘基底部件10内部的布线层(未示出)电连接。布线层11a不是必须以固定斜度或均匀密度延伸或布置在元件安装区S中。
在本实施例中，岛形导电层14选择性地设置在具有低布线层11a排列密度的区域中并远离布线层11a。岛形导电层14通常比布线层11宽，其形状不具体规定。如果需要，岛形导电层14电连接至电路衬底100的接地电位部分。在如上所述现有技术的一些情况下，将岛形导电层14称为虚拟图案(日本未审查的专利申请公开No.2006-32872)。
在本实施例中，在岛形导电层14的表面上设置绝缘树脂层15。在元件安装区S的外部设置抗焊层16以覆盖绝缘基底部件10和布线层11b的表面，其中布线层11b向元件安装区S的外部延伸且稍微远离元件安装区S。
在具有上述结构的电路衬底100中，绝缘基底部件10由例如玻璃环氧树脂、玻璃双马来酰亚胺-三嗪(glass-bismaleimide-triazine，玻璃-BT)树脂或聚酰亚胺的有机绝缘树脂制成。绝缘基底部件10可以由例如陶瓷或玻璃的无机绝缘材料制成。
绝缘基底部件10根据其用途可具有单侧布线结构、双侧布线结构或多层布线结构。电路衬底100也称为布线衬底或内插板。
布线层11、宽电极连接部分12和岛形导电层14由例如铜(Cu)制成，它们的表面按照从下层起的顺序镀有镍(Ni)层和金(Au)层两层。通过电路衬底100的整个表面上的形成物的结合以及选择蚀刻(所谓的光刻)，或通过选择电镀方法使这些金属层形成在一起，以具有7至20μm的厚度。
如上所述，将绝缘树脂层15设置在选择性地设置的岛形导电层14上。
绝缘树脂层15能够由与组成抗焊层16的材料相同的材料制成。这些层能够由发展型抗蚀剂材料、热固性抗蚀剂材料或紫外线固化抗蚀剂材料制成。更具体地，这些层能够由例如环氧树脂、丙烯酸树脂或聚酰亚胺树脂等树脂、或这些树脂的混合物制成。绝缘树脂层15和抗焊层16可以由不同材料制成。
通过在目标层上形成的这些层的结合以及应用至目标层的光刻处理，能够选择性地设置绝缘树脂层15和抗焊层16。这些层的厚度约为5至30μm。
图1B示出以面朝下的倒装芯片方法将半导体元件21安装至具有上述结构的电路衬底100以制造半导体器件200的情形。
在半导体器件200中，用填充在半导体元件21与电路衬底100之间的粘附材料(粘合剂)31，将半导体元件21固定到电路衬底100。粘附材料31也称为底部填充材料。
在半导体元件21中，所谓的晶片加工被应用于由硅(Si)、砷化镓(GaAs)等制成的半导体基底部件的一个主表面，以形成具有例如晶体管的有源元件、例如电容器的无源元件、以及用于连接这些元件的布线层的电子电路。
在形成有电子电路的半导体基底部件的一个主表面上，在连接至布线层的电极焊盘22上设置凸块(凸电极)，作为外部连接电极23。电极焊盘22由具有铝(Al)或铜作为主要成分的材料制成。
用作外部连接电极23的凸块由金(Au)、铜(Cu)、金铜合金、焊料等制成，并通过使用金属线的球形键合方法、电镀方法、印刷方法、转移方法和其它方法形成。
粘附材料31是由环氧树脂、聚酰亚胺树脂、丙烯酸树脂等制成的热固性粘合剂，并且是绝缘体或各向异性的导体。在固化前，粘附材料31为糊状或片状。
在粘合处理后，粘附材料31从半导体元件21的侧面到抗焊层16的侧面形成带(fillet)32。
在具有上述结构的半导体器件200中，如上所述，将布线层11和岛形导电层14选择性地设置在电路衬底100中的元件安装区S。
岛形导电层14的选择性排布改善了电路衬底100上的导电部分的密度不均匀性，并增加了电路衬底100的硬度，从而减小了电路衬底100的翘曲或向下弯曲。
在半导体器件200中，由于绝缘树脂层15设置在岛形导电层14的表面上，所以粘附材料31接触绝缘树脂层15。岛形导电层14和粘附材料31通过绝缘树脂层15牢固连接，所以在岛形导电层14与粘附材料31之间不出现分层。
在相邻的布线层11之间以及布线层11与岛形导电层14之间，绝缘基底部件10的表面接＞？触粘附材料31。当绝缘基底部件10由有机材料制成时，绝缘基底部件10和粘附材料31之间的接触性能令人满意。
由于根据布线层11和岛形导电层14的厚度(高度)，在相邻的布线层11之间以及布线层11与岛形导电层14之间形成不平坦部分，所以随着粘附材料31接触面积的增加，出现所谓的固着效果，从而防止布线层11与粘附材料31之间的分层。
如上所述，根据本实施例，在粘附材料31与布线层11和岛形导电层14的界面处不出现分层；并且在电路衬底100的电极连接部分12与半导体元件21的外部连接电极23之间能够保持令人满意的机械接触和令人满意的电接触。
仅在岛形导电层14上选择性地设置绝缘树脂层15。
因此，在元件安装区S中由绝缘树脂层15占据的面积实际上很小，所以在将半导体元件21安装到电路衬底100时产生的绝缘树脂层15的弹性恢复力很小。
因此，即使在载荷不很大的情况下，施加到半导体元件21的载荷超过绝缘树脂层15的弹性恢复力，电路衬底100的电极连接部分12与半导体元件21的外部连接电极23能以稳定状态连接。
由于施加到半导体元件21的载荷不需要很大，所以位于设置有半导体元件21的外部连接电极23的部分处的内部布线或功能元件没有被损坏。
因此，即使当施加载荷和热量通过热固性粘附材料31使半导体元件21紧压着电路衬底100时，没有损坏半导体元件21的内部布线或内部元件，并且电路衬底100的电极连接部分12与半导体元件21的外部连接电极23可靠性连接。换言之，半导体器件200具有高可靠性。
接下来，参照图2至图5描述包括用于将半导体元件21安装到电路衬底100的过程的半导体器件的制造方法。
图2示出在电路衬底100上放置半导体元件21的情形。
如上所述，将半导体元件21以面朝下的倒装芯片方法安装到电路衬底100。
在安装半导体元件21之前，将糊状或片状粘附材料31提供并布置到电路衬底100的元件安装区S中。分散方法(dispenser method)、印刷方法或粘合方法能用作提供方法。
在电路衬底100的另一个主表面(其是与安装有半导体元件21的表面相反的表面)上设置多个电极焊盘(电极连接盘)17，其中电路衬底100的外部连接端子要设置于电极焊盘17上。
如果需要，在多个电极焊盘17的周围设置布线层11c。由抗焊层16覆盖布线层11c。
通过布线层和形成于电路衬底100内部的层间连接部分，选择性地连接设置于电路衬底100的两个主表面上的布线层、电极焊盘以及其它部分。
由于参照图1B已经描述了电路衬底100的其它元件，因此，在此省略了对这些元件的描述。
通过预先加热的压合工具70，吸附并支撑在电极焊盘22上设有外部连接电极23的半导体元件21。加热温度设置为约150℃到250℃。
通过压合连接台(bonding stage)(未示出)吸附并支撑电路衬底100，如果需要，将电路衬底100和粘附材料31预加热。加热温度设置为约50℃到100℃。
面向电路衬底100放置半导体元件21；将半导体元件21的外部连接电极23设置于与电路衬底100的电极连接部分12相对应的位置；并且将半导体元件21以箭头所示方向向电路衬底100放下。
将半导体元件21放下至电路衬底100，以使半导体元件21的外部连接电极23与电路衬底100的电极连接部分12接触。
压合工具70向半导体元件21施加压力，以向半导体元件21的外部连接电极23施加载荷，其中该外部连接电极23已经与电路衬底100的电极连接部分12接触。例如，载荷设置为5至50荷重/凸块(gf/bump)。
当施加载荷时，粘附材料31在半导体元件21与电路衬底100之间向外流动(即，向元件安装区S的外部流动)，并通过加热(温度约150℃至250℃)使其固化。
如上所述当粘附材料31流动时，抗焊层16用作坝，以阻挡粘附材料31的不必要的流动。因此，粘附材料31形成稳定的带32。
图3示出了上述情形。
接着，释放压合工具70的吸力，使半导体元件21与压合工具70分离，并升高压合工具70(未示出)。
在加热室中，对电路衬底1 00和已经安装并固定至电路衬底100的半导体元件21进行热处理。粘附材料31完全固化，并完成将半导体元件21安装至电路衬底100的过程。
图4示出了上述状态。
在该处理过程中，设定加热温度为例如120℃至180℃，并设定加热时间为例如约30至90分钟。
在图3所示的过程中，例如，当粘附材料31以80％的固化率固化时，可以省略图4所示的过程。
接着，通过回流方法在设置于电路衬底100的后表面上的电极焊盘17上形成用作外部连接端子18的焊球，以制造具有球栅阵列(BGA)封装结构的半导体器件200。
图5示出了上述情形。
可以省略焊球的设置，以制造具有触点阵列(LGA)封装结构的半导体器件200，其中电极焊盘17作为外部连接端子。外部连接端子的形状可以是例如导线形或管脚形的其它形状。
外部连接端子18设置在与安装有半导体元件21的表面相反的电路衬底100的主表面上，但不限于此。如果需要，外部连接端子18可以设置在安装有半导体元件21的主表面上，或电路衬底100的侧面上。
下面描述本发明的第二实施例。
第二实施例
下面描述根据本发明第二实施例的电路衬底和结构，其中在该电路衬底上安装半导体元件以制造半导体器件。图6A示出根据第二实施例的电路衬底101的结构，图6B示出将半导体元件21以倒装芯片方法(面朝下)安装至电路衬底101上以制造半导体器件201的情形。图6B是对应于沿图6A中的线A-A取得的横截面图。
在根据第二实施例的半导体器件201中，在电路衬底101的绝缘基底部件10上选择性设置的岛形导电层14中提供暴露部分14a，以露出岛形导电层14的上边缘表面。在岛形导电层14的其它部分上选择性地设置绝缘树脂层15。
绝缘树脂层15具有比岛形导电层14小的面积。暴露部分14a的宽度与布线层11的宽度大致相同。
除了如何在岛形导电层14上设置绝缘树脂层15之外，第二实施例具有与第一实施例相同的结构，因此，省略相同结构的详细描述。
在具有上述结构的半导体器件201中，在电路衬底101的元件安装区S上，选择性地设置布线层11和岛形导电层14。
岛形导电层14的选择性排布改善了电路衬底101上的导电部分的密度不均匀性，并增加了电路衬底101的硬度，从而减小了电路衬底101的翘曲或向下弯曲。
在半导体器件201中，由于将绝缘树脂层15设置在岛形导电层14的表面上，所以粘附材料31接触绝缘树脂层15。岛形导电层14和粘附材料31通过绝缘树脂层15牢固连接，因此在岛形导电层14和粘附材料31之间不出现分层。
由于在岛形导电层14的表面上选择性地局部设置绝缘树脂层15，其面积小于半导体器件201中的岛形导电层14的面积，所以在岛形导电层14与绝缘树脂层15之间形成台阶。
因此，当在包括绝缘树脂层15的绝缘基底部件10上放置粘附材料31时，由于台阶导致的接触面积的增加，所以进一步提高了粘附材料31与绝缘树脂层15的接触性能。
由于在上述结构中限制了局部设置于岛形导电层14上的绝缘树脂层15，所以当将半导体元件21安装到电路衬底101时，绝缘树脂层15的弹性恢复力被抑制到较低水平。
因此，即使在载荷不是很大的情况下，施加到半导体元件21的载荷超过绝缘树脂层15的弹性恢复力，所以电路衬底101的电极连接部分12与半导体元件21的外部连接电极23能以稳定状态连接。
由于施加到半导体元件21的载荷不需要很大，所以位于设置有半导体元件21的外部连接电极23的部分处的内部布线或功能元件没有被损坏。
因此，即使当施加载荷和热量通过热固性粘附材料31使半导体元件21紧压着电路衬底101时，没有损坏半导体元件21的内部布线或内部元件，并且电路衬底101的电极连接部分12与半导体元件21的外部连接电极23  靠性连接。换言之，半导体器件200具有高可靠性。
接下来描述本发明的第三实施例。
第三实施例
下面描述根据本发明第三实施例的电路衬底和结构，其中在该电路衬底上安装半导体元件以制造半导体器件。
图7A示出根据第三实施例的电路衬底102的结构，图7B示出将半导体元件21以倒装芯片方法(面朝下)安装至电路衬底102上以制造半导体器件202的情形。图7B是对应于沿图7A中的线A-A取得的横截面图。
在根据第三实施例的半导体器件202中，绝缘树脂层15以格栅方式被分割，并设置在岛形导电层14上，其中岛形导电层14选择性地设置于电路衬底102的绝缘基底部件10上。换言之，每个绝缘树脂层15被分割成多块，并设置在一个岛形导电层14上。如果岛形导电层14具有小的面积，则可能不允许将绝缘树脂层15的多块放置在岛形导电层14上。
除了如何在岛形导电层14上设置绝缘树脂层15之外，第三实施例具有与第一实施例相同的结构，因此，省略相同结构的详细描述。
在具有上述结构的半导体器件202中，在电路衬底102的元件安装区S上，选择性地设置布线层11和岛形导电层14。
岛形导电层14的选择性排布改善了电路衬底102上的导电部分的密度不均匀性，并增加了电路衬底102的硬度，从而减小了电路衬底102的翘曲或向下弯曲。
在半导体器件202中，由于将绝缘树脂层15设置在岛形导电层14的表面上，所以粘附材料31接触绝缘树脂层15。岛形导电层14和粘附材料31通过绝缘树脂层15牢固连接，所以在岛形导电层14和粘附材料31之间不出现分层。
由于在半导体器件202中，每个绝缘树脂层15被分割成多块，并设置在岛形导电层14上，所以在树脂层的多块之间形成台阶。
因此，当在包括绝缘树脂层15的绝缘基底部件10上放置粘附材料31时，由于台阶导致的接触面积的增加，所以提高了粘附材料31与绝缘树脂层15的接触性能。
由于台阶导致粘附材料31能在多块之间流动，所以由于所谓的固着效果使得粘附材料31与绝缘树脂层15的接触性能进一步提高。
以格栅方式分割绝缘树脂层15以形成多个台阶。本发明并不局限于这种情况。可以以线和空间的方式分割绝缘树脂层15，或将其分割成具有任何所需形状的部分。可选地，在绝缘树脂层15中可平行地形成多个凹陷。
绝缘树脂层15的分割线可以停止于绝缘树脂层15的厚度方向的中部，而不到达岛形导电层14的表面。
由于在上述结构中将绝缘树脂层15分割成多块，所以在将半导体元件21安装至电路衬底102时，绝缘树脂层15的弹性恢复力受到限制。
因此，即使在载荷不是很大的情况下，施加到半导体元件21的载荷超过绝缘树脂层15的弹性恢复力，所以电路衬底102的电极连接部分12与半导体元件21的外部连接电极23能以稳定状态连接。
由于施加到半导体元件21的载荷不需要很大，所以位于设置有半导体元件21的外部连接电极23的部分处的内部布线或功能元件没有被损坏。
因此，即使当施加载荷和热量通过热固性粘附材料31使半导体元件21紧压着电路衬底102时，没有损坏半导体元件21的内部布线或内部元件，并且电路衬底102的电极连接部分12与半导体元件21的外部连接电极23可靠性连接。换言之，半导体器件202具有高可靠性。
接下来描述本发明的第四实施例。
第四实施例
下面描述根据本发明第四实施例的电路衬底和结构，其中在该电路衬底上安装半导体元件以制造半导体器件。
图8A示出根据第四实施例的电路衬底103的结构，图8B示出将半导体元件21以倒装芯片方法(面朝下)安装至电路衬底103上以制造半导体器件203的情形。图8B是对应于沿图8A中的线A-A取得的横截面图。
在根据第四实施例的半导体器件203中，在选择性地设置于电路衬底103的绝缘基底部件10上的岛形导电层14上设置绝缘树脂层15，以同样覆盖岛形导电层14的侧面。换言之，在一个岛形导电层14上设置各自的绝缘树脂层15，以覆盖岛形导电层14的上面和侧面，并到达绝缘基底部件10。
除了如何在岛形导电层14上设置绝缘树脂层15之外，第四实施例也具有与第一实施例相同的结构，因此，省略相同结构的详细描述。
在具有上述结构的半导体器件203中，在电路衬底103的元件安装区S上，选择性地设置布线层11和岛形导电层14。
岛形导电层14的选择性排布改善了电路衬底103上的导电部分的密度不均匀性，并增加了电路衬底103的硬度，从而减小了电路衬底103的翘曲或向下弯曲。
在半导体器件203中，由于将绝缘树脂层15设置在岛形导电层14的表面上，所以粘附材料31接触绝缘树脂层15。岛形导电层14和粘附材料31通过绝缘树脂层15牢固连接，并且在岛形导电层14与粘附材料31之间不出现分层。
在具有上述结构的半导体器件203中，设置在岛形导电层14上的绝缘树脂层15也覆盖岛形导电层14的侧面，并到达绝缘基底部件10的表面。
因此，当在包括绝缘树脂层15的绝缘基底部件10上放置粘附材料31时，由于岛形导电层14的侧面的接触面积的增加，进一步提高了粘附材料31与绝缘树脂层15的接触性能。
由于在上述结构中绝缘树脂层15的面积增加的不是很大，所以在将半导体元件21安装到电路衬底103时绝缘树脂层15的弹性恢复力受到限制。
因此，即使在载荷不是很大的情况下，施加到半导体元件21的载荷超过绝缘树脂层15的弹性恢复力，所以电路衬底103的电极连接部分12与半导体元件21的外部连接电极23能以稳定状态连接。
由于施加到半导体元件21的载荷不需要很大，所以位于设置有半导体元件21的外部连接电极23的部分处的内部布线或功能元件没有被损坏。
因此，即使当施加载荷和热量通过热固性粘附材料31使半导体元件21紧压着电路衬底103时，没有损坏半导体元件21的内部布线或内部元件，并且电路衬底103的电极连接部分12与半导体元件21的外部连接电极23可靠性连接。换言之，半导体器件203具有高可靠性。
接下来描述本发明的第五实施例。
第五实施例
下面描述根据本发明第五实施例的电路衬底和结构，其中在该电路衬底上安装半导体元件以制造半导体器件。
图9A示出根据第五实施例的电路衬底104的结构，图9B示出将半导体元件21以倒装芯片方法(面朝下)安装至电路衬底104上以制造半导体器件204的情形。图9B是对应于沿图9A中的线A-A取得的横截面图。
在根据第五实施例的半导体器件204中，在岛形导电层14上设置比第一实施例中的绝缘树脂层薄的绝缘树脂层15，其中岛形导电层14选择性地设置于电路衬底104的绝缘基底部件10上。换言之，在岛形导电层14上设置具有相对较小厚度的绝缘树脂层15。
从绝缘基底部件10的表面10a到绝缘树脂层15的表面15a的高度比设置在元件安装区S的周界的抗焊层16的高度低。
更具体地，在本实施例中绝缘树脂层15的厚度设置为2至10μm，而在第一至第四实施例中，其厚度为5至30μm。
除了如何在岛形导电层14上设置绝缘树脂层15之外，第五实施例也具有与第一实施例相同的结构，因此省略相同结构的详细描述。
在具有上述结构的半导体器件204中，在电路衬底104的元件安装区S上，选择性地设置布线层11和岛形导电层14。
岛形导电层14的选择性排布改善了电路衬底104上的导电部分的密度不均匀性，并增加了电路衬底104的硬度，从而减小了电路衬底104的翘曲或向下弯曲。
在半导体器件204中，由于将绝缘树脂层15设置在岛形导电层14的表面上，所以粘附材料31接触绝缘树脂层15。岛形导电层14和粘附材料31通过绝缘树脂层15牢固连接，所以在岛形导电层14与粘附材料31之间不出现分层。
由于在上述结构中绝缘树脂层15制造得较薄，所以在将半导体元件21安装到电路衬底104时，绝缘树脂层15的弹性恢复力被限制到较低水平。
因此，即使在载荷不是很大的情况下，施加到半导体元件21的载荷超过绝缘树脂层15的弹性恢复力，所以电路衬底104的电极连接部分12与半导体元件21的外部连接电极23能以稳定状态连接。
由于施加到半导体元件21的载荷不需要很大，所以位于设置有半导体元件21的外部连接电极23的部分处的内部布线或功能元件没有被损坏。
因此，即使当施加载荷和热量通过热固性粘附材料31使半导体元件21紧压着电路衬底104时，没有损坏半导体元件21的内部布线或内部元件，并且电路衬底104的电极连接部分12与半导体元件21的外部连接电极23可靠性连接。
此外，由于绝缘树脂层15制造得较薄，绝缘树脂层15与半导体元件21之间的空间扩大，从而增加粘附材料31的流动性。因此防止在粘附材料31中产生空隙或减少这种空穴，并防止产生或减少没有被填充粘附材料31的部分。
因此，增加了半导体器件204的可靠性。
与现有技术对比：
下面将描述本发明与现有技术对比的优点。
在潮湿/回流敏感性测试以及高温高压测试(autoclave test)中对根据现有技术的半导体器件A和根据本发明原理的半导体器件B进行了环境评估，以比较半导体器件的可靠性，其中半导体器件A具有岛形导电层14，但是在岛形导电层14上不具有绝缘树脂层15，而半导体器件B具有岛形导电层14，而且在岛形导电层14上具有绝缘树脂层15。
作为要安装到半导体器件A和半导体器件B的半导体元件21，使用具有如下尺寸的逻辑集成电路元件：6.57mm乘6.57mm的面积、50μm的电极焊盘节距(最小节距)、414电极焊盘、以及由金(Au)制成的外部连接端子。
除了绝缘树脂层15外，使用具有图1所示的结构的电路衬底。作为绝缘基底部件10，使用由玻璃-BT制成的四层增强布线衬底。
将岛形导电层14设置为具有接地电位。糊状热固性绝缘环氧树脂用作粘附材料31。
在半导体器件A中，在岛形导电层14上没有设置绝缘树脂层15，而是在岛形导电层14上首先设置镍(Ni)层，接着设置金(Au)层。通过电镀方法形成这些金属层。
相反，在半导体器件B中，在岛形导电层14上设置由与抗焊材料相同的材料制成的绝缘树脂层15，然后在暴露的布线图案、电极连接部分以及岛形导电层14上首先设置镍(Ni)层，接着设置金(Au)层。
通过粘合剂介入型热压焊方法(adhensive-intervening-typethermocompression bonding method)，将半导体器件A和B以倒装芯片方法安装至电路衬底。
在安装条件下，将载荷设置为17荷重/凸块(gf/bump)，半导体元件的加热温度设置为280℃，以及电路衬底的加热温度设置为70℃。压合时间为5秒。
用前述方法制造具有与图5所示的结构相似的每个半导体器件A和B的10个样品，并比较它们的性能。
首先描述潮湿/回流敏感性测试的结果。
将每个半导体器件A和B的10个样品放在温度为30℃以及相对湿度为80％的环境中停留120小时，接着在红外线回流装置中在260℃的峰值温度下进行热处理。
接着，将10个样品放在温度为30℃以及相对湿度为80％的环境中停留96小时，接着在红外线回流装置中在260℃的峰值温度下进行热处理。
对样品的内部进行视觉检查，并进一步检查它们的电气特性。
在样品的内部视觉检查中，通过使用超声波缺陷检测器，检测粘附材料31与半导体元件21之间的界面处以及粘附材料31与电路衬底的基底部件10、岛形导电层14、布线图案11以及外部连接电极23之间的界面处是否发生分层。
在样品的内部视觉检查中，在每个半导体器件A和B的10个样品的任何一个样品中均没有发现缺陷。
在潮湿/回流敏感性测试之后，进行高温高压测试。其结果将在下面描述。在高温高压测试中。将样品放在温度为121℃以及相对湿度为99.8％的环境中停留预定的时间段。
接着，检查样品的电气特性。如果在电气特性检测中发现缺陷，则对样品的内部进行视觉检查。
电气特性检测以及在该测试中的内部视觉检查使用的方法与在潮湿/回流敏感性测试中的方法相同。
在电气特性检测时，保持长达504个小时的半导体器件A的10个样品中以及保持长达840个小时的半导体器件B的10个样品中均没有发现缺陷。
在672个小时时在半导体器件A的10个样品的5个样品的电气特性中发现缺陷，以及在1008个小时时在半导体器件B的10个样品的2个样品的电气特性中发现缺陷。
在内部视觉检查时，在半导体器件A和B的电气特性方面有缺陷的所有样品中均发现分层。
在半导体器件A的样品中，在半导体元件21与半导体元件21的周界附近的粘附材料31之间的界面中，以及与岛形导电层14上面和附近的粘附材料31连接的界面中，均发现分层。
在半导体器件B的样品中，在半导体元件21与半导体元件21的转角附近的粘附材料31之间的界面中，发现分层。在岛形导电层14上没有出现粘附材料31的分层。
从上述的环境评估中可以确定，根据本发明的半导体器件B比具有传统结构的半导体器件A具有更高的可靠性。
本发明的第一到第五实施例中的任一个可被选择和组合。
本发明不限于这种情况，即将上述第一至第五实施例之一应用于设置在电路衬底中的元件安装区的所有多个岛形导电层14。本发明可以应用于只具有较大面积的岛形导电层14。
此外，第一至第五实施例之一可应用于设置在多个岛形导电层14上的绝缘树脂层15中的一个。
在根据本发明的电路衬底中，由于岛形导电层分离地设置在电路衬底中的元件安装区上并远离布线层，所以改善了电路衬底中的导电部分的密度不均匀性，并增加了电路衬底的硬度，从而减小电路衬底的翘曲或向下弯曲。
在根据本发明的电路衬底和半导体器件中，由于在电路衬底中的岛形导电层的表面上设置树脂层，所以用于固定半导体元件的粘附材料接触树脂层。在这种结构下，岛形导电层与粘附材料通过绝缘树脂层牢固连接，因此在岛形导电层与粘附材料之间不出现分层。
如上所述，根据本发明的实施例，防止了半导体器件内的布线层的分层，并防止了在电路衬底的电极连接部分与半导体元件的外部连接电极之间的连接缺陷。因此，可以实现电路衬底以及使用该电路衬底的半导体器件的高可靠性。
如实施例所示的前述内容只作为本发明的原理示例性说明。而且，由于所属领域技术人员能容易地对实施例做出多种更动与改变，因此，本发明不局限于所示和描述的具体结构和应用。可以认为所有适当的更动与等效变化均应涵盖在本发明所附的权利要求及其等效的范围中。

Claims (17)

1.一种电路衬底，在该电路衬底上安装半导体元件，该电路衬底包括：
布线层，设置在该电路衬底表面上与该半导体元件相对的区域；
导电层，设置在该电路衬底表面上与该半导体元件相对的区域且远离该布线层；
树脂层，设置在该导电层上。
2.如权利要求1所述的电路衬底，其中，在该电路衬底表面上与该半导体元件相对的区域，该树脂层仅设置在该导电层上面。
3.如权利要求1所述的电路衬底，其中，该导电层由铜制成，并且在该导电层的表面上，按照从下层起的顺序形成镍层和金层两个金属层。
4.如权利要求1所述的电路衬底，其中，设置在该导电层上的该树脂层也覆盖该导电层的侧面。
5.如权利要求1所述的电路衬底，其中，设置在该导电层上的该树脂层以分割成多块的方式设置。
6.如权利要求1所述的电路衬底，其中，设置在该导电层上的该树脂层具有比该导电层小的面积，以露出该导电层的上边缘表面。
7.如权利要求6所述的电路衬底，其中，该露出的上边缘表面具有与该布线层相同的宽度。
8.如权利要求1所述的电路衬底，其中，从组成该电路衬底的基底部件的表面到该树脂层的表面的高度比设置在所述区域的周界部分的抗焊层的高度低。
9.一种半导体器件，包括：
半导体元件；
电路衬底，在该电路衬底上安装该半导体元件，该电路衬底包括设置在与该半导体元件相对的区域的布线层、设置在与该半导体元件相对的区域且远离该布线层的导电层、以及设置在该导电层上的树脂层；以及
粘附材料，设置在该电路衬底与该半导体元件之间。
10.如权利要求9所述的半导体器件，其中，在该电路衬底表面上与该半导体元件相对的区域，该树脂层仅设置在该导电层上面。
11.如权利要求9所述的半导体器件，其中，该导电层由铜制成，并且在该导电层的表面上，按照从下层起的顺序形成镍层和金层两个金属层。
12.如权利要求9所述的半导体器件，其中，设置在该导电层上的该树脂层也覆盖该导电层的侧面。
13.如权利要求9所述的半导体器件，其中，设置在该导电层上的该树脂层以分割成多块的方式设置。
14.如权利要求9所述的半导体器件，其中，设置在该导电层上的该树脂层具有比该导电层小的面积，以露出该导电层的上边缘表面。
15.如权利要求14所述的半导体器件，其中，该露出的上边缘表面具有与该布线层相同的宽度。
16.如权利要求9所述的半导体器件，其中，从组成该电路衬底的基底部件的表面到该树脂层的表面的高度比设置在所述区域的周界部分的抗焊层的高度低。
17.如权利要求9所述的半导体器件，其中，该导电层具有接地电位。
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