JP3916593B2 - Icモジュールの製造方法、icモジュール、及びicカード - Google Patents
Icモジュールの製造方法、icモジュール、及びicカード Download PDFInfo
- Publication number
- JP3916593B2 JP3916593B2 JP2003273711A JP2003273711A JP3916593B2 JP 3916593 B2 JP3916593 B2 JP 3916593B2 JP 2003273711 A JP2003273711 A JP 2003273711A JP 2003273711 A JP2003273711 A JP 2003273711A JP 3916593 B2 JP3916593 B2 JP 3916593B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- wiring
- wirings
- solder resist
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
2 パッド電極
3 バンプ
4 基板
5 外部接続端子
6a,6b 配線
7a,7b ソルダーレジスト
8 異方性導電フィルム
9 導電粒子
10 ICモジュール
20 カード基材
21 凹陥部
22 アンテナコイル
Claims (12)
- 基板の一面上に複数の配線及び外部接続端子を形成する工程と、
ICチップのパッド電極又は前記外部接続端子にバンプを形成する工程と、
前記複数の配線にソルダーレジストを形成するレジスト形成工程と、
前記基板の前記一面側に導電部材を載置する工程と、
前記パッド電極及び外部接続端子を対向位置合わせする工程と、
前記ICチップの前記パッド電極が形成されている面と反対側の面を加熱及び加圧し、前記ICチップ及び基板を前記導電部材にて固着する工程と
を含むICモジュールの製造方法において、
前記レジスト形成工程は、前記ICチップに対向位置する複数の配線に各別にソルダーレジストを形成することを特徴とするICモジュールの製造方法。 - 前記レジスト形成工程は、前記配線の上面を覆うようにしてソルダーレジストを形成することを特徴とする請求項1に記載のICモジュールの製造方法。
- 前記レジスト形成工程は、前記配線上に離間して並設するようにしてソルダーレジストを形成することを特徴とする請求項1に記載のICモジュールの製造方法。
- 前記導電部材は導電粒子を含有し、
前記パッド電極及び外部接続端子は、該導電粒子及び前記バンプを介して電気的に接続されている
ことを特徴とする請求項1乃至3のいずれかひとつに記載のICモジュールの製造方法。 - 基板の一面上に複数の配線及び外部接続端子が形成され、該複数の配線にソルダーレジストが形成され、ICチップのパッド電極又は前記外部接続端子にバンプが形成され、前記基板に前記ICチップを導電部材を介してフリップチップ実装したICモジュールにおいて、
前記ICチップに対向位置する複数の配線に各別に前記ソルダーレジストが形成されていることを特徴とするICモジュール。 - 前記ソルダーレジストは、前記配線の上面を覆っていることを特徴とする請求項5に記載のICモジュール。
- 前記ソルダーレジストの前記配線の幅方向の寸法は、該配線の幅寸法よりも5μm以上30μm以下長いことを特徴とする請求項6に記載のICモジュール。
- 前記ソルダーレジストは、前記配線上に離間して並設されていることを特徴とする請求項5に記載のICモジュール。
- 前記ソルダーレジストの平面視形状は、円形、矩形、又は菱形であることを特徴とする請求項8に記載のICモジュール。
- 前記平面視形状の前記配線の幅方向の寸法は、該配線の幅寸法の少なくとも1/2倍であることを特徴とする請求項9に記載のICモジュール。
- 前記導電部材は導電粒子を含有し、
前記パッド電極及び外部接続端子は、該導電粒子及び前記バンプを介して電気的に接続されている
ことを特徴とする請求項5乃至10のいずれかひとつに記載のICモジュール。 - 請求項5乃至11のいずれかひとつに記載のICモジュールを備えることを特徴とするICカード。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003273711A JP3916593B2 (ja) | 2003-07-11 | 2003-07-11 | Icモジュールの製造方法、icモジュール、及びicカード |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003273711A JP3916593B2 (ja) | 2003-07-11 | 2003-07-11 | Icモジュールの製造方法、icモジュール、及びicカード |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005033142A JP2005033142A (ja) | 2005-02-03 |
JP3916593B2 true JP3916593B2 (ja) | 2007-05-16 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2003273711A Expired - Fee Related JP3916593B2 (ja) | 2003-07-11 | 2003-07-11 | Icモジュールの製造方法、icモジュール、及びicカード |
Country Status (1)
Country | Link |
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JP (1) | JP3916593B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007180900A (ja) * | 2005-12-28 | 2007-07-12 | Seiko Epson Corp | 水晶発振器及びその製造方法 |
JP5186741B2 (ja) | 2006-08-18 | 2013-04-24 | 富士通セミコンダクター株式会社 | 回路基板及び半導体装置 |
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2003
- 2003-07-11 JP JP2003273711A patent/JP3916593B2/ja not_active Expired - Fee Related
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JP2005033142A (ja) | 2005-02-03 |
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